The 9S12 A/D converter Huang Section ATD_10B8C Block User Guide

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1 The 9S2 A/D converter Huang Section ATD_B8C Block User Guide Analog/Digital Converters A -bit A/D converter is used to convert an input voltage The reference voltages are V RL = V and V RH = 5V What is the quantization level of the A/D converter? V = (V RH V RL )/2 b = 488 mv What is the dynamic range of the A/D converter? DR db = 62 b = 62 db If the value read from the A/D converter is x5a, what is the input voltage? Vin = V RL + [(V RH V RL )/2 b ]*ADvalue = V mv 346 = 6894 V The HCS2 has two -bit A/D converters (ATD and ATD) Each A/D converter has an 8-channel analog mulitplexer in front of it, so each channel can convert 8 analog inputs (but not at exactly the same time) ATD uses the eight bits of Port AD, called PAD through PAD7 Ports AD and AD of ATD are used by DBug-2 at startup to determine whether to execute DBug-2, or to run code from EEPROM of the bootloader ATD uses the eight bits of Port AD, called PAD8 through PAD5 (9S2DT256DGV3pdf) The HCS2 Analog/Digital Converter We will discuss only ATD ATD is identical ATD is an eight-channel -bit A/D converter The A/D converter can also be used in 8-bit mode There are eight inputs to the A/D converter The inputs are fed through a multiplexer to the single A/D converter There are inputs on the HCS2 for the reference voltages V RL and V RH In normal operation V RL = V and V RH = 5 V You must have V SS V RL < V RH V DD The accuracy of the A/D converter is guaranteed only for V RH V RL =5 V

2 When using the A/D converter, you can choose between performing single or continuous conversion on a single channel or multiple channels The AD conversion results are stored in the registers ATDDR through ATDDR7 You can choose whether to have the results left-justified or right justified To program the HCS2 A/D converter you need to set up the A/D control registers ATDCTL2, ATDCTL3, ATDCTL4 and ATDCTL5 The registers ATDCTL and ATDCTL are used for factory test, and not used in normal operation When the AD converter is not used, Port AD can be used for general purpose input Register ATDDIEN is used to set up Port AD pins for use as a general purpose inputs The values on the pins are read from PORTAD MULT= PAD PAD PAD PAD2 PAD7 PAD3 A/D ATDR ATDR ATDDRx ATDR2 ATDR3 CC CB CA Only one channel, determined by CC CB CA Single or continuous conversion to 8 conversions, number determined by SC, S2C, S4C, S8C MULT= PAD PAD7 PAD PAD PAD2 PAD3 A/D ATDR ATDR ATDDRx ATDR2 ATDR3 Several channels Starting channel determined by CC CB CA to 8 conversions, number determined by SC, S2C, S4C, S8C

3 ATDCTL2 ADPU AFFC ASWAI ETRIGLE ETRIGLP ASCIE ASCIF x82 ATDCTL3 S8C S4C S2C SC FIFO FRZ FRZ x83 ATDCTL4 SRES8 SMP SMP PRS4 PRS3 PRS2 PRS PRS x84 ATDCTL5 DJM DSGN SCAN MULT CC CB CA x85 To Use A/D Converter: ADPU = (Power up A/D) ETRIGLE ETRIGP External Trigger Falling edge Rising edge Low level High level ASCIE = => disables ATD interrupt ASCIE = => enables ATD interrupt on sequence complete (ASCIF = ) ASCIF = => no ATD interrupt occurred ASCIF = => ATD sequence complete S8C, S4C, S2C, SC: Number of conversions per sequence: ( to 7) SRES8 = = > Bit Mode SRES8 = => 8 Bit Mode SMP & SMP2: select sample time bits Always use = > 2 A/D conversion clock periods PRS4- PRS are prescaler bits to set the conversion clock frequency ATDclock=([bus clock]/(prs+))*5 PRS4 - PRS Total Divisor Value Max Bus Clock Min Bus Clock by 2 by 4 by 6 by 8 by by 2 by 4 by 6 4 MHz 8 MHz 2 MHz 6 MHz 2 MHz 24 MHz 28 MHz 32 MHz MHz 2 MHz 3 MHz 4 MHz 5 MHz 6 MHz 7 MHz 8 MHz

4 The ATD conversion frequency must be between 5 khz and 2 MHz DJM = => Left justified data in the result registers DJM = => Right justified data in the result registers DSGN = => Unsigned data in the result registers DSGN = => Signed data representation in the result registers (only for left justified) SCAN = => Single conversion sequence SCAN = => Convert continuously MULT = => Sample only one channel MULT = => Sample across several channels CC CB CA Analog Input Channel AN AN AN2 AN3 AN4 AN5 AN6 AN7 SCF Flag is set after a sequence of conversions is complete The SCF Flag is cleared when ATDCTL5 is written, or by writing a to the SCF bit After writing to ATDCTL5, SCF flag cleared and conversions start USING THE HCS2 A/D CONVERTER Power up A/D Converter (ADPU = in ATDCTL2) 2 Select number of conversions per sequence (S8C S4C S2C SC in ATDCTL3) S8C S4C S2C SC = to for to 7 conversions S8C S4C S2C SC = or xxx for 8 conversions 3 Set up ATDCTL4 For 8-bit mode write x85 to ATDCTL4 For -bit mode write x5 to ATDCTL4 Other values of ATDCTL4 either will not work or will result in slower A/D conversion rates

5 4 Select DJM in ATDCTL5 (a) DJM = => Left justified data in the result registers (b) DJM = => Right justified data in the result registers 5 Select DSGN in ATDCTL5 (a) DSGN = => Unsigned data representation in the result register (b) DSGN = => Signed data representation in the result register The Available Result Data Formats are shown in the following table: SRES8 DJM DSGN RESULT DATA FORMAT 8-bit/left justified/unsigned Bits bit/left justified/signed Bits 5-8 X 8-bit/right justified/unsigned Bits 7- -bit/left justified/unsigned Bits 5-6 -bit/left justified/signed Bits 5-6 X -bit/right justified/unsigned Bits 9-6 Select MULT in ATDCTL5: MULT = : Convert one channel the specified number of times Choose channel to convert with CC, CB, CA of ATDCTL5 MULT = : Convert across several channels CC, CB, CA of ATDCTL is the first channel to be converted 7 Select SCAN in ATDCTL5: SCAN = : Convert one sequence, then stop SCAN = : Convert continuously 8 After writing to ATDCTL5, the A/D converter starts, and the SCF bit is cleared After a sequence of conversions is completed, the SCF flag in ATDSTAT is set You can read the results in ATDDRx [-7] 9 If SCAN =, you need to write to ATDCTL5 to start a new sequence If SCAN =, the conversions continue automatically, and you can read new values in ADR[-7] To get an interrupt after the sequence of conversions are completed, set ASCIE bit of ATDCTL2 After the sequence of conversions, the ASCIF bit in ATDCTL2 will be set, and an interrupt will be generated On HCS2 EVBU, AD channels and are used to determine start-up program (D- Bug2, EEPROM or bootloader) Do not use AD channels or unless absolutely necessary (if you need more than 4 A/D channels) 2 ATDDRx =(V in V RL )/(V RH V RL ) 24 Normally, V RL = V, and V RH = 5 V, so ATDDRx =V in /5 V 24

6 Example: ATDDR = 448 => V in = 29 V 3 To use -bit result, set ATDCTL4 = x5 (Gives 2 MHz AD clock with 24 MHz bus clock, -bit mode) 4 You can get more accuracy by averaging multiple conversions If you need only one channel, set MULT =, set S8C, S4C, S2C, SC, bits for eight conversions, then average all eight result registers The following assumes the data was right justified: int avg; avg = (ATDDR + ATDDR ATDDR2 + ATDDR3 ATDDR4 + ATDDR5 ATDDR6 + ATDDR7) >> 3;

7 A sinusoidal signal with Gaussian noise embedded in it, and an averaged signal

8 /* Read temperature from PAD4 Turn on heater if temp too low, * turn off heater if temp too high Heater connected to Bit * of Port A */ #include "hcs2h" #define TRUE #define SET_POINT 72 /* Temp at which to turn heater on or off */ main() { ATDCTL2 = x8; /* Power up A/D, no interrupts */ ATDCTL3 = x; /* Do eight conversions */ ATDCTL4 = x85; /* 8-bit mode */ ATDCTL5 = xa4; /* \ / \ Bit 4 of Port AD \ MULT = => one channel only \ Scan = => continuous \ DSGN = => unsigned \ DJM = => right justified */ /*******************************************************************/ DDRA = xff; /* Make Port A output */ PORTA = x; /* Turn off heater */ /*******************************************************************/ } while (TRUE) { if (ATDDR > SET_POINT) PORTA &= ~x; else PORTA = x; }

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