The Successive Approximation Converter Concept - 8 Bit, 5 Volt Example

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Elmer Harvey
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1 Successive Approximation Converter A successive approximation converter provides a fast conversion of a momentary value of the input signal. It works by first comparing the input with a voltage which is half the input range. If the input is over this level it compares it with three-quarters of the range, and so on. Eight such steps gives 8 bit resolution. While these comparisons are taking place the signal is frozen in a sample and hold circuit. The Successive Approximation Converter Concept - 8 Bit, 5 Volt Example D/A Out = SAR Binary Value x Analog Voltage Range 2 n Where n is the number of bits for A/D - 1

2 Specifications of Analogue-to-Digital Converters Resolution The resolution of the A-D converter is the number of steps the input range is divided into. The resolution is usually expressed as bits (n) and the number of steps is 2 to the power n. A converter with 8-bit resolution, for in stance, divides the range into 2 8, or 256 steps ( 0 to 255). In this case a 0-5 V range will be resolved to 5/256 or mv. Linearity Ideally an A-D converter with n-bit resolution will convert the input range into (2 to the power n)-1 equal steps (255 steps in the case of a 8-bit converter). In practice the steps are not exactly equal, which leads to non-linearity in a plot of A/D output against input voltage. Sample and Hold Acquisition Time A sample and hold circuit freezes the analogue input voltage at the moment the sample is required. This voltage is held constant while the A-D converter digitizes it. The acquisition time is the time between releasing the hold state and the output of the sample circuit settling to the new input voltage value. - 2

3 Throughput The throughput is the maximum rate at which the A-D converter can output data values. In general it will be the inverse of the (conversion time + the acquisition time) of the A-D converter. Thus a converter that takes 10 microseconds to acquire and convert will be able to generate about samples per second. Quantization Error Quantization error is related to resolution and is the error due to the fact that the data from the A/D cannot represent every single analog value. Quantization Error = 2 n above Quantization Error = V R where n is number of data lines and V R is range of A/D. In example 1 x 5 = volts. 256 Transfer Function The transfer equation can be determined from the ratios between the analog input Va to voltage reference V R and digital output to full scale digital. For a linear system the two ratios must be equal. Ratio = Va = code rounded to nearest. V R 2 n or code = Va x 256 rounded to nearest for an 8 bit ADC. V R This equation works for designs in which the minimum voltage is at ground. If the input is bipolar and is level shifted, the general equation is Vin - Vmin = code where Vmin is the minmum input voltage and Vmax Vmin 2 n Vmax is the maximum input voltage. - 3

4 HCS12 A/D Converter The HCS12's A/D is an 8-channel, 10-bit, multiplexed input successive approximation analog-todigital converter. Features 8/10 Bit Resolution. 7msec, 10-Bit Single Conversion Time. Sample Buffer Amplifier. Programmable Sample Time. Left/Right Justified, Signed/Unsigned Result Data. External Trigger Control. Conversion Completion Interrupt Generation. Analog Input Multiplexer for 8 Analog Input Channels. Analog/Digital Input Pin Multiplexing. 1 to 8 Conversion Sequence Lengths. Continuous Conversion Mode. Multiple Channel Scans. - 4

5 Registers to Configure/Read From ATD0CTL5 ATD0STAT0 ATD0DR0H ATD0DR1H ATD0DR2H ATD0DR3H ATD0CTL2 ATD0CTL3 ATD0CTL4 ATD Control Register 2 (ATDCTL2) This register controls power down, interrupt and external trigger. Writes to this register will abort current conversion sequence but will not start a new sequence. For Laboratory 10, set bits as follows: ATD Control Register 2 (ATDCTL2) ADPU Power Down - '1' Normal Functionality AFFC Flag clear - '0' Normal AWAI Power down during wait - '0' ETRIGE Disable external trigger - '0' ASCIE Sequence complete interrupt requests disabled - '0' ATD Control Register 3 (ATDCTL3) This register controls the conversion sequence length, FIFO for results registers and behavior in Freeze Mode. Writes to this register will abort current conversion sequence but will not start a new sequence. ATD Control Register 3 (ATDCTL3) - 5

6 For Laboratory 10, set bits as follows: at reset S4C set to 1 which results in 4 conversions per sequence FIFO conversion result placed in corresponding result register - '0' FRZ1 FRZ2 breakpoint response - continue converting - '0' '0' ATD Control Register 4 (ATDCTL4) This register selects the conversion clock frequency, the length of the second phase of the sample time and the resolution of the A/D conversion (i.e.: 8-bits or 10-bits). Writes to this register will abort current conversion sequence but will not start a new sequence. For Laboratory 10, set bits as follows: ATD Control Register 4 (ATDCTL4) SRES8 10 bit resolution '0' SMP1 SMP0 Sample time select, minimum sample time '0', '0' least accurate PRS0 through PRS4 clock prescaler, max clock freq, '0','0','0','0','0' ATD Control Register 5 (ATDCTL5) This register selects the type of conversion sequence and the analog input channels sampled. Writes to this register will abort current conversion sequence and start a new conversion sequence. For Laboratory 10, set bits as follows: ATD Control Register 5 (ATDCTL5) DJM left justified in result register '0' DSGN Unsigned data representation in result register '0' SCAN Single conversion '0' MULT Sample 1 channel '0' CC, CB, CA Chanel select '0','0','0' - 6

7 ATD Status Register 0 (ATDSTAT0) This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and the conversion counter. ATD Status Register 0 (ATDSTAT0) In Laboratory 10, Examine the SCF bit. That is, wait for SCF (sequence complete flag), do 4 conversions on 1 channel - will be stored in high byte result registers -, then take average of 4 conversions ATD Conversion Result Registers (ATDDRx) The A/D conversion results are stored in 8 read-only result registers. The result data is formatted in the result registers bases on two criteria. First there is left and right justification; this selection is made using the DJM control bit in ATDCTL2. Second there is signed and unsigned data; this selection is made using the DSGN control bit in ATDCTL2. Signed data is stored in 2 s complement format and only exists in left justified format. Signed data selected for right justified format is ignored. - 7

8 // converts 8 bit A/D on pin 67 (PAD00/AN00) #include <hidef.h> /* common defines and macros */ #include <6812dp256b.h> /* derivative information */ // driver for bit ADC //******** ADCgetSample *************** // perform 4 ADC samples on Chan // return average 4 results // analog input return value // // // // unsigned char ADCgetSample(unsigned char chan) { ATD0CTL5 = chan; // start sequence //DJM left justified in result register '0' //DSGN Unsigned data representation in result register '0' //SCAN Single conversion '0' //MULT Sample 1 channel '0' // CC, CB, CA Chanel select '0','0','0' while((atd0stat0&0x80)==0){; // wait for SCF (sequence complete) //do 4 conversions on 1 channel - will be stored in high byte result registers // then take average of 4 conversions return (ATD0DR0H+ATD0DR1H+ATD0DR2H+ATD0DR3H)/4; //******** ADCopen *************** // Initialize ADC void ADCopen(void) { ATD0CTL2 = 0x80; // enable ADC //ADPU Power Down - '1' Normal Functionality //AFFC Flag clear - '0' Normal //AWAI Power down during wait - '0' //ETRIGE Disable external trigger - '0' //ASCIE Sequence complete interrupt requests disabled - '0' /* Register ATD0CTL3 set to defaults 0x */ // at reset S4C set to 1 which results in 4 conversions per sequence */ // FIFO conversion result placed in corresponding result register - '0' // FRZ1 FRZ2 breakpoint response - continue converting - '0' '0' /* Register ATD0CTL4 set to defaults 0x */ // SRES8 10 bit resolution '0' //SMP1 SMP0 Sample time select, minimum sample time '0', '0' least accurate //PRS0 through PRS4 clock prescaler, max clock freq, '0','0','0','0','0' #pragma CODE_SEG NEAR_SEG NON_BANKED /* Interrupt section for this module. Placement will be in NON_BANKED area. */ interrupt void RTIisr(void) { /* simple RTI interrupt service routine */ CRGFLG = 0x80; // clear RTIF bit PORTB=~(ADCgetSample(0)); // convert A/D channel 0 and display #pragma CODE_SEG DEFAULT - 8

9 static void RTIopen(void) { /* setup of the RTI interrupt frequency */ /* adjusted to get 1 millisecond (1.024 ms) with 16 MHz oscillator */ RTICTL = 0x1F; /* set RTI prescaler */ CRGINT = 0x80; /* enable RTI interrupts */ void main(void) { DDRB=0xFF; RTIopen(); ADCopen(); EnableInterrupts; // PORTB outputs for LEDs for(;;) ; /* wait forever */ - 9

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