CMOS DESIGN OF FLIP-FLOP ON 120nm

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1 CMOS DESIGN OF FLIP-FLOP ON 120nm *Neelam Kumar, **Anjali Sharma *4 th Year Student, Department of EEE, AP Goyal Shimla University Shimla, India. ** Assistant Professor, Department of ECE AP Goyal Shimla University Shimla, India. ABSTRACT In this paper we present the CMOS designs of SR latch, SR flip-flop, JK flip-flop, T-flip-flop and D-flip-flop of 120nm technology. Today the low power consumption and less area have become the basic demand of the digital circuits used in the various portable devices. So there is need of VLSI designing methods to control and limit power and area consumed by digital circuits. The introduced CMOS flip-flops have been designed and simulated using DSCH 3.1 and Microwind 3.1 on 120nm. Power variation with respect to the supply voltage has been performed on BISM model. The simulated results show that area consumed by the proposed CMOS circuits in μm 2 on and the power consumed in μw. The power consumed by SR latch, SR flip-flop, JK flip-flop, T-flip flop and D-flip flop at 1.2V input supply voltage is 2.391μW, 6.965μW, 4.743μW, 0.381μW, 8.809μW respectively. The introduced designs possess both low power dissipation and low area consumption and give high performance. Keywords: CMOS technology, Flip-Flops, Latch, Low power dissipation, VLSI design INTRODUCTION Flip-Flops are one of the basic digital devices used for variety of purpose in the digital field. The output of Flip-flops at any instant of time depends on the past output and present input that is why these are also called memory element [7]. These memory elements are made up of an assembly of logic gates NOT, OR, AND, NOR, NAND, and CMOS latches [1]. They may have inputs up to five depending on the type but the outputs are always two normally labelled as Q and Q and should be complimentary [6]. Here we introduce the power efficient CMOS designs of flip-flops. In CMOS designing the minimisation of power has become one of the primary concerns. Power dissipation is Increases due to increasing the rate of transistors on a single chip [4]. Power dissipation in any digital circuit depends on two components one is static dissipation which occurs due to the leakage current or other current drawn continuously from the power supply. The leakage current is described by the equation [12] qv / kt i i ( e 1) (1) o s Where is is reverse saturation current, V is diode voltage, q is electronic charge, k is Boltzmann s constant and T is temperature [12]. The static power dissipation is the product of the leakage current and supply voltage. The total static power dissipation P s is given by 46

2 P s n 1 Leakage current voltage (2) Where n= no of devices Second is dynamic dissipation which occurs due to switching of transient current, and charging and discharging of load capacitances which is given by the equation P d CLV t 2 DD p (3) Another type of power dissipation is short circuit dissipation which is the part of dynamic power dissipation. Short circuit power occurs due to signal rise and fall time. During these periods PMOS and NMOS are ON for short period, so there will be a path from V dd to V ss and is given by the equation Where I pr P SC V dd I prt 2 is pick current during the rise-time, I pf r I pf 2 t f f t f is Fall-time period and f is Circuit switching frequency. (4) is Pick current during the fall-time t r is Rise-time period, Total power dissipation is given by the sum of these three power dissipation i.e. static power dissipation, dynamic power dissipation and short circuit dissipation. P total PS Pd Psc (5) The software used to draw and simulate the architecture of circuit is DSCH 3.1. It is used as a logic editor. The circuit is simulated to analyse and verify the architecture. MICROWIND3.1 is used to work on the layout of the circuit which shows the parameters like power consumption, area, number of N-MOS and P- MOS used etc. A. S.R Latch A latch refers to a non-clocked flip-flop because they latch on to 1 or 0 on receiving the inputs called SET and RESET. In case of gated latches they latch on to 1 or 0 only when the ENABLE signal is high. Here an SR latch is shown which is made by using NAND gates shown in fig. 1. In SR latch there are two inputs S (SET) and (RESET) and two complimentary outputs that are Q and Q. When both the inputs SR are resting in LOW and one of them is pulsed high to change the output, this is called an active-high input latch. When the same process is reversed the latch is called active-low latch [6]. 47

3 SR Latch using CMOS Figure 1: Symbolic diagram of SR latch using NAND gates. This CMOS circuit is made by using two 2 input NAND gates. As in CMOS technology two types of transistors N-MOS and P-MOS are used. Here the N-MOS and P-MOS used are equal in number. This SR Latch circuit has been designed by using 8 transistors. Figure 2: CMOS diagram of SR Latch. The layout of the proposed CMOS circuit of the SR Latch has been shown in Fig. 3. This layout consist 6 metal layers, via, contacts and insulation layer. 48

Figure 3: Layout of SR latch. The name of SR latch driven from its outputs SET (S) and RESET (R) [7]. When S and R are LOW (0) N2 and N3 are OFF and the P-transistors P2 and P3 are ON.

4 Figure 3: Layout of SR latch. The name of SR latch driven from its outputs SET (S) and RESET (R) [7]. When S and R are LOW (0) N2 and N3 are OFF and the P-transistors P2 and P3 are ON. This condition cannot determine the output logic. If we assume Q= 0 then P4 is turned ON and N4 is OFF i.e Q is connected to V DD then Q =1. When Q is HIGH the N-MOS N1 remains ON whereas P1 is OFF that means Q is connected to ground and remains OFF (0). Let us assume Q=1, then the N-MOS N4 is ON and P-MOS P4 is OFF then Q is connected to ground i.e Q =0. As Q =0 N-MOS N1 is OFF and P-MOS P1 is ON that means Q is connected to V DD and remains at logic 1. It proves the first condition of truth table [7]. When S=1 and R=0, then N2 is ON and P2 is OFF that s the Q is connected to ground and is at 0 logic state. This makes the P3 and P4 ON and Q will get connected with the V DD. Table 1: Truth table of SR latch S R Q Q Operation 0 0 Q 0 Q 0 Hold Reset Set Not allowed Figure 4: Timing simulation waveforms of SR Latch. 49

5 Power (micro watt) AGU International Journal of Engineering & Technology Timing simulation of SR Latch has been shown in Fig. 4 by using DSCH simulation tool. When S=0 and R=1 N-MOS is ON and P3 is OFF i.e the Q is connected to ground and will remain 0. Whereas P1 and are turned ON and Q is connected to V DD which rem1ains logic 1 state [7]. Simulation Results Table 2: Area and power consumption of CMOS SR Latch on 1.2 supply voltage Logic Family voltage (V) Power (μw) Area (μm 2 ) Transistor Count CMOS The power and area consumed by CMOS circuit of the SR latch is (μw) and 56.7 (μm 2 ) respectively. Table 3: Variation of power consumed by SR Latch with supply voltage Voltage(V) Power(μW) The power variation of power proposed circuit with respect to supply voltage is shown in fig. 5. At voltage 1.2v the power consumed by circuit is (μw). 3 Power variation of SR latch w.r.t voltage Power variation of SR latch w.r.t voltage voltage (Volt) Figure 5: Variation of power consumed with increased voltage. 50

6 B. SR FLIP-FLOP SR flip-flop is also called SET-RESET flip-flop. Its inputs S and R are synchronous in nature that is the outputs are changed only on triggering the CLOCK pulse [5],[6]. Fig. 6 shows the circuit diagram of SR flip-flop which is made by an assembly of NAND gates. SR Flip-Flop using CMOS Figure 6: Circuit diagram of SR Flip-Flop. This circuit is designed by using P -MOS and N -MOS transistors also called strong 1 (pull up) and strong 0 (pull down) transistors. Fig. 7 shows the Schematic SR flip flop in DSCH3.1 which consists four 2 input NAND gates. Figure 7: CMOS diagram of SR Flip-Flop. The working of the transistors is similar to as discussed in the CMOS circuit of SR latch. A CLOCK pulse generator is used here and this circuit gives the output only in presence of the CLOCK pulse i.e clock pulse is high at every operation [7]. 51

Figure 8: Layout of SR Flip-Flop in Microwind 3.1. The layout of SR flip-flop is shown in figure 8 in which has been designed by using different metal layers.

Table 4: Truth table SR Flip-Flop Inputs Clock Outputs Operation S R Q Q 0 0 HIGH Q Q No Change 1 0 HIGH 1 0 SET 0 1 HIGH 0 1 REEST 1 1 HIGH?

7 Figure 8: Layout of SR Flip-Flop in Microwind 3.1. The layout of SR flip-flop is shown in figure 8 in which has been designed by using different metal layers. Metal layers have been shown by blue colour and contacts have been shown by using red colour. Table 4: Truth table SR Flip-Flop Inputs Clock Outputs Operation S R Q Q 0 0 HIGH Q Q No Change 1 0 HIGH 1 0 SET 0 1 HIGH 0 1 REEST 1 1 HIGH?? Invalid As we know the CLOCK pulse acts as an enable signal for the inputs of the gates. The output Q and Q will remain HIGH until the clock pulse is at logic 0 [5].This is nothing but the quiescent condition of the flip-flop [5]. According to truth table at initial condition let us assume both inputs S and R at 0 and clock pulse at 1 (HIGH) there will be no change at the output. Let s assume S=1, R=0 and CP (CLOCK pulse) = 1. At this condition set state is reached i.e Q will be at logic 1[9]. That is because of both the inputs of the S gate are HIGH. We know the NAND gate gives 0 output only when both the inputs are HIGH. So when S=1, R=0 &CP=1. Both the inputs to the S gate are 1or high and hence its output is 0. This Output (0) is passed to gate which is having the output Q. Since one of the inputs of gate Q is 0, we can say that the output Q=1 and Q =0[7]. Figure 9: Timing simulation waveform of CMOS SR flip-flop. 52

8 Power(microwatt) AGU International Journal of Engineering & Technology Similarly when the condition S=0, R=1 & CP=1 is applied the Q will be at logic 1 whereas the output Q is at logic 0. This state is called RESET state. When both the inputs are HIGH the outputs Q and Q also remain at HIGH (1). This is not possible because both the outputs are complementary to each other. So it is better to avoid this condition during practice [7]. Simulation Results Table 5: Study of area and power consumption of CMOS SR flip flop Logic Family voltage (V) Power (μw) Area (μm 2 ) Transistor Count CMOS The power and area consumed by CMOS circuit of the SR flip flop is (μw) and (μm 2 ) respectively. Table 6: Variation of power w.r.t Supplied voltage Voltage(V) Power (μw) The power variation of power proposed circuit with respect to supply voltage is shown in figure 10. At voltage 1.2v the power consumed by circuit is (μw) Power variation of SR flip-flop w.r.t voltage Power variation of SR flip-flop w.r.t voltage Voltage(volt) Figure 10 : Variation of Power w.r.t voltage. 53

9 C. JK Flip-Flop JK flip flop was invented by a scientist Jack Kilby that is why it is called JK flip flop [1]. This flip flop avoid the invalid output of SR flip flop when both the inputs are HIGH. So it has possible operation at every condition [5]. Figure 11: Circuit diagram of JK Flip-Flop. When both the inputs J and K are at logic 1 in the presence of clock pulse there is no change at the output i.e called HOLD state [6]. Similarly the condition J=1 and K=0 gives the command to SET the flip flop that is the output Q is at logic 1 whereas the output Q is at logic 0 as illustrated in Table 7 [1]. Table 7: Truth table of JK flips flop Inputs Clock Outputs Operation J K Q Q 0 0 HIGH Q 0 Q 0 HOLD (no change) 0 1 HIGH 0 1 RESET 1 0 HIGH 1 0 SET 1 1 HIGH Q Q TOGGLE When J=0 and K=1 it gives the command to RESET the flip flop.when J and K both the input it are HIGH the flip flop will toggle on the next positive clock pulse i.e will change to its compliment [6]. This state is called Toggle operation [7]. JK Flip-Flop using CMOS This circuit is made by using two 3 input NAND gates and two 2 input NAND gates. This propounded circuit is designed by using strong 1(pull up) and strong 0 (pull down) transistors namely P -MOS and N - MOS transistors [1]. 54

10 Layout design Figure 12: CMOS design of JK flip-flop. This layout design shows the count of transistors used. The total transistors used here are 20 whereas out of them 10 are n-mos transistors and 10 p-mos transistors. The efforts are done to give the common V dd supply to reduce the power consumption. Simulation Results Figure 13: CMOS design of JK flip-flop. Table 8 : Study of area and power consumption of CMOS JK flip flop Logic family voltage (V) Power (μw) Area (μm 2 ) Transistor Count CMOS

11 Power(µ) AGU International Journal of Engineering & Technology The power and area consumed by CMOS circuit of the JK flip flop is (μw) and (μm 2 ) respectively. Table 9: Variation of power w.r.t Supplied voltage Voltage(V) Power (μw) The power variation of power proposed circuit with respect to supply voltage is shown in fig. below. At voltage 1.2v the power consumed by circuit is (μw). Variation of power of JK flip flop w.r.t voltage Variation of power w.r.t voltage Voltage(volt) D. T Flip-Flop Figure 14: power and voltage variation of JK flip flop w.r.t supplied voltage. In JK flip flop if the terminal J and K are fed from the same input (T) the resulting circuit is referred to as T flip flop or Toggle flip flop It has only one input i.e T input as shown in figure 15 [7]. When T=1 on applying the clock pulse the output is changed to its compliment i.e is called toggle. [7], [9]. 56

12 Figure 15: Symbolic diagram of T- flip flop. When the T=0 in the presence of clock pulse the output remains at the previous state (HOLD) as shown in the table 10. Table 10: Truth table of T flips flop Input Clock Output Comments T Q Q 0 HIGH 1 0 Previous state 1 HIGH 0 1 Toggle (Compliment of previous state ) T Flip-Flop using CMOS The construction of T Flip Flop is similar to JK flip flop. It is designed by using two 3 input NAND gates and Two 2 input NAND gates as shown in figure below. Figure 16: CMOS design of T-flip flop 57

Layout Design The layout of figure 5.2 in Microwind3.1 is shown in fig. below. This design is checked for DRC if there will be no error the layout can be simulated [9].

13 Layout Design The layout of figure 5.2 in Microwind3.1 is shown in fig. below. This design is checked for DRC if there will be no error the layout can be simulated [9]. In this circuit 20 transistors are used, whereas out of them 10 are NMOS and 10 are PMOS transistors. Simulation results Figure 17: Layout of T-flip flop Table 11: Area and power consumption of CMOS T flip flop Logic family voltage (V) Power (μw) Area (μm 2 ) Transistor Count CMOS The power and area consumed by CMOS circuit of the T flip flop is (μw) and (μm 2 ) respectively. Table 12: Variation of power w.r.t Supplied voltage Voltage(V) Power (μw) The power variation of power proposed circuit with respect to supply voltage is shown in fig. 18. At voltage 1.2v the power consumed by circuit is (μw). 58

14 Power (microwatt) AGU International Journal of Engineering & Technology 1.2 Power variation of T flip flop w.r.t voltage Power variation of T flip flop w.r.t voltage Voltage (volt) E. D flip flop Figure 18: power and voltage variation of T flip flop w.r.t supplied voltage D flip-flop stands for delay flip flop, it has only one input (D). It can be made by adding the inverter to an SR flip flop [7]. The block diagram of D flip flop is shown in figure 19. Figure 19: Block diagram of D-flip flop. When Clock pulse and input D are at HIGH or logic 1 the D input propagates the output Q. This condition is called SET state. If clock pulse is at logic 0 the output remains same. When the input D is low in the presence of clock pulse the output Q =1. This state is called RESET state as illustrated in Table 13. Table 13: Truth Table of D flip-flop D CLOCK Q Q OPERATION 0 HIGH 0 1 RESET 0 LOW 0 1 HOLD 1 HIGH 1 0 SET 1 LOW 1 0 HOLD 59

15 D flip flop using CMOS As shown in block diagram the D flip flop is constructed by adding the inverter in between the SR flip flop. This CMOS circuit of D flip flop is also made by connecting the inverter in between the SR input of the SR Flip flop as shown in fig. 21. Figure 21: D-flip flop using CMOS in DSCH3.1 The working waveforms of the D flip flop on simulating the architecture drawn in DSCH 3.1 according to the conditions illustrated in truth table of D-flip flop is shown in fig. 22. Figure 22: Timing simulation of CMOS D-flip flop in DSCH3.1. Fig. 23 shows the layout of D-flip flop using CMOS which shows the number of transistors used in circuit. In this layout 20 transistors are used. Whereas out of them 10 are NMOS and 10 are PMOS transistors. 60

16 Simulation Results Figure 23: Layout out of D-flip flop in Microwind 3.1. Table 14: Study of area and power consumption of CMOS D flip flop Logic family voltage (V) Power (μw) Area (μm 2 ) Transistor Count CMOS The power and area consumed by CMOS circuit of the D flip flop is (μw) and (μm 2 ) respectively. Table 15: Variation of power w.r.t Supplied voltage Voltage(V) Power (μw) The power variation of power proposed circuit with respect to supply voltage is shown in figure 24. At voltage 1.2v the power consumed by circuit is (μw) 61

17 Power(microwatt) AGU International Journal of Engineering & Technology power variation Of D flip flop w.r.t voltage voltage power variation Of D flip flop w.r.t voltage Figure 24: power and voltage variation of D flip flop w.r.t supplied voltage. RESULT Table 16: Observation of parameters of various flip flops and latches Logic Family Latch and Flip-flop Paramet SR SR Flip JK Flip D Flip T Flip ers Latch flop flop flop flop N-MOS P-MOS CMOS Width (μm) Height (μm) Area (μm 2 ) Power (μw) Max Current (ma) Avr Current (ma)

18 The observation of various parameters of the different CMOS circuits of flip flops and latch is shown in table 16. These observations are taken from layout design simulation of the various circuits. The supply voltage is 1.2 Volt at which the circuits are simulated. CONCLUSION In this paper the proposed circuits SR latch, SR, JK, D and T flip flops are designed by using the CMOS technique which provides track of low power consumption by self designing the layout of the circuit. The foundry used to design the circuit is 120nm. All results are also verified at different supply voltage. From the table 16 we can compare the efficiency of the various flip flops at the same voltage of 1.2 volt. JK flip flop using 20 transistors consumes power and area μw and μm 2 respectively which is the average power consumption of the flip flop circuits illustrated in table 16. All the results are simulated using MICROWIND3.1. REFERENCES [1] Pinki, Rajesh Mehra, Design of Low Power High Performance JK Flip Flop International Journal of Scientific Research Engineering & Technology (IJSRET), pp 1-4, year 2015 [2] Ahmed Sayed and Hussain Al-Asaad Low-Power Flip-Flops Survey, Comparative Evaluation and a New Design, IACSIT International Journal of Engineering and Technology, Vol.3, pp , Year [3] Ahmed Sayed and Hussain Al-Asaad, A New Low Power High Performance Flip-Flop. [4] Anjali Sharma, Richa Singh, Rajesh Mehra, Low Power TG Full Adder Design Using CMOS Nano Technology, IEEE International Conference on Parallel, Distributed and Grid Computing, pp [5] [6] VLSI DESIGN by Debprasad DAS. [7] Introduction to Digital Electronics by Vipin Arora. [8] [9] Pushap Rajand, Rajesh Mehra Performance and Analysis of T Flip flop Using CMOS Technology IJEEE, Volume 07, pp , year [10] Microwind and DSCH version 3.1, User s Manual, Copyright , Microwind INSA France, pp , [11] Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective Reading, Pearson Education, Addison Wesley pp , [12] Sung-Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits: Analysis and Design, pp ,

ANALYSIS OF POWER REDUCTION IN 2 TO 4 LINE DECODER DESIGN USING GATE DIFFUSION INPUT TECHNIQUE

ANALYSIS OF POWER REDUCTION IN 2 TO 4 LINE DECODER DESIGN USING GATE DIFFUSION INPUT TECHNIQUE *Pranshu Sharma, **Anjali Sharma * Assistant Professor, Department of ECE AP Goyal Shimla University, Shimla,