Case3:08-cv JW Document279-2 Filed07/02/12 Page1 of 10. Exhibit B

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1 Case:0-cv-0-JW Document- Filed0/0/ Page of 0 Exhibit B

2 Case:0-cv-0-JW Case:0-cv-00-JW Document- Document0 Filed0// Filed0/0/ Page Page of 0 0 John L. Cooper (State Bar No. 00) jcooper@fbm.com Nan Joesten (State Bar No. ) njoesten@fbm.com Eugene Y. Mar (State Bar No. 0) emar@fbm.com Farella Braun & Martel LLP Telephone: Facsimile: () -0 Attorneys for Defendants TECHNOLOGY PROPERTIES LIMITED and ALLIACENSE LIMITED Charles T. Hoge, Esq. (State Bar No. 0) choge@knlh.com Kirby Noonan Lance & Hoge Tenth Avenue San Diego, CA 0 Telephone: () - Facsimile: () - Attorneys for Defendant PATRIOT SCIENTIFIC CORPORATION UNITED STATES DISTRICT COURT NORTHERN DISTRICT OF CALIFORNIA SAN JOSE DIVISION HTC CORPORATION and HTC AMERICA, INC., v. Plaintiffs, TECHNOLOGY PROPERTIES LIMITED, PATRIOT SCIENTIFIC CORPORATION and ALLIACENSE LIMITED, Defendants. I/S/O DEFS. OPP. TO HTC S MTN. FOR SUMMARY JUDGMENT/ No. :0-cv-0 Case No. :0-cv-0 JF DECLARATION OF DR. VOJIN OKLOBDZIJA IN SUPPORT OF DEFENDANTS TECHNOLOGY PROPERTIES LTD., PATRIOT SCIENTIFIC CORP. AND ALLIACENSE LIMITED S OPPOSITION TO HTC S MOTION FOR SUMMARY JUDGMENT OF NON-INFRINGEMENT Dept.: Courtroom, th Floor Judge: The Honorable Jeremy Fogel Hearing: To Be Determined [REDACTED] \.

3 Case:0-cv-0-JW Case:0-cv-00-JW Document- Document0 Filed0// Filed0/0/ Page Page of 0 0 I, Vojin Oklobdzija, hereby declare:. I have been asked by, counsel for Defendants Technology Properties Limited and Alliacense Limited to evaluate Plaintiffs HTC Corp. and HTC America, Inc. s ( HTC s ) Motion for Summary Judgment of Non-Infringement of U.S. Patent Nos.,0,;,0,; and,, ( Motion ), and provide some of my expert opinions in response to the arguments raised in HTC s Motion. I expect to supplement or amend my opinions based on additional discovery and in rebuttal to any expert opinions provided by technical experts representing HTC or co-plaintiffs Acer or Barco in related case nos. 0-cv-0 and 0-cv-0, respectively.. I received a Dipl. Ing. (equivalent to a Master s in Electrical Engineering in the U.S.) degree in Telecommunications and Electronics in, followed by a Master s in Computer Science from the University of California, Los Angeles in. I received a PhD in Computer Science with a minor in Electronics from the University of California, Los Angeles in. Following my PhD graduation, I spent years at IBM s T.J. Watson Research Center working on microprocessor architecture, development and design. Since then, I have held faculty (Full Professor) positions at the University of California - Davis, Sydney University in Australia, and University of Texas at Dallas. I have over years of teaching experience, teaching courses in: Computer Architecture, Computer Design, Digital Design, VLSI Circuits as well as advanced post-graduate courses in Computer Architecture and Design. I have served as a consultant with members of the microprocessor industry extensively and was a principal architect in the Siemens/Infineon TriCore processor and media-processor for SONY. Currently, I continue to serve as a consultant and am a Distinguished P.W. Klipsch Professor and Department Head of the Klipsch School of Electrical and Computer Engineering at New Mexico State University. I also remain an Emeritus Professor with the University of California - Davis. I am a named inventor on issued U.S. Patents and a similar number of international patents. I have also authored several books on microprocessor design, including a book on clocking titled Digital System Clocking, published by John Wiley & Sons, Inc. in 0, and a book titled Computer Engineering Handbook, published by CRC Press in 0, which won the CHOICE Outstanding I/S/O DEFS. OPP. TO HTC S MTN. FOR SUMMARY JUDGMENT/ No. :0-cv-0 \.

4 Case:0-cv-0-JW Case:0-cv-00-JW Document- Document0 Filed0// Filed0/0/ Page Page of 0 0 Academic Title Award for 0. I have attached a true and correct copy of my curriculum vitae as Exhibit to this declaration, which further sets forth my qualifications.. I understand that my opinions expressed in this report are described from the perspective of one having ordinary skill in the art at the time of the inventions described in the,, and Patents. I understand that the inventions occurred in. In the context of these three patents, a person having ordinary skill in the art would at least have a bachelor s degree in electrical engineering or computer science and have approximately - years of experience in the field of microprocessor design and programming. This person would have access to a library of technical publications, periodicals, and textbooks. I. HOW MULTIPLE THUMB STATE INSTRUCTIONS ARE FETCHED AND SUPPLIED TO THE CPU. This section contains my opinions on how one of ordinary skill in the art would understand how the accused HTC products infringe the Patent based on the claim charts attached to Defendants Preliminary Infringement Contentions and the reference materials incorporated into those claim charts. My review of these claim charts included Exhibit to the Declaration of Kyle Chen [Dkt. ], which illustrates how the HTC Mobile Phone Star Trek infringes the Patent.. Exhibit illustrates how the accused HTC phone infringed the originally issued claims of the patent. In original claim of the Patent, the claim includes a limitation to fetch multiple sequential instructions from said memory in parallel and supply the multiple sequential instructions to said central processing unit integrated circuit during a single memory cycle. Patent] at :-; Declaration Eugene Y. Mar in Support of Defendants Oppostion ot Motion for Summary Judgment ( Mar Decl. ), Ex. G.. During reexamination of the Patent, Claim was amended to include the following clarification: wherein the microprocessor system comprises an instruction register configured to store the multiple sequential instructions and from which instructions are accessed and decoded; and wherein SUMMARY JUDG. / No. :0-cv-0 \.

5 Case:0-cv-0-JW Case:0-cv-00-JW Document- Document0 Filed0// Filed0/0/ Page Page of 0 0 the means for fetching instructions being configured and connected to fetch multiple sequential instructions from said memory in parallel and supply the multiple sequential instructions to the central processing unit integrated circuit during a single memory cycle comprises supplying the multiple sequential instructions in parallel to said instruction register during the same memory cycle in which the multiple sequential instructions are fetched. Mar Decl., Ex. B [January, Amendments in Reexam No. 0/00,0]. I understand that the Patent Office has indicated that it will confirm the patentability of claim with this amended language when it issued the Notice of Intent to Issue a Reexamination Certificate on February, ( NIRC ), Mar Decl., Ex. A. The amendments to claim clarified that (i) the multiple sequential instructions are fetched and supplied to the instruction register in the CPU, and (ii) that the multiple sequential instructions are supplied in parallel to the instruction register in the CPU.. All of the HTC products accused of infringing the patent contain an embedded ARM microprocessor core. For example, in Exhibit to the Chen Declaration, the accused HTC phone contains a Texas Instrument OMAP (Open Multimedia Application Platform) 0 system-on-chip, which contains an embedded ARM microprocessor core. An ARM microprocessor core executes ARM instruction set, which includes Thumb instructions. Thumb instructions expanded the ARM instruction set to include a mixture of both -bit and - bit instructions. Thumb is an extension to the ARM architecture. It contains instruction formats drawn from the standard -bit ARM instruction set that have been re-coded into -bit wide op-codes. This brings very high code density, since Thumb instructions are half the width of ARM instructions. Mar Decl. Ex. D [Introduction to Thumb], at.. As illustrated by Exhibit to the Chen Declaration, the Defendants infringement claim charts for the patent use multiple excerpts from different ARM documents to highlight how microprocessors operating in a Thumb state fetch multiple sequential instructions from external memory and supply those multiple sequential instructions in parallel to the instruction register within the central processing unit (CPU). The embedded ARM microprocessors found in the HTC products accused of infringing the Patent are all capable of supporting a mixture of both -bit ARM instructions and -bit Thumb instructions. For example, in Exhibit, the accused HTC Mobile Phone Star Trek contains an ARM core, SUMMARY JUDG. / No. :0-cv-0 \.

6 Case:0-cv-0-JW Case:0-cv-00-JW Document- Document0 Filed0// Filed0/0/ Page Page of 0 0 which according to the cited ARMEJ-S Technical Reference Manual, supports a mixture of both -bit ARM instructions and -bit Thumb instructions. Mar Decl., Ex. H [ARM-EJ-S Technical Reference Manual], at -.. The mixture of -bit and -bit instructions improves code density and instruction bandwidth by allowing two -bit instructions to be fetched from memory and supplied in parallel to the instruction register within the CPU. In particular, the highlighted passage from page of the Introduction to Thumb states Each external fetch draws either one -bit ARM instruction or two -bit Thumb instructions. Mar Decl., Ex. D [Introduction to Thumb]. at. A person having ordinary skill in the art understands from the highlighted passage how multiple sequential instructions are fetched from memory in parallel and supplied in parallel to the instruction register within the CPU, as further explained below. 0. ARM describes that its instructions are stored in instruction memory as -bit words. Mar Decl. Ex. D [Introduction to Thumb], at. Each word either contains one -bit ARM instruction or two -bit Thumb instructions. Id. Since instructions are fetched one word at a time, fetching one -bit instruction word that contains two -bit instructions from instruction memory and storing that word in the instruction register within the CPU constitutes supplying two instructions to the CPU in parallel as required by claim of the patent. When a -bit word is fetched and supplied to the instruction register within the CPU without additional fetches, then the fetch and supply occur during a single memory cycle.. Since each word is -bits wide, the instruction register that stores the instruction word is -bits wide. In Thumb state, the instruction register contains two Thumb instructions. During the decode cycle, instructions stored in an instruction register are decoded. The decode stage receives inputs from the instruction register, which are supplied over the -bit wide instruction bus. This can be seen in Figure of the Introduction to Thumb document, which was also cited on page of Exhibit. See Mar Decl. Ex. D [Introduction to Thumb], at. Figure illustrates how Thumb instructions are decoded and decompressed. Id. (caption states Thumb decoding and decompression ). A person having ordinary skill in the art would understand that each instruction fetch would bring either one -bit ARM instruction or two - SUMMARY JUDG. / No. :0-cv-0 \.

7 Case:0-cv-0-JW Case:0-cv-00-JW Document- Document0 Filed0// Filed0/0/ Page Page of 0 bit Thumb instructions over a -bit bus into the instruction register within the CPU in the same memory cycle they are fetched.. In addition, in the amended Preliminary Infringement Contentions for the Patent, Defendants have highlighted the presence of the -bit instruction register and its relationship to the decode stage in the claim chart to reflect the clarifying claim phrase wherein the microprocessor system comprises an instruction register configured to store the multiple sequential instructions and from which instructions are accessed and decoded. See Mar Decl. Ex. C [Exemplar Claim Chart] at PIC000 (reproduced below). 0. The relationship between the instruction register and the instruction decode stage is also shown in the top portion of Figure - of the ARMTDMI Technical Reference Manual (reproduced below). The instruction decode stage illustrated in Figure of the Introduction to Thumb document (Mar Ex. D) is also found in the blue box below. The red box highlights the -bit instruction register within the CPU, which stores the instructions that will be decoded during the decode stage. (figure on next page) SUMMARY JUDG. / No. :0-cv-0 \.

8 Case:0-cv-0-JW Case:0-cv-00-JW Document- Document0 Filed0// Filed0/0/ Page Page of 0 0 Mar Decl., Ex. I [ARMTDMI Technical Reference Manual] at -. II. HOW ONE OF ORDINARY SKILL IN THE ART UNDERSTANDS THE TERM RING OSCILLATOR AS CLAIMED IN THE AND PATENTS. A person having ordinary skill in the art would understand that a ring oscillator is a structure consisting of a multiple (more than one), odd number of inversions arranged in a loop. See //0 Memorandum Opinion and Order, Case No. :0-cv- TJW (E.D. Tex.) ( Judge Ward s Markman Order ) at (Chen Claim Construction Repsonsive Decl., Ex. A (Dkt. -).. The Mead and Conway textbook, Introduction into VLSI Systems, (Mar Decl., Ex. J) which was cited in the portion of Judge Ward s Markman Order construing ring oscillator, explains at p. that in a ring oscillator circuit: Rings of an odd number of inversions have no stable conditions and will oscillate with the period that is some odd submultiple of the delay time twice around the ring. SUMMARY JUDG. / No. :0-cv-0 \.

9 Case:0-cv-0-JW Case:0-cv-00-JW Document- Document0 Filed0// Filed0/0/ Page Page of 0 0. As explained more fully below, a person having ordinary skill in the art would understand that Fig. of U.S. Patent No.,, ( Talbot ) (Chen Claim Const. Decl., Ex. B) does not disclose a ring oscillator because the oscillator of Talbot would maintain an oscillation with only the Schmitt trigger and the capacitor(s). Talbot also does not characterize Figure of the patent as a ring oscillator.. The Talbot oscillator may oscillate by employing only the Schmitt trigger and capacitor(s). In contrast, as recognized by Judge Ward in his Markman Order, and as described in the Mead and Conway textbook (pp.-), a ring oscillator requires multiple, odd number of inversion stages and is not capable of oscillating with only one inversion stage.. The oscillator in Figure of Talbot is capable of oscillating with only the capacitor 0 (and ) and the Schmitt trigger (), where the output of the Schmitt trigger is directly wired back to the input of the Schmitt trigger. The remaining structures, transistors - and inverter, could be eliminated without affecting the ability of the Talbot oscillator to oscillate. As noted by Acer s expert, Dr. Wolfe (see of Dkt. - in case no. 0-cv-0), a Schmitt trigger does not change the output of a signal (from 0 to or from to 0) until the input voltage meets a certain threshold level. The capacitor 0 (and ) are used to charge and discharge the voltage needed to attain the threshold voltage used to trigger the Schmitt trigger. A Schmitt trigger employs different threshold voltages for triggering from LOW to HI and HI to LOW transitions. These unequal threshold voltages allow the oscillation to be maintained (not to reach steady state) when combined with a capacitor as described. Assume 0 serves as the input to the Schmitt trigger, producing as the output. With the other structures eliminated, this output is connected to the capacitor 0, the capacitor will be charging, and voltage across the capacitor will start to rise. Once the capacitor 0 is charged to a particular amount of charge, the voltage across the capacitor will reach the switching threshold level of the Schmitt trigger (V T0 ). At this point, the output of the Schmitt trigger will change from to 0, and the capacitor will start to discharge. As the capacitor discharges, the voltage across capacitor 0 (which is connected to the input of the Schmitt trigger) will reach the switching threshold of the Schmitt trigger required to switch the output from 0 to (V T0 ). The threshold voltage V T0 is lower than the threshold voltage V T0, SUMMARY JUDG. / No. :0-cv-0 \.

10 Case:0-cv-0-JW Case:0-cv-00-JW Document- Document0 Filed0/0/ Filed0// Page0 Page of of 0 which causes the Schmitt trigger to switch the output from to 0. This is the inherent feature of a Schmitt trigger. The cycle will repeat, thereby creating the oscillating signal.. Contrary to a circuit described in Talbot, a single stage of a ring oscillator with an output connected to an input will not oscillate, but instead, will remain at a stable voltage level.. Therefore, a person having ordinary skill in the art would understand that Figure of Talbot is not a ring oscillator. III. ADDITIONAL DISCOVERY. I understand that Defendants have requested additional technical documents and 0 information from microprocessor designers and HTC. These types of documents and information would be useful to an infringement analysis of the HTC products. From my experience on microprocessor design teams, many types of documents are generated during the design process and when the microprocessors are incorporated into a larger product. These documents are typically stored in design databases. The design documents serve as the blueprint for the fabrication of the microprocessors and the incorporation of the microprocessors into larger products. Relevant documents generated during the design process include, but are not limited to, the following: Documents regarding how the embedded ARM processing cores in the microprocessors are programmed to be compliant with various ARM specifications, including the Thumb instruction state; and Schematics or block diagrams that show how the microprocessors are connected to memory in the HTC products, internal register-level diagrams of the ARM processor, and what types of memory are used, including the specifications for the memory. I declare under penalty of perjury under the laws of the United States of America that the foregoing is true and correct to the best of my knowledge. Executed on April,, at Las Cruces, New Mexico. SUMMARY JUDG. / No. :0-cv-0 Vojin G. Oklobdzija \.