Lecture 7: Sequential Networks

Transcription

1 Lecture 7: Sequential Networks CSE 14: Components and Design Techniques for Digital Systems Spring 214 CK Cheng, Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1

2 Sequential Networks Memory Components Hierarchy of Memory Basic Mechanism of Memory Types of Flip-Flops Implementation Finite State Machine 2

3 Part II. Sequential Networks (Ch. 3) Memory / Time steps x i s i y i Clock Memory: Flip flops Specification: Finite State Machines Implementation: Excitation Tables y i =f i (S t,x) s i t+1 =g i (S t,x) 3

4 What is a sequential circuit? A circuit whose output depends on current inputs and past outputs A circuit with memory 4

5 Why do we need circuits with memory? A. Complex systems often consist of circuits that perform a sequence of tasks B. Circuits with memory can be used to store data C. Both A and B 5

6 The connection between sequences and memory What differentiates a musical piece from a cacophony? What is the role of memory in playing a musical piece (essentially a sequence of notes)? 6

7 Sequential Network vs. Combinational Logic: : Which of the following is FALSE? A. Combinational logic can replace any sequential network to realize the same function. B. Sequential networks use the same set of logic gates as combinational logic. C. Sequential networks can implement a CPU. D. Sequential networks require a precise clock for timing. 7

8 Hierarchy of Memory Devices Memory Bank (Farms of memory cells) Register (Vector of memory cells) Flip-Flop (Single memory cell) SR, D, T, JK flip-flops (Different types of memory cells) State Tables (Truth table of sequential machine) Characteristic Expressions (Switching algebraic expression of sequential machine) 8

9 Fundamental Memory Mechanism I2 I1 I1 I2 9

10 Memory Mechanism: Capacitive Load Fundamental building block of sequential circuits Two outputs:, There is a feedback loop! In a typical combinational logic, there is no feedback loop. No inputs I2 I1 I1 I2 1

11 Capacitive Loads Consider the two possible cases: = : then = 1 and = (consistent) 1 I1 I2 1 = 1: then = and = 1 (consistent) I1 1 1 I2 Bistable circuit stores 1 bit of state in the state variable, (or ) But there are no inputs to control the state 11

12 iclicker. Given a memory component made out of a loop of inverters, the number of inverters has to be A. Even B. Odd 12

13 SR (Set/Reset) Latch SR Latch R N1 S N2 Consider the four possible cases: S = 1, R = S =, R = 1 S =, R = S = 1, R = 1 13

14 SR Latch Analysis S = 1, R = : R N1 S 1 N2 S =, R = 1: R 1 N1 S N2 14

15 SR Latch Analysis S = 1, R = : then = 1 and = R N1 S 1 N2 S =, R = 1: then = and = 1 R 1 N1 S N2 15

16 SR Latch Analysis S = 1, R = 1: R 1 N1 S 1 N2 16

17 SR Latch Analysis S =, R = : R N1 S N2 17

18 SR Latch Analysis S =, R = : then = prev prev = prev = 1 R N1 R N1 S N2 S N2 S = 1, R = 1: then = and = R 1 N1 S 1 N2 18

19 S y y = (S+) R = (R+y) 19

20 Flip-flop Components SR F-F (Set-Reset) S R y Inputs: S, R State: (, y) 2

21 Id (t) y(t) S R (t 1 ) y(t 1 ) (t 2 )y(t 2 ) (t 3 ) y(t 3 ) SR 11 State y State Diagram Transition SR 21

22 CASES: SR=1, (,y) = (,1) SR=1, (,y) = (1,) SR=11, (,y) = (,) SR = => if (,y) = (,) or (1,1), the output keeps changing. To avoid the SR latch output from toggling or behaving in an undefined way which input combinations should be avoided: A. (S, R) = (, ) B. (S, R) = (1, 1) 22

23 SR Latch Analysis S =, R = : then = prev and = prev (memory!) prev = prev = 1 R 1 N1 R N1 1 S N2 1 S 1 N2 S = 1, R = 1: then = and = (invalid state: NOT ) 1 R N1 S 1 N2 23

24 CASES: SR=1, (,y) = (,1) SR=1, (,y) = (1,) SR=11, (,y) = (,) SR = => if (,y) = (,) or (1,1), the output keeps changing Solutions: 1) SR = (,), or 2) SR = (1,1). inputs PS (t) State table SR Characteristic Expression (t+1) = S(t)+R (t)(t) (t+1) NS (next state) 24

25 SR Latch Symbol SR stands for Set/Reset Latch Stores one bit of state () Control what value is being stored with S, R inputs Set: Make the output 1 (S = 1, R =, = 1) Reset: Make the output (S =, R = 1, = ) Must do something to avoid invalid state (when S = R = 1) SR Latch Symbol R S 25

26 D Latch Two inputs:, D : controls when the output changes D (the data input): controls what the output changes to Function When = 1, D passes through to (the latch is transparent) When =, holds its previous value (the latch is opaque) Avoids invalid case when NOT D Latch Symbol D 26

27 D Latch Internal Circuit SR Latch Symbol R S D 27

28 D Latch Internal Circuit D D R S R S D D X D S R 28

29 D Latch Internal Circuit D R R D D S S D X D X 1 S R prev prev 29

30 D Flip-Flop Two inputs:, D Function The flip-flop samples D on the rising edge of When rises from to 1, D passes through to Otherwise, holds its previous value changes only on the rising edge of A flip-flop is called an edge-triggered device because it is activated on the clock edge D D Flip-Flop Symbols 3

31 D Flip-Flop Internal Circuit D D N1 D L1 L2 31

32 D Flip-Flop Internal Circuit Two back-to-back latches (L1 and L2) controlled by complementary clocks When = L1 is transparent, L2 is opaque D passes through to N1 When = 1 L2 is transparent, L1 is opaque N1 passes through to D D L1 Thus, on the edge of the clock (when rises from 1) D passes through to N1 D L2 32

33 D Flip-Flop vs. D Latch D D D (latch) (flop) 33

34 D Flip-Flop vs. D Latch D D D (latch) (flop) 34

35 Latch and Flip-flop (two latches) A latch can be considered as a door =, door is shut = 1, door is unlocked A flip-flop is a two door entrance = 1 = = 1 35

36 D Flip-Flop (Delay) D D D L1 N1 D L2 Id D (t) (t+1) State table PS D NS= (t+1) Characteristic Expression: (t+1) = D(t) 36

37 iclicker Can D flip-flip serve as a memory component? A. Yes B. No 37

38 JK F-F J K State table PS JK ? 1 1 1? (t+1) 38

39 JK F-F J K State table PS JK (t+1) Characteristic Expression (t+1) = (t)k (t)+ (t)j(t) 39

40 T Flip-Flop (Toggle) T State table PS T (t+1) Characteristic Expression (t+1) = (t)t(t) + (t)t (t) 4

41 Using a JK F-F to implement a D and T F-F x J K iclicker What is the function of the above circuit? A. D F-F B. T F-F C. None of the above 41

42 Using a JK F-F to implement a D and T F-F T J K T flip flop 42

43 Reading [Harris] Chapter 3: 3.3, 3.4.1,