Multi bit Retention Flip-Flop For Zigbee SoC s

Transcription

1 Multi bit Retention Flip-Flop For Zigbee SoC s Namepalli Malathi*, B.R.K. Singh** *PG Student, MIC College of Technology, Kanchikacherla, Krishna, AP, India, , nmalathi228@gmail.com **Associate Professor, MIC College of Technology, Kanchikacherla, Krishna, AP, India, , bondilirk@gmail.com ABSTRACT Zigee-SoC is a wireless sensor network which integrates all the components of the Zigbee device in a single chip. Zigbee SoC gives assistance to a number of power modes including standby mode. This standby mode extends the battery life. So the standby power reduction is significant to extends the battery life. To ensure that Zigbee SoCs can operate accurately after recurring to active mode, the logic states must be preserved. So I use level converting retention flip flop (RFF) to store the logic states. We have several types of retention flip flops at present. This RFF acquiesce the voltage regulator to be turned off in the standby mode, thus it reduces the standby power further it stores the logic states of the circuit. INTRODUCTION In present days, the portable devices are prominent and used widely. A portable device is nothing but hard drive which stores digital data. These must be making littler size and we need to enhance battery life. I am using Low power circuit technology to meet these requirements. The power supply that is VDD has to be reduced to extend the battery life. For this, powers down techniques are available and were shortlisted in the thesis. Power down technique can decline the power consumption in portable devices. In this technique, whenever the device is not in active condition the clock must be stopped to reduce the frequency of operation results in reduction of power consumption as well as it extends the battery life [1-5]. However, these techniques are not suitable for portable devices because even if the device is in the off condition there is a standby leakage current. So, in order to reduce the standby leakage current I introduce Multi Threshold-voltage CMOS (MTCMOS) scheme. In this scheme, power gating technique was used. Power gating technique is nothing but shutting off current to the blocks which are not in use thus we can cut down the stand by leakage current. In MTCMOS scheme, I use high threshold voltage transistors to cut off leakage. But at any moment, the device is in sleep mode; formerly the data will lose because power supply is not employed for the parts of the devices in the off condition. So we have to preserve data in sleep mode. If we retain data in sleep mode, we can uphold the operation of the circuit by translating the core to active mode [6]. For this purpose I access, retention logic on Zigbee- SoC s by using transmission gates. In flip-flops information is collected in cross-coupled inverters. Cross-coupled inverters can hold their states in the shut down mode, if their inputs are appropriately gated. In view of this, basic clock and information gating hardware are utilized in flip-flops to hold their information in the shut down mode without utilizing any additional preserving latches [7]. To accomplish higher thickness and performance and lower power dissipation, CMOS innovation has been scaled down for quite a few years. Supply voltage (VDD) has been scaled down to hold the power consumption under control. Subsequently, the transistor limit voltage (Vth) must be similarly scaled to keep up a high drive current and accomplish performance. Be that as it may, the threshold voltage scaling results in the significant increment of the leakage current [8]. Accordingly, as a consequence of technology scaling, leakage current is big donor to total power consumption. Leakage current is available in both dynamic and standby methods of operation. In spite of diminish the standby leakage power utilization; circuits can be placed in the shut down mode by shutting off the power amid the standby mode [9]. FIGURE 1 STRUCTURE OF RETENTION FLIP-FLOP Page 1198

2 The power can be terminated by terminating either the supply voltage (VDD) or ground (GND) of the circuit. The transistors terminating the power are called sleep transistors. For terminating the VDD (gated -VDD), PMOS sleep transistors are required between the core VDD and virtual VDD of the circuit. On the other hand, for terminating the GND (gated -GND), NMOS sleep transistors are utilized between the core GND and virtual GND of the circuit [10]. Since the sleep transistors are genuinely substantial, gated-gnd is elected as gated-vdd in light of the fact that the NMOS sleep transistors can be much littler than the PMOS sleep transistors. The condition of a circuit which is maintained in flip-flop may be lost in the shut down mode. So, in shut down applications the condition of the circuit is required to be saved [11]. Shadow or balloon latches are useful in shut down mode for preserving states. The balloon latch and a few switches which are not in the basic ways utilize high threshold voltage (high -Vth) transistors to decrease their leakage power, since they are constantly powered. The internal clock and data gating hardware is just made out of one inverter and one PMOS transistor. The inverter of the clock-gating hardware may not be required if the clock is as of now cushioned through the clock dispersion system. In the sleep mode, the PMOS transistor pulls up the clock data hub of the flip-flop to VDD. In this way, the information data is likewise consequently gated by the transmission gate at the info of the flip-flop. In addition, the circle of the cross coupled inverters in the master latch is shut to hold the information put away in the master latch [7]. In this plan just the inverter that produces signal CKB is required to be constantly powered, and hence, can be actualized utilizing high-vth transistors. The information maintenance TGFF (DR-TGFF) and the balloon TGFF are planned in the 70nm CMOS innovation hub, utilizing Berkeley Prescient Innovation Models. The TGFF with no sleep transistor or information maintenance hardware and with all low-vth transistors is additionally intended for examination. 2. RETENTION ARCHITECTURE IN ZIGBEE SoCS There are three types of retention architectures for zigbee socs as follows. 2.1 RETENTION LOGIC WITH THE MULTI THRESHOLD-VOLTAGECMOS SCHEME A power gating plan utilizing multi threshold-voltage CMOS (MTCMOS) produce one answer for decreasing the standby force and conventional RFFs embrace the MTCMOS plan appeared in Figure 2. retention logic supplied by VDD, core conserves the logic states in the standby mode, though the calculation logic supplied by the virtual supply voltage (VDD, virtual) is power gated to decline the standby power [10]. Be that as it may, the power decrement constrained in light of the fact that the voltage controller creating VDD, core (VR2) must stay on during the standby mode to supply retention logic. Another imperfection of the power gating plan utilizing MTCMOS is the region wastefulness because of the necessity of expansive head/foot switches [12]. Figure 2: RETENTION ARCHITECTURE WITH MTCMOS SCHEME 2.2 RETENTION LOGIC WITH ULTRALOW SUPPLY VOLTAGE The utilization of a ultralow supply voltage for holding the data takes into account the minimization of the leakage power amid the standby mode. In this way, the leakage power plan with the ultralow-supply voltage retention logic appeared in Figure 3 is another answer for lessening the standby force. Since every one of the transistors in the retention logic work in powerless reversal with a low drain- to-source voltage, the sub threshold leakage current is exponentially decreased. Contrasted and the plan in Figure 3 an extra voltage controller (VR3) creating a forcefully scaled supply voltage is utilized just for the maintenance rationale at the expense of zone overhead and dynamic force [11]. This power management method likewise has the same drawback as the force administration plan in Fig. in that the voltage controller for the retention logic (VR3) must be turned on amid the standby mode. Subsequently, a power management plan to shut off the voltage controller in the standby mode is required. Page 1199

3 Bluetooth can't serve this section as they have to great degree high power utilization because of the high throughput they convey. Zigbee is another individual territory system radio correspondences standard, which has been intended to serve low information rate, low power fragments. FIGURE 3: RETENTION ARCHITECTURE WITH ULTRA LOW SUPPLY VOLTAGE 2.3 RETENTION LOGIC WITH I/O SUPPLY VOLTAGE The power management plan for shut off the voltage controller in the standby mode is appeared in Figure 4. In this construction modelling, the voltage controller for the retention logic is specifically supplied from V DD,IO. The standby power of the retention logic itself is really somewhat extensive inferable from the utilization of V DD, IO that is bigger than V DD, core. Then again, contrasted and the power dissipation of the voltage controller for retention logic, the increment in the standby force brought about by V DD, IO is inconsequential. The present moving through the turned-on voltage controller is a couple microamperes. This current is much bigger than that moving through the few hundred bits of the maintenance rationale required in Zigbee SoCs. To utilize this force administration plan, level change between the V DD,core and V DD, IO spaces ought to be upheld; generally, the power management plan can't be connected attributable to the dc current way made by the level contrast in the middle of V DD,core and V DD,IO. The proposed RFF accomplishes level-up change from V DD, core to V DD,IO by an embedded nmos pass-transistor leveltransformation plan utilizing a low-just flag transmitting system. The fundamental and stringent necessity for zigbee system on chips is power utilization, as at times, power sources are accessible in basic and dangerous spots. Additionally it is neither reasonable nor plausible to have batteries changed each few days. Technologies like x nor FIGURE 4: RETENTION ARCHITECTURE WITH I/O SUPPLY VOLTAGE 3. PROPOSED SCHEME Retention flip-flops have been generally utilized as a part of power gated structures to store information amid rest mode. Then again, their extra space and draining power render it basic to minimize the entire retention storage area. The present business practice replaces every flip-flop with single piece retention ones, which fundamentally restrains the outline opportunity and yields imperfect structures. Towards this, without precedent for the writing, we propose the idea and the configuration of multi bit retention flip-flops, with which just chose flip-flops should be alternated. The method can altogether diminish the quantity of bits that should be saved and in this way the leakage power, yet needs a few clock cycles for mode move. Also, useful algorithm is produced to minimize the aggregate retention storage size subject to mode move inactivity requirement. 3.1 MULTIBIT RETENTION FLIP-FLOP Figure 5 shows structure of multi bit retention flip-flop. Here we have two latches namely master latch and slave latch. The master latch is likewise taking into account a cross-coupled-inverter latch as the DFF, and an extra data transmission path (M3 and M1) is implanted. Both thin and thickoxide transistors are utilized, and the core logic and retention logic are provided by V DD, core and VDD, IO separately. Level up transformation from the V DD,core area in the master latch to the V DD, IO space Page 1200

4 in the slave latch is accomplished through a nmos pass-transistor level-change. Figure 5 structure of multi bit retention flip-flop 3.1 NMOS PASS TRANSISTOR LRVEL CONVERSION SCHEME In NMOS pass transistor level conversion scheme, by utilizing low supply voltage (VDDL) in noncritical ways, i.e., setting speed uncaring gates with supply voltage VDDL, and utilizing high supply voltage (VDDH) in speed sensitive paths, the entire device power utilization could be lessened without diminishing the execution. In NMOS pass transistor level conversion scheme, one end of the NMOS transistor N1 unites with the low-voltage input signal, and the level deviation point "sf" is lifted to (VDDL-Vth of the NMOS) through NMOS transistor N1. Attendant I2 will pull "sf up to VDDH. One NMOS transistor N1 and one inverter I2 are utilized to actualize the level deviating. condition of information in the master latch, and the voltage level can be changed over in the slave latch without producing a dc-current way on the grounds that just a low signal is transmitted at all times. In this way, the V DD, core field is altered into the V DD, IO field without the requirement for an extra level-up converter. Level-down transformation from V DD, IO to V DD, core happens at INV3 and INV4, which are made out of thick-oxide transistors yet supplied by V DD, core. In the standby mode, when RSTb is affirmed low, CK turns out to be low, and V DD, core is crashed by shutting off the voltage controller; for this situation, the slave latch is separated by turn off the access transistors (M1 and M2) and works as a retention latch to hold logic states by V DD, IO that is constantly turned on. Note that the sizes of the transistors on the data-to- deliberately. output path should be resolved There are two discussions, standby power and write-ability. As the standby power is absorbed by just a slave latch, INV1 and INV2 ought to be measured to minimize the sub threshold current that is commonly corresponds to the width of the transistor. On the other hand, in profound sub micrometer procedure innovation, Vt forcefully diminishes with a reduction in the channel width, and this is known as the backwards limit width impact (INWE). This impact result s in an exponential increment in the leakage current, making the INWE progressively significant with innovation scaling. 4. SIMULATION RESULTS 4.1 MULTIBIT RETENTION FLIP-FLOP RTL SCHEMATIC Figure 6: NMOS level shifting scheme 3.2 OPEARATION OF MULTI BIT RETENTION FLIP-FLOP The proposed RFF works as takes after When nodes X and Y (or Y and X) in the master latch are high and low, individually, an access transistor M4 (or M3) is turned on, and one more access transistor M3 (or M4) is turned off. At that point, the ON-state access transistor M4 (M3) shapes a transmission path between the master latch and the slave latch, and node Y (X) turns into an information of the transmissionn way. As such, just the transmission way from the master latch to the slave latch is resolved on the premise of the Figure 7 RTL SCHEMATIC OF RETENTION FLIP-FLOP Page 1201

5 proposed RFF is composed with thick-oxide transistors leakage current. REFERENCES of a stacked structure to reduce the standby FIGURE 8 GATE LEVEL RTL OF RETENTION FLIP-FLOP 4.2 SIMULATION OUTPUT OUTPUT DESCRIPTION The mechanism of retention flip-flop is to store the logic state whenever the system is in standby mode for continuous operation when system retrieves back to active mode. So if we give data to zigbee module, the retention logic stores the data in standby mode and gives the same as output whenever the system comes to active mode. By this simulation, the input data is 1000 is given to DATA [3:0]. The retentionn logic stores the given data and comes as output at OUT [3:0] port. 4.3 AREA REPORT SCHEMATIC [1] J.-S. Lee, Y.-W. Su, and C.-C. Shen, A comparative study of wirelessprotocols: Bluetooth, UWB, ZigBee, and Wi-Fi, IEEE Wireless Commun.,vol. 14, no. 4, pp , Nov [2] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada,, A 1-V high-speed MTCMOS circuit scheme for power-down applicationcircuits, IEEE J. Solid-State Circuits, vol. 32, no. 6, pp ,Jun [3] Jung-Hyun Park, Heechai Kang, Level- for Reducing Converting Retention Flip-Flop Standby Power in ZigBee SoCs Ieee Transactions On Very Large Scale Integration Systems. [4] W. Kluge et al., A fully integrated 2.4-GHz IEEE complianttransceiver for ZigBee applications, IEEE J. Solid-State Circuits,vol. 41, no. 12, pp , Dec [5] J.-S. Lee, Y.-W. Su, and C.-C. Shen, A comparative study of wirelessprotocols: Bluetooth, UWB, ZigBee, and Wi-Fi, IEEE Wireless Commun.,vol. 14, no. 4, pp , Nov [6] J. Hu, W. Liu, W. Khalil, and M. Ismail, Increasing sleep-modeefficiency by reducing battery current using a DC-DC converter, in Proc. IEEE Int. MWSCAS, Aug. 2010, pp [7] S. Liang, Y. Tang, and Q. Zhu, Passive wake- networks, in Proc. up scheme for wirelesssensor Int. CICIC, Sep. 2007, p [8] Y.-I. Kwon, S.-G. Park, T.-J. Park, K.-S. Cho, and H.-Y. Lee, An ultralow-power CMOS transceiver using various low-power techniques forlr-wpan applications, IEEE Trans. Circuits Syst. I, vol. 59, no. 2,pp , Feb [9] M. Albano and S. Chessa, Data centric storage in ZigBee wirelesssensor networks, in Proc. IEEE ISSCC, Jun. 2010, pp [10] S. Shigematsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada,, A 1-V high-speed MTCMOS circuit scheme for power-down applicationcircuits, IEEE J. Solid-State Circuits, vol. 32, no. 6, pp ,Jun [11] L. T. Clark, M. Kabir, and J. E. Knudsen, A low standby power flipflopwith reduced circuit and control complexity, in Proc. IEEE CICC,Sep. 2007, pp CONCLUSION The proposed MULTI BIT RFF achieves ultralow-standby power by adopting a power management scheme to use V DD, IO for data retention and to turn off the voltage regulator in the standby mode. In addition, the retention latch in the Page 1202