Noise Margin in Low Power SRAM Cells

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1 Noise Margin in Low Power SRAM Cells S. Cserveny, J. -M. Masgonty, C. Piguet CSEM SA, Neuchâtel, CH Abstract. Noise margin at read, at write and in stand-by is analyzed for the 6 transistor SRAM cell in a 0.18 µm process considering specific low power conditions such as low supply voltage and source-body biasing. These conditions reduce the noise margin. By using an asymmetrical cell design in which read is performed only on one of the two complementary bit lines, the noise margin can be improved and the bias limits extended for a reduced power consumption. Introduction The increasing complexity of integrated circuits results in a general power awareness [1], especially for the increasing number of portable battery (or accumulator) powered applications. In processor-based systems-on-chip the memories occupy an increasing part of the area, limit most of the time the speed and are the main part of the power consumption. The trend in the scaled down deep sub-micron technologies is toward an increased contribution of the static consumption [2], a major problem for the most frequent SRAM application, the cache memories [3, 4]. This increased contribution becomes even more important in the extreme case of applications with very long idle modes as in wireless micro sensor systems [5], in which the standby period is much longer than the active mode. The dynamic power consumption is directly related to the VDD supply, therefore there is a tendency to reduce its value as much as allowed by the speed requirements. Several techniques were proposed to further reduce the dynamic power reduction, among them the physically divided read bit line [6, 7] for the memories; in the case of the SRAM this technique uses an asymmetrical cell which is also interesting as a low leakage approach [8]. The static consumption is due to the leakage current that has several contributions as described in [9]. There are digital blocks that can be switched off in long stand-by modes, however special precaution is needed in flip-flop based storage circuits that have to be biased properly in order to maintain their information. In the case of the SRAM cell the source-body biasing allows important leakage reduction while the supply voltage is maintained to guarantee safe information storage [8, 10]. In this paper the safety of the 6-transistor SRAM cell operation at read, write and stand-by is analyzed by evaluating the effects on its noise margin of a reduced supply voltage and the use of the source-body bias leakage reduction technique. A reference minimum size symmetrical SRAM cell in a 0.18 µm process is considered first and the improvement possibilities offered by the asymmetrical cell are explored next.

2 The SRAM cell The generic 6-transistor SRAM cell that is considered in this paper is represented in Fig. 1. VDD mp0 mp1 SW SW1 B0 ms0 N0 N1 ms1 B1 mn0 SN mn1 VSS Fig. 1. The 6T SRAM cell with the possibility to separate the select gate signals (asymmetrical cell) and to apply a source-body bias to the NMOS transistors for leakage reduction In the basic symmetrical cell there is a unique word select signal applied to both ms0 and ms1 select NMOS gates (SW1 connected to SW) and the common source SN of the two pull-down NMOS mn0 and mn1 is connected to the ground VSS. The W/L ratios of the transistors on the two sides of the cell are the same. The reference cell in this 0.18 µm process uses minimum size transistors 0.22 µm / 0.18 µm for all inverter transistors (mp0, mp1, mn0 and mn1) and longer 0.22 µm / µm ms0 and ms1 select transistors. In Fig. 1 the possibility for separate select gate signals SW and SW1 has been shown, corresponding to the asymmetrical cell described in [6, 7]. With this cell read is performed only on the bit line B0 as only SW goes high. The dynamic consumption at read can be further reduced by physically splitting these single read bit lines into several sub-bit lines; as the sub-bit lines are connected to a fraction of the cells in the column, the capacitive load to be discharged is significantly reduced. Out of all precharged sub-bit lines only those for which a 1 is read will be discharged. On the other hand both bit lines are needed to write safely at any supply value without voltage boosters, therefore this asymmetrical cell needs separated SW and SW1 select signals, with a small area penalty. As only one select transistor is activated at read, the W/L ratios for the select and pull down NMOS transistors on the two sides of the cell can be optimized differently resulting in an asymmetrical design.

3 In the considered 0.18 µm process the static leakage is strongly dominated by the subthreshold current of the turned-off NMOS transistors, the minimum size PMOS leaking about 100 times less. With present process scaling tendencies towards much deeper nanometric devices, special care is needed to deal with important tunneling gate currents and gate induced drain leakage [9], even if the subthreshold leakage remains dominant [10], and it seems that for all these leakage components the NMOS will leak more than the PMOS. A source-body bias increasing the threshold is the best way to reduce the subthreshold leakage, however, it is interesting to notice that the source-body biasing is beneficial also for the gate current as it reduces the gate fields. In order to allow NMOS source-body biasing in the 6 transistors SRAM cell, the common source of the cross-coupled inverter NMOS (SN in Fig. 1) is not connected to the body. Body pick-ups can be provided in each cell or for a group of cells and they are connected to the VSS ground. A positive VSB bias between SN and VSS will reduce the subthreshold leakage of a non-selected cell (SW and SW1 at VSS). It is important to notice that, as both select transistors ms0 and ms1 have their gates at ground, their leakage current will decrease rapidly with this bias because, besides the body effect on the threshold voltage, there is the very strong exponential effect related to the increasing negative gate-source voltage; unfortunately, no such effect occurs for the cut-off pull-down transistor in the flip-flop mn0 or mn1, only the body effect reduces its leakage because it has the same SN node potential on its gate and source. Read and stand-by noise margin In order to estimate the safety of the data retention, the noise margin is extracted with the method described in the literature [11, 12] as the maximum size square that can be nested into the cross-coupled voltage transfer characteristics. Examples of transfer characteristics to be considered in stand-by and at read are shown in Fig.2. Vout (V) b a c y x z Vin (V) Fig. 2. Stand-by and read transfer characteristics at 125 C VDD = 0.9 V and V(SN) = 0 for the N-fast P-slow corner; the MOS W/L ratios in µm/µm are 0.22/0.18 (a, x, z), 0.42/0.18 (b, y) and 0.22/0.295 (c) for mn, 0.22/0.295 (x, y) and 022/0.18 (z) for ms and 0.22/0.18 for mp The central characteristics (a and x) in Fig. 2 are those of the reference cell.

4 The transfer characteristic to be considered in stand-by is that of the inverter in the flip-flop (mp0 and mn0 or mp1 and mn1); the three examples in Fig. 2 (a, b and c) show the effect of a stronger (b) and weaker (c) than the reference (a) inverter NMOS. At read (x, y and z in Fig. 2), the loading effect of the select MOS (ms0 respectively ms1), with the bit line precharged at VDD when the read starts, shifts the low output voltage part of the characteristic upwards; this shift is more important when the inverter NMOS is weaker (x above y) and the select NMOS stronger (z above x). As a result, the noise margin is much smaller at read than in stand-by (Fig. 3). Read Vout (V) Stand-by Vin (V) Fig. 3. Worst case (N-fast P-slow 125 C) stand-by and read static noise margin analysis for the reference symmetrical cell at V(SN) = 0 and VDD = 0.9 V Such stand-by and read noise margins of the reference symmetrical cell extracted by simulation are analyzed in the following results. As the VDD supply voltage decreases from its nominal 1.8 V value, both stand-by and read noise margins decrease (Fig. 4). As many perturbation signals are related to the VDD value, it is interesting to analyze also the noise margin to VDD ratio; this relative noise margin first improves at moderate VDD reduction before taking down at the lower values. As expected, the N-fast P-slow process corner is the worst case. Also the highest temperature is worst, except for the stand-by margin at low VDD. If a NMOS source-body bias VSBN is applied between the SN node and the VSS ground (Fig. 5), the worst-case stand-by noise margin decreases, mainly at low VDD; notice the temperature effect change between high and low VDD. There is no such temperature effect change for the read noise margin (always N-fast P-slow highest temperature worst case), however it increases with VSBN at high VDD and decreases only at low VDD. Consequently, at low VDD, where the VSBN source-body bias dangerously reduces the read noise margin while the stand-by margin, even if reduced, remains acceptable, it is recommended to switch this bias off at read [8, 10].

5 Fig. 4. VDD supply voltage dependence of the stand-by and read noise margin (top) and noise margin over VDD ratio (bottom) for the symmetrical reference cell without source-body bias for different process corners (TT typical, FS N-fast P-slow worst case) and temperatures Fig. 5. VSBN (SN node source-body bias) dependence of the stand-by (top) and read (bottom) noise margin for the symmetrical reference cell for the worst-case N-fast P-slow process corner at different VDD supply voltages and temperatures

6 Noise margin at write In order to modify the data stored in the cell the critical task is for the bit line that has to pull down the internal node N0 or N1 previously high for the selected cell (SW and SW1 high). The write noise margin is defined as the maximum voltage on this bit line for which the cell flips; in the presence of a VSBN bias, its value is subtracted from the bit line flipping value. Both the write noise margin and its VDD relative value decrease with the VDD supply (Fig. 6). There is a severe limitation for the minimum acceptable VDD value that gives the bottom requirement of at least a 10% relative margin. As expected, the N-slow P-fast process corner is the worst case, while the temperature effect changes between high and low VDD values. Fig. 6. VDD supply voltage dependence of the write noise margin (top) and noise margin over VDD ratio (bottom) for the symmetrical reference cell without source-body bias for different process corners (TT typical, SF N-slow P-fast worst case) and temperatures In the presence of a NMOS source-body bias VSBN, the write noise margin further decreases (Fig. 7), becoming totally unacceptable at low VDD. In fact, for the noise margin requirements, the write is far more demanding than the read. At 0.9 V with a VSBN = 0.3 V the worst case stand-by margin of 173 mv is very good, the 80 mv read margin is just under a 10% limit, however at write there is no margin left at all, it is negative; it is even more important to connect the SN node to ground at write than at read, however both are welcome as done in [8, 10].

7 SF -40 C Noise margin (V) SF -40 C SF 125 C SF 125 C 1.8 V 0.9 V VSBN (V) Fig. 7. VSBN (SN node source-body bias) dependence of the write noise margin for the symmetrical reference cell in the worst-case N-slow P-fast process corner at different VDD supply voltages and temperatures Noise margin improvement with the asymmetrical cell The asymmetrical cell has been proposed in [6, 7] to reduce the dynamic power. Here the capability of this approach to improve the noise margin at low VDD and in the presence of a VSBN bias is searched for. In the following example (Fig. 8 and Fig. 9) an extreme bias case is used to better demonstrate what can be achieved by making the cell asymmetrical. symmetrical Vout (V) asymmetrical Vin (V) Fig. 8. Worst case (N-fast P-slow 125 C) read noise margin analysis for the symmetrical and asymmetrical cells with the reference MOS W/L ratios at VDD = 0.6 V and VSBN = 0.3 V

8 In this example VDD = 0.6 V is extremely low especially because a VSBN bias is also used. The cross-coupled transfer characteristics of the symmetrical cell not only show a very small noise margin, they also display 5 crossings instead of 3 (Fig. 8); such 5 crossings are observed also at VDD = 0.9 V (Fig. 3 in [8]), however with the 2 extra crossings not so far from the middle one. As in the asymmetrical cell read activates only SW, the transfer characteristic of the other side is that of the inverter mn1 and mp1 that is no more loaded by the cut-off ms1 select NMOS. Using still the same W/L values the noise margin is not improved, however the 5 crossings are avoided. Optimizing differently the W/L ratios on the two sides in a further step, the noise margin can be substantially increased with a stronger mn0 and a weaker mn1 (Fig. 9). mn1 0.22/0.295 mn0 0.42/0.18 mn0 = mn1 0.22/0.18 Vout (V) Vin (V) Fig. 9. Worst case (N-fast P-slow at 125 C) read noise margin analysis comparison for the asymmetrical cell using the reference W/L ratios (mn0=mn1 0.22µm/0.18µm) with a longer mn1 (0.295 µm) and with a larger mn0 (0.42 µm) at VDD = 0.6 V and VSBN = 0.3 V In the asymmetrical cell the requirements are very different on the two sides. On the read side mn0 and ms0 should be strong enough for the required driving capability and the ratio of their W/L (called transfer ratio) should be large enough for the desired read disturb noise margin. More relaxed requirements apply to the other side used only to write and keep the stored data. It has been shown in Fig. 2 that a weaker mn shifts the inverter characteristic to the right and a stronger mn and a weaker ms (i.e. a larger transfer ratio) shifts the ms loaded inverter characteristic downwards closer to the axis, therefore to the left in the cross-coupled representation in Fig. 9. Notice that in the symmetrical cell increasing the mn width (i.e. the transfer ratio) with the same value as in Fig. 9, the cross-coupled characteristics are as bad as those in Fig. 8 just shifted to the left, with the same 5 crossings shape and small margin. The freedom to shift separately the two characteristics in the asymmetrical cell allows for a better noise margin, or a smaller transfer ratio constraint for a required margin.

9 The reduced leakage cell proposed in [8], besides the source-body bias technique, uses less-leaking non-minimal length transistors whenever effective; the asymmetrical cell is favorable to implement this. As shown in Fig. 9, a longer mn1 improves the noise margin, and a relaxed transfer ratio requirement allows also for a longer mn0 if its width and the ms0 W/L are adapted for the desired speed; the VSBN bias is very effective to reduce the ms0 and ms1 leakage (they have a negative gate-source voltage in a non-selected cell with SW and SW1 at ground), therefore they can be minimum length. These arguments have been used to design an asymmetrical cell that has much less leakage, more driving capability and a little better noise margin (Fig. 10) than the reference cell; the area penalty is about 25%, however a larger number of metal pitches takes advantage of this area increase. Noise margin (V) 0 1 Stand-by Read Noise margin (V) 0 1 Write VSBN (V) Fig. 11. VSBN (SN node source-body bias) dependence of the worst case noise margin for the designed asymmetrical cell at VDD = 0.9 V for stand-by and read (N-fast P-slow 75 C) and for write (N-slow P-fast -25 C) in the states 1 (node N1 high) and 0 (node N0 high) Notice that the noise margin (as the stand-by leakage) is better for the state 1 than 0 as there are no reasons not to make them better than the more stringent stage 0 design requirements. Locally switched source-body bias is used [8] to keep the active mode read and write noise margins and the speed as without such a bias. First measurements of the SRAM using this cell in an industrial application show it is fully functional.

10 Conclusions Low power SRAM use reduced VDD supply for less dynamic power consumption and source-body biasing for static leakage reduction. The present analysis shows that in such conditions the noise margin of the SRAM cell is reduced, and therefore the range of applicability of these techniques is limited by the noise margin requirements for a safe operation. An asymmetrical cell approach has been proposed to reduce the dynamic power [6, 7] and the leakage [8]. In such an asymmetrical cell, in which read is performed only on one of the two complementary bit lines, it is possible to improve the noise margin performance at low VDD and in the presence of a source-body bias taking advantage in the design of the difference in requirements on the side used for read and on the side used only to write and to keep the stored data. Simulated results are shown for the asymmetrical cell designed in a standard single threshold voltage 0.18 µm digital process. The SRAM using this asymmetrical cell has been integrated in a RF transceiver circuit for an industrial wireless system; first measurements show that this SRAM is fully functional. References [1] T. Sakurai, Perspectives on Power-Aware Electronics, Plenary Talk 1.2, Proc. ISSCC 2003, San- Francisco, CA, Feb. 9-13, 2003, pp [2] C. Piguet, S. Cserveny, J. -F. Perotto, J. -M. Masgonty: Techniques de circuits et méthodes de conception pour réduire la consommation statique dans les technologies profondément submicroniques, Proc. FTFC 03, pp [3] H. Hanson, M. S. Hrishikesh, V. Agarwal, S. W. Keckler, D. Burger, Static Energy Reduction Techniques for Microprocessor Caches, IEEE Trans. VLSI Systems, vol. 11, pp , June 2003 [4] A. Agarwal, H. Li, K. Roy, A Single-Vt Low-Leakage Gated-Ground Cache for Deep Submicron, IEEE J. Solid-State Circuits, vol. 38, pp , Feb [5] A. Chandrakasan, R. Min, M. Bhardwaj, S. -H. Cho, A. Wang, Power Aware Wireless Microsensor Systems, Proc. ESSCIRC 2002, pp [6] J. -M. Masgonty, S. Cserveny, C. Piguet Low Power SRAM and ROM Memories, Proc. PATMOS 2001, paper 7.4 [7] S. Cserveny, J. -M. Masgonty, C. Piguet, F. Robin, Random Access Memory, US Patent US B1, April 2, 2002 [8] S. Cserveny, J. -M. Masgonty, C. Piguet, Stand-by Power Reduction for Storage Circuits, in J. J. Chico and E. Macii (Eds.): PATMOS 2003, LNCS 2799, pp , Springer 2003 [9] K. Roy, S.Mukhopadhyay, H. Mahmoodi-Meimand, Leakage Current Mechanism and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuit, Proc. IEEE, vol. 91, pp ,Feb [10] A. Agarwal, K. Roy: A Noise Tolerant Cache Design to Reduce Gate and Sub-threshold Leakage in the Nanometer Regime, Proc. ISLPED 03, pp [11] E. Seevinck, F. J. List, J. Lohstroh Static-Noise Margin Analysis of MOS SRAM Cells, IEEE J. Solid-State Circuits, vol. 22, pp , Oct [12] A. J. Bhavnagarwala, X. Tang, J. D. Meindl The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability, IEEE J. Solid-State Circuits, vol. 36, pp , April 2001

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