CprE 281: Digital Logic
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1 CprE 281: igital Logic Instructor: Alexander Stoytchev
2 Registers CprE 281: igital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
3 Administrative Stuff Homework 8 is due next Monday. The second midterm exam is next Friday.
4 Midterm Exam #2 Administrative Stuff When: Friday October 4pm. Where: This classroom What: Chapters 1, 2, 3, 4 and The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes).
5 Midterm 2: Format The exam will be out of 130 points You need 95 points to get an A for this exam It will be great if you can score more than 100 points. but you can t roll over your extra points L
6 Midterm 2: Topics Binary Numbers and Hexadecimal Numbers 1 s complement and 2 s complement representation Addition and subtraction of binary numbers Circuits for adders and fast adders Single and ouble precision IEEE floating point formats Converting a real number to the IEEE format Converting a floating point number to base 10 Multiplexers (circuits and function) Synthesis of logic functions using multiplexers Shannon s Expansion Theorem
7 Midterm 2: Topics ecoders (circuits and function) emultiplexers Encoders (binary and priority) Code Converters K-maps for 2, 3, and 4 variables Synthesis of logic circuits using adders, multiplexers, encoders, decoders, and basic logic gates Synthesis of logic circuits given constraints on the available building blocks that you can use Latches (circuits, behavior, timing diagrams) Flip-Flops (circuits, behavior, timing diagrams) Registers and Register Files
8 Review of Flip-Flops
9 A simple memory element with NOT Gates x x x
10 A simple memory element with NAN Gates x x x
11 A simple memory element with NOR Gates x x x
12 Basic Latch
13 A simple memory element with NOR Gates
14 A simple memory element with NOR Gates
15 A simple memory element with NOR Gates Set Reset
16 A memory element with NOR gates Reset Set [ Figure 5.3 from the textbook ]
17 Two ifferent Ways to raw the Same Circuit [ Figure 5.3 & 5.4 from the textbook ]
18 R S SR Latch: Circuit and Truth Table a b S R a b 0 0 0/1 1/ (no change) (Undesirable) (a) Circuit (b) Truth table [ Figure 5.4a,b from the textbook ] NOR Gate NOR Gate Truth table x 1 x 2 f
19 Gated SR Latch
20 Circuit iagram for the Gated SR Latch [ Figure 5.5a from the textbook ]
21 Circuit iagram for the Gated SR Latch This is the gate of the gated latch
22 Circuit iagram for the Gated SR Latch Notice that these are complements of each other
23 Gated SR Latch: Circuit iagram, Characteristic Table, and Graphical Symbol (Undesirable) [ Figure 5.5 from the textbook ]
24 Gated SR latch with NAN gates S Clk R [ Figure 5.6 from the textbook ]
25 Gated SR latch with NAN gates S Clk R In this case the gate is constructed using NAN gates! Not AN gates.
26 Gated SR latch with NAN gates S Clk R Also, notice that the positions of S and R are now swapped.
27 Gated SR latch with NAN gates S 1 S Clk = 1 R 1 R Finally, notice that when Clk=1 this turns into the basic latch with NAN gates, i.e., the SR Latch.
28 Gated SR latch with NOR gates Gated SR latch with NAN gates S Clk R
29 Gated SR latch with NOR gates Gated SR latch with NAN gates S Clk R Graphical symbols are the same
30 Gated SR latch with NOR gates (undesirable) Gated SR latch with NAN gates S Clk R (undesirable) Characteristic tables are the same
31 Gated Latch
32 Circuit iagram for the Gated Latch [ Figure 5.7a from the textbook ]
33 Gated Latch: Alternative esign Clk [
34 Gated Latch: Circuit iagram, Characteristic Table, and Graphical Symbol Note that it is now impossible to have S=R=1. When Clk=1 the output follows the input. When Clk=0 the output cannot be changed. [ Figure 5.7a,b from the textbook ]
35 Setup and hold times for Gated latch t su t h Clk Setup time (t su ) the minimum time that the signal must be stable prior to the the negative edge of the Clock signal Hold time (t h ) the minimum time that the signal must remain stable after the the negative edge of the Clock signal [ Figure 5.8 from the textbook ]
36 Master-Slave Flip-Flop
37 Constructing a Master-Slave Flip-Flop From Two Latches Master Slave
38 Constructing a Master-Slave Flip-Flop From Two Latches Master Slave
39 Constructing a Master-Slave Flip-Flop From Two Latches Master Slave
40 Constructing a Master-Slave Flip-Flop From Two Latches [ Figure 5.9a from the textbook ]
41 Constructing a Master-Slave Flip-Flop From one Latch and one Gated SR Latch (This version uses one less NOT gate) Master Slave
42 Constructing a Master-Slave Flip-Flop From one Latch and one Gated SR Latch (This version uses one less NOT gate) Master Slave
43 Edge-Triggered Flip-Flops
44 Master-Slave Flip-Flop Master Slave m s Clock Clk Clk (a) Circuit [ Figure 5.9a from the textbook ]
45 Negative-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk Positive-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk
46 Negative-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk Positive-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk
47 Negative-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk Positive-Edge-Triggered Master-Slave Flip-Flop Master Slave m s Clock Clk Clk
48 T Flip-Flop
49 T Flip-Flop [ Figure 5.15a from the textbook ]
50 T Flip-Flop Positive-edge-triggered Flip-Flop [ Figure 5.15a from the textbook ]
51 T Flip-Flop What is this? [ Figure 5.15a from the textbook ]
52 What is this? T
53 What is this? T + =?
54 T Flip-Flop T 0 1 Clock
55 T Flip-Flop T 0 1 Clock Note that the two inputs to the multiplexer are inverses of each other.
56 Another Way to raw This T 0 1 Clock
57 Another Way to raw This T 0 1 Clock What is this?
58 What is this? T
59 What is this? T = T + T
60 It is an XOR T = + T
61 It is an XOR T = + T
62 What is this? + =?
63 T Flip-Flop T Clock
64 T Flip-Flop (circuit, truth table and graphical symbol) [ Figure 5.15a-c from the textbook ]
65 T Flip-Flop (How it Works) If T=0 then it stays in its current state If T=1 then it reverses its current state In other words the circuit toggles its state when T=1. This is why it is called T flip-flop.
66 JK Flip-Flop
67 JK Flip-Flop = J + K [ Figure 5.16a from the textbook ]
68 JK Flip-Flop J K Clock (a) Circuit J K ( t + 1) t ( ) 0 J t ( ) K (b) Truth table (c) Graphical symbol [ Figure 5.16 from the textbook ]
69 JK Flip-Flop (How it Works) A versatile circuit that can be used both as a SR flip-flop and as a T flip flop If J=0 and S =0 it stays in the same state Just like SR It can be set and reset J=S and K=R If J=K=1 then it behaves as a T flip-flop
70 Complete Wiring iagrams
71 Positive-Edge-Triggered Flip-Flop
72 Negative-Edge-Triggered Flip-Flop
73 The Complete Wiring iagram for a Positive-Edge-Triggered Flip-Flop Clock
74 The Complete Wiring iagram for a Negative-Edge-Triggered Flip-Flop Clock
75 The Complete Wiring iagram for a Negative-Edge-Triggered Flip-Flop Clock
76 Positive-Edge-Triggered T Flip-Flop T Clock
77 Negative-Edge-Triggered T Flip-Flop T Clock
78 The Complete Wiring iagram for a Positive-Edge-Triggered Flip-Flop T Clock
79 The Complete Wiring iagram for a Negative-Edge-Triggered Flip-Flop T Clock
80 Positive-Edge-Triggered JK Flip-Flop Clock J K
81 Negative-Edge-Triggered JK Flip-Flop Clock J K
82 The Complete Wiring iagram for a Positive-Edge-Triggered JK Flip-Flop J K Clock
83 The Complete Wiring iagram for a Negative-Edge-Triggered JK Flip-Flop J K Clock
84 Registers
85 Register (efinition) An n-bit structure consisting of flip-flops.
86 Parallel-Access Register
87 1-Bit Parallel-Access Register Load In 0 1 Out Clock
88 1-Bit Parallel-Access Register Load In 0 1 Out Clock The 2-to-1 multiplexer is used to select whether to load a new value into the flip-flop or to retain the old value. The output of this circuit is the output of the flip-flop.
89 1-Bit Parallel-Access Register Load 0 In 0 1 Out Clock If Load = 0, then retain the old value.
90 1-Bit Parallel-Access Register Load 1 In 0 1 Out Clock If Load = 1, then load the new value from In.
91 1-Bit Parallel-Access Register Load In 0 1 Out Clock If Load = 0, then retain the old value. If Load = 1, then load the new value from In.
92 2-Bit Parallel-Access Register Out_1 Out_0 Load Clock In_1 In_0
93 2-Bit Parallel-Access Register Parallel Output Out_1 Out_0 Load Clock In_1 In_0 Parallel Input
94 3-Bit Parallel-Access Register Out_2 Out_1 Out_0 Load Clock In_2 In_1 In_0 Notice that all flip-flops are on the same clock cycle.
95 3-Bit Parallel-Access Register Parallel Output Out_2 Out_1 Out_0 Load Clock In_2 In_1 In_0 Parallel Input
96 4-Bit Parallel-Access Register Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0
97 4-Bit Parallel-Access Register Parallel Output Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0 Parallel Input
98 4-Bit Parallel-Access Register Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0
99 4-Bit Parallel-Access Register Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0
100 4-Bit Parallel-Access Register Out_3 Out_2 Out_1 Out_0 Load Clock In_3 In_2 In_1 In_0
101 Shift Register
102 A simple shift register In Out Clock [ Figure 5.17a from the textbook ]
103 A simple shift register In Out Clock Positive-edge-triggered Flip-Flop
104 A simple shift register In Out Clock Master Slave m s Clock Clk Clk
105 A simple shift register In Out Clock Flip-Flop Master Slave m s Clock Clk Clk Gated -Latch Gated -Latch
106 A simple shift register In Out Clock
107 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
108 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
109 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
110 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
111 A simple shift register In Out Clock In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
112 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk
113 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Clock
114 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Clock
115 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Clock
116 A simple shift register In Clock Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Master Clk Slave Clk Clock
117 A simple shift register In Out Clock (a) Circuit t 0 In = Out t t t t t t t (b) A sample sequence [ Figure 5.17 from the textbook ]
118 Parallel-Access Shift Register
119 Parallel-access shift register [ Figure 5.18 from the textbook ]
120 Parallel-access shift register 0 When Load=0, this behaves like a shift register. [ Figure 5.18 from the textbook ]
121 Parallel-access shift register 1 When Load=1, this behaves like a parallel-access register. [ Figure 5.18 from the textbook ]
122 Shift Register With Parallel Load and Enable
123 A shift register with parallel load and enable control inputs [ Figure 5.59 from the textbook ]
124 A shift register with parallel load and enable control inputs The directions of the input and output lines are switched relative to the previous slides. [ Figure 5.59 from the textbook ]
125 A shift register with parallel load and enable control inputs Parallel Input Parallel Output [ Figure 5.59 from the textbook ]
126 A shift register with parallel load and enable control inputs 0 0 [ Figure 5.59 from the textbook ]
127 A shift register with parallel load and enable control inputs 0 1 [ Figure 5.59 from the textbook ]
128 A shift register with parallel load and enable control inputs 1 0 [ Figure 5.59 from the textbook ]
129 A shift register with parallel load and enable control inputs 1 1 [ Figure 5.59 from the textbook ]
130 Parallel-access shift left / right register
131 Parallel-access shift left/right register Complete the following circuit diagram to implement a 4-bit register that has both parallel load and shift left/right functionality. The register has two control inputs (C1 and C0), four parallel input lines (I3, I2, I1, and I0), and four output lines (3, 2, 1, and 0). epending on the values of C1 and C0, the register performs one of the following four operations:
132 Parallel-access shift left/right register
133 Parallel-access shift left/right register Clock
134 Parallel-access shift left/right register Clock
135 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock
136 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock In_0
137 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock In_3 In_0
138 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock In_3 In_2 In_1 In_0
139 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_ Clock In_3 In_2 In_1 In_0
140 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_0 C 0 C Clock In_3 In_2 In_1 In_0
141 Parallel-access shift left/right register Out_3 Out_2 Out_1 Out_0 C 0 C Clock In_3 In_2 In_1 In_0
142 Multiplexer Tricks (select one of two 2-bit numbers)
143 Select Either A=A 1 A 0 or B=B 1 B 0 s A 0 B F 0 A 1 B F 1
144 Select Either A=A 1 A 0 or B=B 1 B 0 s 0 A 0 B F 0 = A 0 A 1 B F 1 = A 1
145 Select Either A=A 1 A 0 or B=B 1 B 0 s 1 A 0 B F 0 = B 0 A 1 B F 1 = B 1
146 Multiplexer Tricks (select one of four 2-bit numbers)
147 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = 1 0 s s 1 0 A 0 B 0 C F A 1 B 1 C F
148 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = s s 1 0 A 0 B 0 C F = A 0 A 1 B 1 C F = A 1
149 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = s s 1 0 A 0 B 0 C F = B 0 A 1 B 1 C F = B 1
150 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = s s 1 0 A 0 B 0 C F = C 0 A 1 B 1 C F = C 1
151 Select A=A 1 A 0 or B=B 1 B 0 or C=C 1 C 0 or = s s 1 0 A 0 B 0 C F = 0 A 1 B 1 C F = 1
152 Register File
153 Complete the following circuit diagram to implement a register file with four 2-bit registers, one write port, one read port, and one write enable line.
154
155 Register 0 Register 1 Register 2 Register 3
156 Register A Register B Register C Register
157 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register
158 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register
159 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register Write_address_0 Write_address_1 Write_enable
160 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register Write_address_0 Write_address_1 Write_enable
161 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register Write_address_0 Write_address_1 Write_enable Out 1 Out 0 Read_address_1 Read_address_0
162 In 1 In 0 A 1 A 0 Register A B 1 B 0 Register B C 1 C 0 Register C 1 0 Register Clock Write_address_0 Write_address_1 Write_enable Out 1 Out 0 Read_address_1 Read_address_0
163 In 1 In 0 A 1 A 0 B 1 B 0 C 1 C Clock Write_address_0 Write_address_1 Write_enable Out 1 Out 0 Read_address_1 Read_address_0
164 uestions?
165 THE EN
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