University of Victoria Electrical and Computer Engineering CENG 241 Digital Design I Laboratory Manual

Transcription

1 University of Victoria Electrical and Computer Engineering CENG 241 Digital Design I Laboratory Manual Copyright c University of Victoria, 2011 Original by Warren Little Revised by Farshad Khunjush and Amirali Baniasadi, 2006 Revised by Lynn Palmer, 2009 Revised by Fayez Gebali and Ahmed Morgan, 2011

2 University of Victoria Department of Electrical and Computer Engineering CENG 241 Digital Design I Lab Manual INDEX Introduction to the Labs 3 Lab 1: Digital Instrumentation, Basic Digital Components and Circuits 6 Lab 2: Using Xilinx ISE Tutorial 13 Lab 3: Combinational Circuits: 2-bit Multiplier 42 Lab 4: 4-bit Binary Adder/Subtractor 44 Lab 5: Sequential Circuits: Flip-Flops and Counters 64 Lab 6: Finite State Machines: Mealy and Moore Circuits 70 Lab 7: RAM System 75 2

3 INTRODUCTION TO THE LABS Introduction In this lab you will gain hands-on experience in the design, implementation and testing of digital circuits. The seven labs that you will perform support the theory covered in your textbook, the course notes and the lectures. The labs progress from rather simple labs that deal with digital instruments and components to the seventh lab that involves a rather complex digital system based upon a RAM memory chip. The mark for lab 7 is weighted twice that of the other labs. Some labs do not give you step-by-step instructions on how to do the lab. They require you to think carefully about what and how you are going to do things. For most of the labs you must do some preparation before you actually come to the lab. Some labs can actually be wired and pre-tested before you come to the lab. You will do the labs with prototype boards and components that are signed out to you by the ECE Department, as well as the Xilinx ISE software. The kits must be returned at the end of the course. Lab Requirements Each lab has prelab questions that should be answered before the session and handed in to your lab TA at the beginning of each session. Much of the lab work can be done outside of the scheduled lab time. Each lab is to be demonstrated to the lab TA to confirm its operation. The TA will ask questions regarding the lab and sign that the lab has been demonstrated. The write-up for lab #n must be submitted at the start of lab session #n+1 except for lab #7 which must be submitted on the last day of lectures. 3

4 The lab write-up should contain neat schematic diagrams, comments, explanations and answers to lab questions posed in the manual. See the 241 lab web page for additional guidance on the lab write-up. Additional Details Additional lab and lecture information is available through the ECE web page. The web site, has data sheets for many electronic components. The CENG 241 web site has links to all data sheets used in the labs. Data books and data sheets are also provided in the labs. The Lab is equipped with nine stations. Each station includes a PC workstation computer with Xilinx ISE software, an ethernet link to the Unix system, a power supply, an oscilloscope, two multimeters and a function generator. The Lab also contains a printer and a logic analyzer. 4

5 Components in Logic Kit Qty Part 2 74LS00 Quad 2 input NAND 2 74LSLS02 Quad 2 input NOR 2 74LS04 Hex Inverter 2 74C04 CMOS Hex Inverter (or CMOS 4069) 2 74LS05 Hex Open Coll. Inverter 1 74LS08 Quad 2 input AND 2 74LS10 Triple 3 input NAND 2 74LS20 Dual 4 input NAND 1 74LS32 Quad 2 input OR 4 74LSLS74 Dual D Flip-Flop 1 74LS86 quad 2 input XOR 1 74LS163 synchronous binary counter 1 74LS194 Shift Register 1 74LS244 octal tri-state buffer 1 74LS374 octal D FFs with tri-state outputs 1 74LS377 octal D FFs with load enable timer (32K x 8 RAM) 1 78C05 5V Regulator 8 Red LEDs 2 Yellow LEDs 8 Green LEDs ohm 20 1K ohm 2 5.lK ohm 4 l0k ohm 4 l00k ohm 4 1M ohm 2.01 µf 2.1 µf 4 pushbutton switches 1 toggle switch 4 DIP toggle switch 5

6 CENG 241: Lab 1 Digital Instrumentation, Basic Digital Components and Circuits 1. Objective This lab is intended to familiarize you with the following basic digital components and circuits. 1. Regulator 2. Power supply, multimeter, and prototype board 3. Oscilloscope 4. Pulse generator 5. Logic probe 6. LED Displays 7. Single-Pole/Single-Throw (SPDT) Switches 8. Push button Debouncer Your lab write-up should include a record of all the measurements you took and sketches of relevant waveforms. The write-up should also contain comments and explanations of things you observed and questions you were asked. You are expected to refer to the appropriate equipment manual available in the lab to help you with portions of the lab. 2. Prelab Questions 1. Read the datasheets for the voltage regulator to identify the input and output operating range and pin layout 2. Draw the SR-Latches based on NAND and NOR gates and identify the inputs and outputs for each latch. You can consult Section 5.3 in the textbook or any other resource. 6

7 3. Regulator Every electronic circuit is designed to work using some voltage supply which is usually constant. Voltage regulators are electronic devices which provide constant voltage regardless of changes in current load and input voltage. This assumes that current and voltage changes are within definite range. Figure 1- Regulator pin configuration 4. Power supply, multimeter and prototype board Power supplies provide the dc voltages required to power the electronics. Connect the lab power supply to your prototype board. Mount the voltage regulator chip and a 1k ohms resistor on your board. Connect the voltage regulator and use it to provide power to the resistor. You will need to use data sheets for the voltage regulator in order to determine the correct pin connections. Provide a good ground reference on your board so that all voltage measurements can be made relative to the board ground. Vary the supply voltage from 0 to 12 volts and measure the regulator input current and output voltage and current with the multimeter. Tabulate and graph your measurements. Comment on the power consumed by the regulator and the temperature of the regulator. 7

8 For what input voltages does the regulator actually regulate the output voltage? Try shorting the output of the regulator to ground. If you don't limit the current supplied by the power supply you will likely burn out your regulator. Make some measurements so you can describe what happens. 5. Oscilloscope Observe the calibration output signal, one channel at a time, on the two channels of the oscilloscope. Tune the probes and observe underdamped, overdamped and critically tuned probes. Measure the period of the calibration signal and observe the rise and fall portion of the signal using the X10 magnifier and the delayed sweep feature. 6. Pulse Generator Set up and observe on the oscilloscope a 1 KHz and then a 50 MHZ pulse train. Set up and observe a 1 MHz pulse train with a 25% duty cycle, fast and slow rise and fall times. 7. Logic Probe Set the logic probe in TTL mode and observe a high and low TTL logic level. Generate a number of TTL pulse trains with the pulse generator and observe the response on the logic probe. 8. LED Displays Light-emitting diodes (LEDs) are electronic devices that emit light whenever current flows across them. As figure 2 shows, an LED has two pins: anode and cathode. When the voltage of the anode exceeds from voltage of cathode by a certain threshold, the LED illuminates. LED is a unidirectional device, therefore it is important to distinguish anode and cathode. The cathode is usually the shorter lead or the lead close to the flat side of the LED s plastic housing. 8

9 Anode Cathode Figure 2. LED Connect 1 LED through 1K pull-up resistor to 1 open-collector output of an inverter of a 74LS05 chip. The inverter inputs are to be used as probe inputs to test circuits you build in this lab and in subsequent labs. Wire this circuit compactly and locate it so that it won't interfere with other circuits you build in the future. Note the conditions under which a LED is lit. Note also that a 7404 inverter cannot be used in place of a 7405 inverter. Explain why? (Hint: compare their data sheets) 9. Single-Pole/Double-Throw (SPDT) Switches Figure 3 shows an SPDT switch. As the figure shows, the SPDT switch has three point connections to the outside. Internal mechanics make it possible to connect selectively one of the two connections to the third connection. When the switch is in the up position, the output node value is logic 1 (figure 3.a). When it is in the low position the output logic value is 0 (figure 3.b). The resistor should be chosen to limit the current between power supply and ground. If the resistor is too small, the current drawn from power supply will cause high power dissipation. On the other hand, if the resistor is too big the voltage drop across the resistor may reduce the circuit input voltage to a level no longer recognizable as logic 1. 9

10 a. Open SPDT switch b. Closed SPDT switch Figure 3. SPDT Switch 10. Single-Pole/Double-Throw (SPDT) Switches: A variation on the single-pole/double throw switch is the momentary contact push-button. This is shown in figure 4. A distinguished input pole is connected through to the output when the push-button is at rest. When the push-button is pressed, the switch makes a connection between the second input pole and the output. When you release the button, it immediately returns to its rest position. Figure 4. Single-pole/double-throw push-button 10

11 11. Push Button Debouncer The switches you have in your kit, and indeed all mechanical switches, do not switch a voltage or current cleanly from one level to another. A switch debounce circuit as shown in figure 5 is widely used to produce a clean transition when a switch is activated. Wire the switch debounce circuit compactly in a corner of your board so that it can be used as a source of clean pulses for future experiments. Note that you must use both normally open contacts and normally closed contacts from the push button switches in your kit to realize the SPDT switch that the circuit requires. Use an ohm meter to determine suitable contacts to use on the push button switch you choose. In your write-up, give an equivalent NOR based debounce circuit. Display concurrently, the undebounced and debounced signals on an oscilloscope. 5 volts 1k ohms 7400 Figure 5. Push button debouncer 12. Lab Report Results to be included in the report: 1) The regulator voltage and current readings in section 4. 11

12 2) The range of input voltages at which the regulator output voltage is constant. 3) The waveforms of underdamped, overdamped and critically damped signals in section 5. 4) The rise time and fall time of the critically damped signal in section 5. 5) The undebounced and debounced signals in section 11. Things to be discussed in the report: 1) The outcomes when the regulator is short circuited in section 4. 2) The difference between ordinary inverter and open-collector inverter in section 8. 3) NOR-based debouncer in section

13 CENG 241: Lab2 Using Xilinx ISE Tutorial 1. Objective The second lab is arranged such that students learn how to use the Xilinx ISE software package. Students will learn to use both schematic capture and Verilog language to enter design information. In this lab, we will learn how to use the ISE Software series to enter (using schematic capture), simulate, and compile your design. 2. Prelab Questions Read Lab 2 and answer the following questions: 1. What is a net according to the definition in Lab 2? 2. What does the horizontal axis in Fig. 19 on page 30 represent? 3. What is the function performed by the Verilog module in Fig. 29 on page 39? 3. System Startup The PC will boot Windows XP, and display a logon message. At this prompt, you login using your Unix Engineering username/password. When you login, you will be able to access your Unix home directory (through drive M:) and lab s printer. 4. Creating a Design 1) Double click on the Xilinx ISE icon in the Xilinx directory on the desktop. 13

14 The Project Manager should appear. This will present you with the following windows: Figure 1. Project Manager Window 14

15 2) Click on File -> New Project. You will see the following window Figure 2. New Project Window 3) In Project: Name: enter the name of your project, i.e., lab2. 15

16 4) In Top-Level Source Type select Schematic and click on Next> Figure 3. Device Properties Window 5) Under Device Properties, choose Family: Spartan2, Device: XC2S200, Package: PQ208, and Speed: 6 to specify the Xilinx FPGA board and its speed rating. The other options need to be at the settings noted above. Click Next> 16

17 Figure 4. Create New Source Window 6) Click New Source. Figure 5. Source Type Window 17

18 7) Select source type as Schematic, enter lab2 as a file name, make sure Add to project is selected. Figure 6. Source Summary Window 8) Click on Finish. 9) Select Yes to add the directory. Figure 7. Create Project Directory Window 18

19 Figure 8. Completing New Source Window 10) Click Next>, then Next> again, then Finish 19

20 Figure 9. Project Manager 11) Click on the lab2.sch tab. The Schematic Editor will appear with lab2.sch indicated at the lower left. 20

21 Figure 10. Schematic Editor 12) If you would like, you can change the page setup in the edit options. Try to change the sheet size to 17 x Selecting and Placing Components This is the first step in a typical schematic capture process. 1) To begin entering the LAB2 schematic, click on logic in the Categories pane. Scroll down and select and2 from the Symbols pane. The Categories and Symbols panes contain all of the Xilinx components available for the part we are using. If at any point, you make an error, you can select a component, wire or region using Select (Arrow) (Upper left) in the Schematic Editor window, click or drag and click to select, and press Delete. When you are finished placing items, hit the ESC key to release the item attached to your cursor. You are now in Select mode. 21

22 Figure 11. Schematic symbols 2) Next, move the cursor to the Schematic Editor window. A 2-input AND gate will appear-attached to the cursor. 3) Position the cursor and click to place the AND, as shown in the above figure. 4) Click on the and2 again to place another gate in the schematic. 5) Repeat the above steps to place three 2-input and2 gates in total. 6) Repeat again to place a single 2-input or2 gates, and 2 inv gates. 7) These are the basic internal logic components for our design. 8) Next, we need to place the IO components. From the categories pane, click on IO. 9) An ibuf is required on each of the inputs. The ibuf receives and amplifies the input signal. Select and place an ibuf on the left of your schematic. ibuf is the same as any other input in logic circuits. 10) The IO Marker connects to an external pin on the FPGA. FPGA is a chip containing an array of cells that can be programmed as many times as you would 22

23 like, the IO Marker is the pin on the FPGA board to communicate with the external world. Click on the IO Marker icon and place one instance of it on the left of one of the ibuf items. Your cursor will suddenly change when you are over the ibuf s connection point. Click the mouse to place the marker here. Note that due to the net labels, I/O components need to be well spaced. You can select your IO marker and drag it away from your ibuf to leave more space for your net labels. Figure 12. Add IO Markers 11) Repeat steps 9 and 10 for the second ibuf. Note that space is required between the IO Marker and the ibuf for the name of the input. 12) An obuf is required on each of the outputs. The obuf amplifies its input signal to produce strong current drive for charging and discharging large 23

24 capacitances or other drive needs on the board. Select and place two obufs on the right of your schematic. 13) Repeat step 11 for 2 IO Markers, except that the markers will be placed on the right hand side of the obufs. At this stage, you should have the following components: 6. Adding Wires to Form Nets Figure 13. Components in Schematic Editor A net is a set of wires, all of which are connected to each other. This step can be performed for any particular net as soon as the components to be connected by the net are present. 24

25 1) Select Wire Drawing Mode icon (see figure 14 arrow) or select Add -> Wire from the menu items. Figure 14. The circuit after adding wires 2) Click on a desired wire origin. Drag, with a single click to force corners and to terminate the wire at a desired destination. Note that Escape (Esc) cancels a partially drawn wire. To delete a fully drawn wire, select Select (Arrow) from the icons on the left, highlight the wire and press Delete. 3) Repeat step 2 for all of the wires in LAB2. Note that you can move symbols with wires attached to re-arrange your schematic if necessary. 7. Labelling Nets To perform simulation and produce an implementation, it is necessary to name the I/Os. These names are placed on the net attached to the IO Markers. 1) Double-click the net (wire) between the topmost IO Marker symbol and topmost IBUF symbol on the left of your schematic. 2) Enter X in the name box that appears and click OK. 25

26 3) Repeat steps 1 through 3 for Y, S, and C. 4) Click File->Save. 8. Check Schematic The simulation and implementation tools need a netlist description of the circuit. The purpose of netlist generation is converting the schematic to a representation that is suitable for simulation and actual design of the circuit on a FPGA board. The following steps generate that description. Also, you will save and print the schematic. 1) Select Tools -> Check Schematic Figure 15. Check Schematic window 2) You may see an indication of some warnings or errors that are viewable in the Project Manager window. Click on the Errors Tab at the bottom of your screen to 26

27 see them. If you have warnings or errors, try to fix them and repeat Check Schematic. 3) Select File -> Print. Make sure 1 Page per Sheet is selected and click OK. 4) Select File -> Save. It is interesting to leave the Schematic Editor open to see that logic values are back-annotated to the named nets during simulation. 9. Create A Test Bench File 1) Next, we will perform a functional simulation to see if the design is correct. To do this, we first need to create a Test Bench Waveform. Click on Project -> New Source Figure 16. Create Test Bench Waveform 2) Call the file name lab2test. Note that the file name of the testbench must be different from the project name. Make sure Add to project is ticked. Click Next. 27

28 Figure 17. Associate Source 3) Select lab2, click Next, then Next, then Finish. 28

29 Figure 18. Timing and Clock Setup 4) Our circuit does not use a clock signal. Select Combinatorial. The rest of the defaults are OK in this case. 5) Click Finish. 29

30 10. Setting Up Test Conditions 1) Notice that the signals we need are already appearing in the testbench screen. We only need to add changes to the X and Y inputs. Figure 19. Signal Selection window 2) For signal X, click on the second blue square on the line. Notice that the signal goes high at this point. Clicking another blue square makes the signal go low at that point. You will need at least 4 pulses of X to test all conditions for this circuit. 30

31 Figure 20. Adding inputs to simulate the circuit 3) For signal Y, click on the blue square as in the diagram above. There will be at least 2 pulses of Y to test all conditions of this circuit. 4) By clicking and dragging on the signal names, order the signals as follows: X, Y, S, and C. 5) Save the testbench. 11. Performing Simulation and Verifying Results 1) On the Sources tab, click on sources for: behavioral simulation. Select the testbench file lab2test.tbw. 2) On the Processes tab, double-click on simulate behavioral model (or rightclick and select run. 31

32 Figure 21. Running the Simulator 3) The simulation window will come up. 32

33 Figure 22. The Result of Simulation 4) Click on Simulation tab and check the result. The blue bar can be moved to check the outputs anywhere along the simulation screen. 12. Archive To backup your design, you can use the archive facility in the ISE. 1) Click File -> Save Project As. 2) In Path, select a folder on your M: drive, and Click on the Next. 33

34 Figure 23. ARCHIVE window 13. Restore To restore the project, click on File -> Open Project, and select the appropriate.ise file from your M: drive. 34

35 14. Creating a project by using an HDL In this section, you will learn how to make a project by using an HDL like Verilog. 1) Create a new project by clicking on FILE->New Project. 2) In New project window, write HA as name of project. Click on HDL for Top- Level Source Type. Click Next. Figure 24. Create a New HDL Project 35

36 Figure 25. HDL Project Properties 3) Select Spartan2, XC2S200, PQ208, and -6 as you did with the previous project. 4) Click on next. 36

37 Figure 26. Create Verilog Source Module 5) Choose Verilog Module. Write HA as name of the file. Click Next. 6) In Design Wizard Ports, write X, Y as inputs and S, C as outputs. 7) Click on Next. Figure 27. Define Ports 37

38 15. Modify Verilog Source File In this stage, you will see the following: Figure 28. Verilog Source File 1) Write following two lines in between output C: and endmodule. assign S = (X&(!Y)) ((!X)&Y); assign C = X & Y; //S = X XOR Y //C = X AND Y 2) Save the file. 3) Click on Synthesize ->Check Syntax under the Processes tab. If you wrote the Verilog code correctly you will see Check Successful report. 38

39 16. Synthesis and Post Synthesis Simulation Double click on Generate Post Synthesis Simulation Model. A green check mark will indicate that this has been done correctly. Figure 29. Verilog Source Synthesized. 1) On the Sources tab, click on Behavioral Simulation, and create a testbench file as you did in the first project of this lab. 2) Run the simulation, as you did in the first part (Schematic capture). In this phase, you simulate only the functionality of the circuit. 39

40 You should take into account that the timing details of the circuit will not be considered during simulation. 17. Implementation and post implementation simulation Click on Sources for Synthesis/Implementation, then click on the Processes tab on the left. 1) Double-Click on Implement Design. In this phase, the HA circuit that you have written in Verilog will be mapped to the FPGA. A green check mark will indicate success. 2) When Implementation finishes, click on the Post Route Simulation tab under Sources. It is not necessary to re-create a testbench file. In this phase you will simulate the equivalent circuit of Verilog code which has been mapped to the FPGA. Double-click on Simulate Post Place and Route Model in the Processes Tab. This simulation includes all timing details of the circuit. It is very important to mention that outputs of the circuit do not change immediately after input changes due to propagation delay. Delay of internal components of FPGA is the source of this delay. 18. Backup Archive your design for use in future. 19. Lab Report Results to be included in the report The following is to be included for the half adder design: 1) Snapshot for the complete schematic like that in Figure 15. 2) Snapshot for the functional simulation like that in Figure

41 3) Snapshot for the complete Verilog code entered like that in Figure 29. 4) Snapshot for the post place-and-route timing simulation. Things to be discussed in the report: 1) What are the digital design entry methods? Form your opinion, which one is the most efficient? Why? 2) What is the difference between functional and timing simulations? Is functional simulation sufficient enough to ensure the correctness of the design? 41

42 CENG 241: Lab 3 Combinational Circuits: 2-bit Multiplier 1. Objective To design, simulate, build and test a combinational circuit. 2. Prelab questions The product of two n-bit binary numbers A and B is C which has 2n bits. C = A! B where in this lab A and B are 2-bits each: A = [A1 A0] B = [B1 B0] C = [C3 C2 C1 C0] Read Section 4.7 of the Textbook on Binary Multiplier and answer the following questions: 1. Write down the defining Boolean equations for the 2-bit multiplier outputs C0, C1, C2 and C3. 2. Write down the truth tables for the four outputs. 3. Write down the four K-maps for the four outputs bit Multiplier The combinational circuit you will work with in this lab is a 2-bit Multiplier. The circuit is to have inputs A1, A0 and B1, B0 and outputs C3, C2, C1, C0 where A1, A0 are the 2 bits of one of the numbers to be multiplied, and B1, B0 are the 2 bits of the other number to be multiplied and C3, C2, C1, C0 are the 4 bits of the result. For example, if 01 is multiplied to 10 the product is Your task is to design, simulate and test circuits corresponding to Boolean equations for C3, C2, C1 and C0. Each equation is a different function of the 4 input variables A1, A0, B1, and B0. Do your design by constructing K-maps for C3, C2, C1 and C0 and then getting minimum sum -of-product expressions for the 4 outputs. 42

43 To implement your equations, assume that all inputs and outputs are asserted high and use only NAND gates and inverters in your circuits. Share product terms to save gates if possible. Simulate your circuit using Xilinx ISE Simulator for all possible input combinations. Build your circuit and compare its operation with the simulated circuit. 4. Lab Report Results to be included in the report 1) Snapshot for the complete schematic. 2) Snapshot for the simulation. Things to be included in the report: 1) A detailed description of your design solution including truth table, K- maps, simplified boolean functions...etc. 2) Complete circuit diagram for your design of the 2-bit multiplier if correct, you can include your prelab for point 1 and 2. 3) A general discussion for the design and the lab. 43

44 1. Objective CENG 241: Lab4 4-bit binary Adder/Subtractor In this lab, you will design, implement, and verify a combinational logic circuit. After the end of this lab, you should be able to: 1. Design a hierarchical combinational circuit using Xilinx ISE schematic editor. 2. Use simulation to verify circuit function. 3. Design a hierarchical combinational circuit using Verilog. 2. Prelab Questions 1. What is meant by hierarchical design in the sense used in this lab? 2. Use the Verilog statements in step 4 of Section 12 to create Verilog statements for the 4-bit adder/subtractor. 3. Binary Adder/Subtractor The combinational circuit in this lab is a 4-bit binary adder/subtractor. The circuit inputs are A3, A2, A1, A0, B3, B2, B1, B0, and the Control bit to control the mode of operation. The outputs are S3, S2, S1, S0, and C. The subtraction of unsigned binary numbers is done by means of complements. Subtraction A B can be done by taking the 2 s complement of B and adding it to A. Also, the 2 s complement can be obtained by taking 1 s complement and adding one to the least significant pair of bits. The 1 s complement can be implemented with inverters and a one can be added to the sum through the input carry. + 3 ( 0011 ) 1 s complement s complement ( -3 )

45 A ( 7 ) ( 7 ) B ( 3 ) ( -3 ) C = (A - B) ( 4 ) The circuit for subtracting A B consists of an adder with inverters placed between each data input B and the corresponding input of the full adder. The input carry C 0 must be equal to 1 when performing subtraction. The operation performed becomes A, plus the 1 s complement of B, plus 1. This is equal to A plus 2 s complement of B. For unsigned numbers, this gives A B if A B or the 2 s complement of (B A) if A < B. In this lab, we combined the addition and subtraction into one circuit with one common binary adder. This is done by including an XOR gate with each full adder. A 4-bit adder-subtractor circuit is shown in Fig 1. The mode input CONTROL controls the operation. When CONTROL=0, the circuit is an adder, and when CONTROL = 1 the circuit is a subtractor. 45

46 Figure 1 Binary Adder/subtractor 4. Creating a Design 1) Double click on the Xilinx ISE Project Manager icon in the Xilinx Folder on the desktop. The Project Manager should appear. 2) Click on Create a New Project and OK in File -> New Project. 3) In New Project: Name: enter the name of your project, i.e., lab4. Figure 2. Project Manager 4) In Top-Level Source Type, select Schematic and click Next. Ensure the other options are as they were for lab 2. 5) Create a schematic and call it lab4. 5. Creating a New Module In this part, we create a new device (HA) that is going to be used in the next part of this lab. For creating a new device follow the next instructions. 46

47 1) Click on the Project -> New Source. The following windows will appear. Figure 3. New Source window 2) Create a new source of type Schematic, and call it HA (for Half Adder). Click on Next. 47

48 Figure 4. Half Adder Schematic 3) Create the schematic as shown above. Note: no ibufs or obufs are used in this module. This schematic will be used to create the HA symbol. 4) Save your HA schematic. Run Tools -> Check Schematic. 5) Under Tools, select Symbol Wizard. 48

49 Figure 5. Schematic Editor for the new Module 6) Select Using Schematic-> HA, click Next. 49

50 Figure 6. Pin Assignment for HA Symbol 7) Assign pins as above. Note the order of the pins, the Polarity and Side (Left for Inputs, Right for Outputs). Click Next. 8) Use the default options to create the symbol drawing. Click Next, then Finish. From now on, you have HA as a component available to you within the Schematic Symbols window, with the file path showing in Categories, and HA showing in the Symbols window. Whenever you select it, you will get the following element with 2 inputs and 2 outputs. 50

51 Figure 7. HA block diagram 9) Use the next circuit to test your HA Module. Figure 8. The test circuit for HA 51

52 6. Hierarchical Design 1) In this part we will create a FA from two HAs created in the previous section. 2) Use the same procedure as you used in creating HA. 3) Use A, B, and CIN as inputs, and S and COUT as outputs. 4) The final FA module should have the following circuit. 5) Simulate and test your full adder to make sure about the correctness of your design. Figure 9. Building FA from two HA s and an OR gate 52

53 7. Binary ADDER/SUBTRACTOR Design Finally, you will design your binary Adder/Subtractor by using the modules created in the previous sections. Follow Selecting and placing components from lab2 to place components and wires, but do not place I/O markers yet. Use the schematic editor to design the circuit as shown below. Figure 10. Binary Adder/Subtractor 53

54 8. Creating a Bus The only problem that you need to be aware of is combining the single lines into a bus to make simulation easier. To make a bus from single lines follow the following instructions. 1) Add a wire to the right of the obufs as shown below. 54

55 2) To make S bus, double-click on the wire. For the Name of the bus, enter S(3:0) to indicate that there will be 4 output lines, from S(3) to S(0). Click Apply then OK. Figure 11. Creating BUS from single lines 3) Place 4 Bus Taps along the edge of the Bus, label each tap from S(3) to S(0). You can use Ctrl+E to flip the Bus Tap or Ctrl+R to rotate the Tap as required. 55

56 Figure 12. S Bus with Bus Taps 4) Once all the Taps are in place, connect the wires to the OBUFS. Hint: it is easier to work on one bus at a time. After the Bus wires are connected, the wires need to be named so that the correct output is associated with the correct Bus line. Double-click on the connecting wire and name each one, starting with S(0) at the top. Click Apply. 56

57 Figure 13. Add Net Name and Make Visible (1) 5) While the Net Attribute screen is still open, click on Add under Visible, then Add, then OK then OK. Figure 14. Make Net Name Visible (2) 57

58 6) Complete the schematic with 2 input busses, A(3:0) and B(3:0), following the schematic example carefully. Do not forget to add IO markers for the busses, CONTROL, and C. Figure 15. Wiring for A(3:0) and B(3:0) 9. Assign Data to a Bus 1) Create a Testbench Waveform as in Lab 2. Choose Combinatorial, suggested time 7500 ns to ns. 2) Click on the Bus that you want to assign data, in the place you want it assigned. 3) You may either enter a value, or run the pattern wizard. You may also expand the bus signals and change each line individually. 58

59 Figure 16. Assigning Data to a BUS using Pattern Wizard 1) Simulate your design. The final simulation result for this lab should contain the following data, besides your own data: ADD 1,4 two positive numbers, no overflow ADD -3,2 one positive one negative, no overflow ADD -5, -1 two negative numbers, no overflow ADD 7,6 two positive numbers, overflow ADD -5,-4 two negative numbers, overflow SUB 4,2 two positive numbers SUB 4,-1 one positive one negative SUB -2,3 one negative one positive SUB -3,-4 two negative numbers SUB 4,-6 one positive, one negative, overflow SUB -5,4 one negative, one positive, overflow 59

60 NOTE THAT DUE TO LIMITATIONS OF THE SIMULATOR, IT IS EASIER TO FOLLOW IF YOU ENTER SIGNED NUMBERS AS TWO S COMPLEMENTS. IE: TO ENTER -3, CONVERT TO TWO S COMPLEMENT, WHICH WOULD BE Archive Archive your design for later usage. Figure 17. The Testbench Waveform 11. Using HDL for Designing Binary ADDER/SUBTRACTOR In this section, you will learn how to write and simulate your hierarchical designs in an HDL. 60

61 12. Designing FA from HAs Actually in lab 2, you designed a half-adder in Verilog and simulated it. In this section, you will connect two half-adders to make a full-adder. 1) Create a new project. Name the project as FA. 2) Under Add Existing Sources, select the HA verilog file that you created in Lab 2. Figure 18. Adding HDL codes to project in Project Manager 3) Make a new Verilog file by clicking on Project -> New Source. Name the file as FA. Write A, B, CIN as input and S, COUT as output. 61

62 4) Add following two lines to the file. HA U0(A, B, S0, C0) ; //Instantiates HA with A,B as input and S0,C0 as //output. We use U0 as instantiation name. HA U1(S0, CIN, S, C1) ; //Instantiates HA with S0,CIN as input and S,C0 as //output. We use U1 as instantiation name. assign COUT = C0 C1; 5) Save the file. Right-Click on the file FA.V, and select SET AS TOP MODULE. 6) Click on Synthesis->Check Syntax under Processes. 7) Double-Click on Synthesize. 8) After synthesis, simulate the code. 9) Do implementation and post implementation simulation the same as lab Designing a 4-bit binary Adder/Subtractor from FA s In this section, you will write a 4-bit binary Adder/Subtractor by using FA and HA. 1) Create a new project. Name the project add_sub. 2) Add FA.v and HA.v source files to the project. 3) Create add_sub.v file. Write 4-bit binary adder/subtractor by instantiating FA. 4) Save the file. Check syntax of Verilog file. 5) Synthesis the file. 7) Do post synthesis simulation. 8) Implement your project on real hardware in the IMPLEMENTATION part in Project Manager and simulate after implementation to observe the differences of timing (propagation delay) in either case. 62

63 14. Lab Report Results to be included in the report For the complete adder/subtractor design, the following is to be included: 1) Snapshot for the complete schematic. 2) Snapshot for the complete Verilog code entered. 3) Snapshot for the simulation functional or timing. Things to be discussed in the report: 1) A detailed discussion of how the 4-bit adder can be changed into 4-bit subtractor using XOR gates and only one control signal. 2) A general discussion for the design and the lab. 63

64 CENG 241: Lab 5 Sequential Circuits: Flip-Flops and Counters 1. Objective Sequential circuits are logic circuits with feedback used to realize memory of state. Flip-flops are elementary sequential circuits. Sequential circuits are the basis of registers, counters and controllers. In this lab you will experiment with an SR latch, D flip-flop, T flip-flop and a counter. 2. Prelab Questions 1. You are required to use the equations of the 555 timer in Section 3 to create a clock with a frequency of approximately 10 Hz using the capacitance and resistance values given to you in the lab kit. Notice, however, that you will find it much easier to manually clock your circuit to observe the transitions at your leisure. 2. Based on the discussion on Section 5.3 in the textbook, write the function table for the NAND-based SR-latch. 3. Based on the discussion on Section 5.4 in the textbook, write the characteristic equation for the D-FF. 4. Explain the function of each pin in the 74LS163 counter. 5. Study the datasheet for the 74LS163 counter to determine the correct input values for operation of the counter in Figure 5 on page 65. Specifically, you are required to indicate what are the values of the input pins CEP, CET, PE, P0 P3. 3. Clock Circuit The 555 timer is used to generate clock signals. Figure 6 shows a 555 timer circuit. By selecting appropriate values for resistors and capacitors, we can control frequency and duty cycle of the clock signal. The following formula shows the relation between resistor, capacitor and clock signal characteristics. Clock high time = (Ra + Rb) C 1 64

65 Clock low time = (Rb) C 1 Clock frequency = 1.44/(Ra + 2Rb)C 1 Duty cycle = (Ra + Rb) / (Ra + 2 Rb) Figure Timer circuit Build and test the 555 clock circuit. Select circuit components so that the clock frequency is a few hertz and the duty cycle is about 50%. Use a scope to observe and record the waveforms of the 555 pins. 65

66 4. RS Latch A NAND implementation of an SR latch is shown in figure 2. Build the circuit and test its operation by driving the inputs with logic levels generated by 2 undebounced pushbutton switches and a pair of pull-up resistors. Figure 2. SR Latch In theory, the flip-flop you have just built is unstable and oscillates when R and S are simultaneously changed from 00 to 11. Connect a scope to the output Q (H) and see if you can demonstrate the unstable oscillatory behaviour. If you have trouble observing oscillations (you will), try extending the effective delay time of the NAND gates by adding a pair of rather slow 74C04 inverters to the outputs of the NANDs. Make sure the input you use is debounced. Observe the frequency of oscillation and correlate the frequency with the delay times of the components in your circuit. Write state equations for the circuit under the assumption that each NAND gate has 1 unit of delay. Manually evaluate the change equations to show the response of an RS=00 to an RS=11 input change. The state equations could be implemented in a spreadsheet. 5. Edge triggered D flip-flop Build the negative edge-triggered D flip-flop shown below. Apply a variety of inputs to demonstrate that the flip-flop changes state only on negative clock edges. Record the responses to your inputs in a timing diagram. Explain clearly and in detail how the flip-flop works. 66

67 Figure 3. D flip-flop 6. T flip-flop Flip-flops are storage elements that their output value changes in the edge of clock input signal (rising edge or falling edge not both of them). A D flip-flop transfers its input to its output in the edge of clock. Output of a T flip-flop toggles in every edge of the clock. In this section, you will make a T flip-flop by using a D flip-flop. Figure 4 shows the circuit. Build the circuit and test it. Figure 4. T flip-flop 67

68 7. Counter In this section, you will learn how to use 74ls163 IC to make a counter. 74ls163 counter includes synchronous load inputs in order to initialize the counter at a desired state once the Load signal is asserted. The counter is incremented at the rising edge of the clock. Figure 5 shows a circuit that counts from 3 to 12. The counter value is increased one unit at each clock cycle as long as the output data is not equal to 12. The load signal is activated when the output data is equal to 12. Once the load signal is active, the values on the input signals (0011) are loaded into the counter, and the counter keeps counting in the next clock cycle. Read the datasheet of 74ls163, find out details of IC pin out, and complete the circuit in figure 5. Build the circuit on the board. Initially, activate the Clear signal at least for one clock cycle and then deassert it. Explain why the output of the circuit is not in the range of 3 to 12 in the first few clock cycles. 8. Lab Report Figure 5. Counter Results to be included in the report: 1) The waveforms at the output, pin 3, and the capacitor, pin 6, of the 555 timer, one graph for the two waveforms. 68

69 2) The sinusoidally oscillatory waveform if you change RS of the latch from 00 to 11. 3) The waveforms of the clock and the output of the D flip-flop, one graph for the two waveforms. 4) The waveforms of the clock and the output of the T flip-flop when T=1, one graph for the two waveforms. Things to be discussed in the report: 1) Why does the output of the RS latch oscillate when RS changes from 00 to 11. 2) General discussion of the operation of the RS latch, the edge triggered D flip-flop, the T flip-flop and the counter. 69

70 1. Objective CENG 241: Lab 6 Finite State Machines: Mealy and Moore Circuits In this lab you will design two sequential circuits capable of detecting the 1101 sequence. This sequence detector is an overlapping one that does not necessarily return to the start state after detecting the sequence. The first circuit is a Mealy state machines and the second one is the Moore implementation of the same circuit. You will design these Finite State Machines (FSMs) from flip-flops and input and output logics. After designing these circuits, you should understand the differences between these 2 general FSM design methodologies. 2. Prelab Questions 1. Draw the state diagram for the Moore state machine to detect the sequence Draw the state diagram for the Mealy state machine to detect the sequence Write down the transition tables for both machines. 4. Write down the K-maps for both machines to get the optimum Boolean expressions for each output. 3. Moore and Mealy State Machines There are two general methods to design a clocked sequential circuit: 3.1. Moore machine: In this method, the outputs of the circuit depend only on present state. Figure 1 shows the structure of a Moore machine. A combinational logic circuit generates next state base on the present state and inputs. The outputs are computed by a combinational logic which maps the present state to 70

71 the outputs. The state register outputs are updated at the edge of the clock signal. Therefore, outputs signals change with respect to the edge of the clock. State Register Inputs Combinational Logic for Next State Combinational Logic for Outputs Outputs Clock State Feedback Figure 1. Moore machine block diagram 3.2. Mealy machine: Figure 2 shows the block diagram of a mealy machine. In mealy machines, the output depends on both the present state and inputs. The outputs can change when inputs change independent of the clock signal. Inputs Combinational Logic for Next State Outputs State Register Clock State Feedback Figure 2. Mealy machine block diagram 4. A sequence detector: In this section, a sequence detector that detects the 11 sequence is designed with both Mealy and Moore state machines. Consider a finite state machine that asserts its single output whenever its input string has at least two 1's in sequence. The minimum Moore and Mealy state diagrams are shown in Figure 3. 71

72 0 0/0 0/ /0 0/0 1/ /1 1/1 1 a. Moore machine b. Mealy machine Figure 3. A sequence detector Figure 4 shows the table for the next state and the output of Moore machine. As it can be seen, the next state depends on both the present state and the input, but the output depends only on the present state. S 1 S 0 X S S S 1 S Z b. Output a. Next State Figure 4. Next State and output of Moore machine 72

73 Figure 5 depicts the table for the next state and output of Mealy machine. As expressed before, the output depends not only on the present state but also on the input. S 0 X S S 0 X a. Next State b. Output Z Figure 5. Next State and output of Mealy machine As it is shown in the above tables, Mealy machines generally have fewer states than Moore machines. Explain why? How about outputs problem? Sequence Detector 1) Design, build and test FSMs for detecting the 1101 sequence. Design your circuits as described in section 3. Draw the state diagram, Next state and output table for the Mealy and Moore circuits. Using Karnaugh map find the Flip-flops input and output logics. The circuit should work as described below: Inputs Outputs The 74LS74 D type flip-flops should be used to design the sequence detector. Use switches and pushbuttons to generate the clock pulses, and the circuit input. LEDs can be used to display the output. 73

74 Test and demonstrate your circuits. In your write-up, explain the differences between Mealy and Moore machines in terms of number of states, stability of outputs, etc. (Pick one of the machines and build it) 2) Use Xilinx Foundation software to design and simulate your Moore or Mealy circuits. 6. Lab Report Things to be included in the report: A detailed description of your design solution, both Mealy and Moore, including state diagrams, truth tables, K-maps, simplified boolean functions...etc. you may attach your prelab if correct Results to be included in the report: 1) Snapshot for the complete schematic. 2) Snapshot for the simulation functional or timing. Things to be discussed in the report: 1) Explain the differences between Mealy and Moore machines in terms of number of states, stability of outputs...etc. 2) A general discussion for the design and the lab 74

75 CENG 241 Lab 7 RAM System 1 Lab Outcomes By doing this lab, you should become familiar with the operation of RAM and how to implement the reading and writing operations. 2 Introduction In this lab you will construct and test a digital system that reads and writes data to a random access memory (RAM). The system is divided into the following major parts, also shown in Fig. 1: 1. The RAM memory block 2. RAM controller 3. 4-bit Counter to generate 4-bit addresses for RAM. 4. Tri-state buffer to feed input data source into the RAM 5. Four-bit register to store memory output Notice in Fig. 1 that the address inputs to the RAM are connected to LEDs so as to be able to visually see the values of the address bits. LEDs are also used to display the data stored in the 4-bit register. Switches are used to set the input data values to be stored in the RAM. The connection diagram of the RAM chip is shown in Fig. 2. The functions of the pins are explained in Table 1. Table 2 explains the effect of the RAM control signals on the operation of the RAM. Notice from the table that CS is the most important pin. When it is high, the RAM is in standby state irrespective of the values of WE and OE. In that case the data pins are disconnected from the I/O lines connected to the RAM. Next pin in importance is the WE. When it is low the RAM is in write mode irrespective of the value of OE. 3 System Operation 3.1 RAM Read Operation Figure 3 shows the timing diagram for the RAM read operation. Reading from the RAM device is accomplished by setting CS =0, OE =0and WE =1. Under these conditions, the contents of the memory location specified on the address pins will appear on the eight I/O pins. Notice that desired Address must be provided along with the control signals and the associated output data is obtained after a certain delay (access time). The minimum period after which a new data address could be supplied is called the read cycle time. 75

76 Figure 1: Memory system. Figure 2: Connection diagram for the RAM chip. 76

77 Name Direction Polarity Function A[0-14] In Address lines Table 1: Pins of the RAM pins CS In Active low Select RAM memory. I/O[0-7] In/Out Data in or data out of RAM OE In Active low Enable selected RAM data to be placed on the I/O lines V cc In Power (5V) V ss In Ground WE In Active low Place RAM in write mode when low and in read mode when high Table 2: Functional description of the RAM pins CS OE WE I/O Pins Mode Power H X X High-Z Deselected Standby L H H High-Z Output Disabled Active L L H Dout Read Active L X L Din Write Active Read Cycle Time Address Address Valid CS WE OE Data Out Data Valid Access Time Figure 3: Timing diagram for the RAM read operation. 77

78 3.2 RAM Write Operation Figure 4 shows the timing diagram for the RAM write operation. Data is prepared using the switches Read Cycle Time Address Address Valid CS WE Data In Data Valid Hold Time Figure 4: Timing diagram for the RAM write operation. connected to the tri-state buffer. Writing into the RAM device is accomplished by setting CS =0, OE =0 and WE =1. Under these conditions, the contents of the memory location specified on the address pins will appear on the eight I/O pins. Data on the I/O pins (I/O 0 through I/O 7 ) is written into the memory location specified on the address pins (A 0 through A 14 ). 4 The RAM Controller Specifications Table 3 identifies the I/O signals of the controller and their functionality. The controller actions depend on whether the R/W is 1 or 0. When R/W =1the system is in RAM read mode. When R/W =0the system is in RAM write mode. In the following discussion, when we a controller output is not mentioned, it is taken to be inactive. For example, if we indicated that Reset counter =0only, then the rest of the controller outputs assume the inactive value, e.g. OE =1, etc. The actions of the controller when the system is in the RAM read mode can be summarized as follows: 1. The controller starts in the reset state and produces the following outputs: Reset counter =0 2. When Go = 1 and R/W =1, the controller reads the from the RAM by setting CS = OE =0 and WE =1 3. In the next clock cycle, the controller loads input data in the 4-bit register by making Load data =0 for one clock cycle. 4. At the next clock cycle, the controller increments the counter Inc =1. 5. The controller then unconditionally goes to step 2. 78