Chip-Scale Energy and Power... and Heat. Electrical and Computer Engineering Department, Georgia Tech University

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1 Chip-Scale Energy and Power... and Heat Prof. Paul Hasler Electrical and Computer Engineering Department, Georgia Tech University The views and opinions presented by the invited speakers are their own and should not be interpreted as representing the official views of DARPA or DoD

2 Report Documentation Page Form Approved OMB No Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. 1. REPORT DATE MAR REPORT TYPE 3. DATES COVERED to TITLE AND SUBTITLE Maximizing Computational Capability with Minimal Power 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) 5d. PROJECT NUMBER 5e. TASK NUMBER 5f. WORK UNIT NUMBER 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) Georgia Institute of Technology,Electrical and Computer Engineering Department,Atlanta,GA, PERFORMING ORGANIZATION REPORT NUMBER 9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSOR/MONITOR S ACRONYM(S) 12. DISTRIBUTION/AVAILABILITY STATEMENT Approved for public release; distribution unlimited 11. SPONSOR/MONITOR S REPORT NUMBER(S) 13. SUPPLEMENTARY NOTES MTO (DARPA Microsystems Technology Office) Symposium, 2009 Mar , San Jose, CA. U.S. Government or Federal Rights License. 14. ABSTRACT 15. SUBJECT TERMS 16. SECURITY CLASSIFICATION OF: 17. LIMITATION OF ABSTRACT a. REPORT unclassified b. ABSTRACT unclassified c. THIS PAGE unclassified Same as Report (SAR) 18. NUMBER OF PAGES 22 19a. NAME OF RESPONSIBLE PERSON Standard Form 298 (Rev. 8-98) Prescribed by ANSI Std Z39-18

3 Maximizing Computational Capability with Minimal Power Paul Hasler Professor, Georgia Institute of Technology DARPA activity: ISP, CT2WS, SyNAPSE, Healics, TEAM

Power Efficient Computing Portable Devices

minimize battery size / weight Get as much

of inputs, 1000 s of channel populations, one

neuron (no learning / growth) ~ roughly 20pW /

efficient than Custom Digital (Mead 1990)

(DSP) Useful Analog must be Programmable /

is quite far away (100mW) analog VMM closer

4 Power Efficient Computing Portable Devices battery powered (or less) larger systems minimize battery size / weight Get as much computation as possible Cortical Neurons 1000 s of inputs, 1000 s of channel populations, one output Equivalent computation ~ 400MMAC / neuron (no learning / growth) ~ roughly 20pW / neuron Custom Analog ~ more efficient than Custom Digital (Mead 1990) Analog (VMM): 10MMAC/ W Digital: 4 MMAC / mw (DSP) Useful Analog must be Programmable / Configurable 400MMAC / neuron at 20pW digital is quite far away (100mW) analog VMM closer (100 W) analog HMM / dendrites get close ~ 200TMAC < 500 neurons ~ 40kW (comp) with 2000 DSPs

Modern System Design Fixed function Digital

Adders Design at Basic Algorithms (1837) Fixed

Frequency Decomposition Adaptive Filters

systems, we expect to build primitives at the

.. Programmable Digital (Mixed mode) Analog =

How to get enough analog engineers Hierarchy is a

5 Modern System Design Fixed function Digital Design at gate level Design at Multipliers and Adders Design at Basic Algorithms (1837) Fixed function Analog Vector-Matrix Multiplication Frequency Decomposition Adaptive Filters Classifiers (NN, GMM, HMM) When building analog systems, we expect to build primitives at the basic algorithm level... Programmable Digital (Mixed mode) Analog = programmable and configurable. How to get enough analog engineers Hierarchy is a key ingredient to the success of the digital circuit, and, until recently, one reason why large analog designs have been difficult

6 Levels of Energy Efficiency Subthreshold Transistor Operation Highest throughput / amount of power Programmable Circuits (FG transistors) Analog Signal Processing Configurable Signal Processing Eliminate mismatch Programmability ~ x1000 improvement in power efficiency Wide accessibility Moving analog approaches /conceptual framework to a system design approach, similar to digital s system transformation in the 1970 s / 80 s. Large need for tools to compile / program these systems. Link most useful at system /sig processing level Education / training / foundational theory is critical for designing. These techniques open further opportunities to utilize / explore biologically inspired techniques

MOS Transistor Derivation 1 A 100nA Drain current (A) 10nA 1nA 100pA =

2104fA Mismatch is significant: 10mV V T shift ~ 50% bias current

8 0.9 Gate voltage (V) 10 2 10 1 10 0 gm/i vs.

7 MOS Transistor Derivation 1 A 100nA Drain current (A) 10nA 1nA 100pA = I o = fA Mismatch is significant: 10mV V T shift ~ 50% bias current variation 10-1 Transconductance/Current (1/Vg)S 10pA Gate voltage (V) gm/i vs. Current Subthreshold U T As devices shrink, most of useful operating region is Subthreshold Channel Current(A) 2 K I

Programmable Analog Transistors Standard CMOS Data

1% between 100pA - 1 A ~ 10e - Write degradation (100 C): V

8 Programmable Analog Transistors Standard CMOS Data retention: < 5 V (0.5 m) (10 year, 300K) Apps: Filters, Data converters, Regulators, etc. Accuracy ~ 0.1% between 100pA - 1 A ~ 10e - Write degradation (100 C): V tun increase less than 25% V inj negligable change (100 C is >10 9 complete FG rewrite) Otherwise, need a DAC at every parameter and/or memory, etc.

Input Offset Voltage Drifts by 130 V over 170 C Input Offset Voltage Reduced to 25 V I tail M 5

9 Industrial Quality Programmable Analog ICs Floating-gate transistors V dd V tun V tun V dd V g M 3 V g M 4 M 9 V A V B S 1 S 2 D 1 D 2 In + In - M 1 M 2 Bias Circuitry M 7 M 10 M 8 V out Input Offset Voltage Drifts by 130 V over 170 C Input Offset Voltage Reduced to 25 V I tail M 5 M 6 V. Srinivasan, G. Serrano, J. Gray, and P. Hasler, CICC 2005, pp (Best paper CICC 2005)

Analog Signal Processing Techniques V in Constant Q Filterbanks Vector-Matrix

Output(s) Analog Output(s) x 1 w1 x 2 w2 x N w N VMM 128x32 VMM (0.

10 Analog Signal Processing Techniques V in Constant Q Filterbanks Vector-Matrix Multiplication I 1 + I 1 - I m + I m - Vtun Vdd out 1 out 2 out 3 out 4 out 5 out n I + out 1.5mm Gaussian Mixture Models / VQ V 1 V 2 V 3 V n Winner-Take-All Digital Output(s) Analog Output(s) x 1 w1 x 2 w2 x N w N VMM 128x32 VMM (0.5 m) < 1mm 2 Adaptive Filters y ŷ Steady-state weights w 1 cos w 2 sin - I out Rotation parameter (degrees)

11 Computing in Memory Input Memory Micro Processor (Pipelined Multiplexed) Input Y= A * B Computing Element Computing Element

12 Coefficient Generation Programmable Transform Imager LCDinterfaced withthe computer Imager Chip Digital Output VMM Block Selection Computational Pixel Element Array Technology ADCs Readout Offset Removal Readout Circuitry Block Selection 0.35μm CMOS Array size 256 x 256 Pixel size Fill factor 38% 6 μm x 6 μm XYZ Translator Mounting Posts Optical Slide Lens Polarizer Optical Bench Polarizer Light Source Original Image Read Image Read Log compress Measured Log compress DCT -> IDCT DCT -> IDCT Edge Enhan DCT Matrix 2D DCT Reconstruct Die area = 4.5mm x 4.5mm

13 Analog--Digital Signal Processing Real world (analog) Real world (analog) A/D Converter Specialized A/D ASP IC A/D DSP Processor DSP Processor Computer (digital) Computer (digital) Digital and Analog SP Efficiency CADSP = Cooperative Analog Digital Signal Processing Custom Analog ~ more efficient than Custom Digital (Mead 1990) Analog (VMM): 10MMAC/ W ( = 10TMAC / W) Digital: 4 MMAC / mw (DSP) 1W Computation MMAC/ W Ratio to digital 10mW DSP ICs LowPowerDSPs 0.02 to Analog VMM 1 to Analog Filterbanks 30 to mW 1 W 1000 to 10,000 improvement Gene's Law Analog VQ 1 to Analog HMM >1000 > nW 100pW 20 year leap Analog SP Power Year Microphone Cepstrum VQ HMM Digital Signal Processing

14 Resolution for Analog / Digital Tradeoffs 16 DSP log ( "Cost" ) digital analog Lower analog cost Lower digital cost Signal-to-Noise (Bits of Resolution) [Vittoz95, Sarpeskar98] Input Input ADC 16bit (16bit) A/D filter filter filter filter Analog filter bank (~FFT) FFT FFT 10 bit A/D bit A/D bit A/D bit A/D 10 ~10bit SNR SNR < 10bits 10bit Remaining DSP Application Program DSP DSP Application Program Remaining DSP DSP [Kucic, et. al. 2001]

Reconfigurable Signal Processing FPGAs Large Configurability Cost 100% S/W (Programmable) Tech trend Cost 100% H/W (Fixed Function) Power: Just MAC engine around

DSPs Low Power Processing - cell phones (processing < 30mW average) - hearing aids (1 mw levels) (AMI / DSP factory) Power: 54C series 4MMAC/mW Power does not include

15 Reconfigurable Signal Processing FPGAs Large Configurability Cost 100% S/W (Programmable) Tech trend Cost 100% H/W (Fixed Function) Power: Just MAC engine around 2-10MMAC/mW Baseline static power ~ 0.5W to 1 W Signal routing power / memory:? DSPs Low Power Processing - cell phones (processing < 30mW average) - hearing aids (1 mw levels) (AMI / DSP factory) Power: 54C series 4MMAC/mW Power does not include comm off chip (i.e. accessing memory) Innovation and Process Scaling moves solutions towards programmability and reconfigurability Power = ½ C Vdd 2 f for CMOS Chip to Chip (10pF load min, 2.5V): 32uW/Mbit (dynamic) Obtaining data for 4MMAC computation ~ 4mW

Moving towards Configurable Analog FPAA = Field Programmable Analog Arrays Useful Analog must be Programmable / Configurable Needing large number (>1000) of FPAAs Can be a prototyping tool, early

16 Moving towards Configurable Analog FPAA = Field Programmable Analog Arrays Useful Analog must be Programmable / Configurable Needing large number (>1000) of FPAAs Can be a prototyping tool, early devices, or final application 3mm RASP 1.x (2002) (T. Hall, P. Hasler, et. al, FPL, Sept ) RASP 2.x: RASP 2.5, 2.7: (C. Twigg & P. Hasler, CICC, 2006) - >50,000 Prog. Analog Devices - Used by > 100 Eng RASP 2.8x: (A. Basu, et. al, CICC, 2008) - Used by > 50 Eng and growing RASP 2.9x: mm Custom versus FPGAs: x2-3 speed, x10 area, x100 power Custom versus FPAAs: < x2 speed, < x2 area, < x2 power I in1 Switches are not dead weight - + I in2 -+ I in3 - + I out1 I out2 I out3 I out4

Next Questions on FPAAs FAQ on Large-Scale FPAAs Design time similar time for FPAA targeted and

design Similar speed as custom upto routing fabric speed (~10-20MHz in 0.

process shrink Node (nm) Prog #s (M) TMACs 350 4.0 1 90 64.0 64 45 256.

order filters / filterbanks, Capacitive summation / differencing, Ramp ADC, Algorithmic and

17 Next Questions on FPAAs FAQ on Large-Scale FPAAs Design time similar time for FPAA targeted and custom ICs Size can be similar to custom (programmable caps / I) Noise levels are similar to custom design Similar speed as custom upto routing fabric speed (~10-20MHz in 0.35um CMOS) Power levels often similar to custom solutions Techniques scale (~ ideal CMOS rules) with process shrink Node (nm) Prog #s (M) TMACs Neuromorfix to commercialize FPAA Computer (MATLAB) technology Compiled circuits include: n-th order filters / filterbanks, Capacitive summation / differencing, Ramp ADC, Algorithmic and Sigma-Delta ADCs, MP3 encoder, WTA, USB Analog Distributed Arithmatic, HMM classifiers, Van-der-pol Oscillator Extract Xcircuit Spice Netlist Simulate / Verify Compiler (RASPER)

18 Rapid Prototyping using FPAAs RASP 2.7 PhotoReceptor Response Paper Strip

Participants. > 20 Participants. ATL Workshop, Oct 2008 >25 Participants.

19 FPAA Workshops (RASP 2.8x) LA Workshop USC Campus, May 2-7, 2008 CO Workshop Telluride, July 2008 >30 Participants. > 20 Participants. ATL Workshop, Oct 2008 >25 Participants. Other workshops being planned: Boston, SF, Orlando, DC? GT Neurmorophic Classs (Fall2008, >20 students) Education / training / foundational theory is critical for designing.

20 Simulink FPAA Tool FPAA library Petre, et. al, ISCAS 2008]

further processing) Programmability and Configurability empowers neuromorphic design towards useful applications in a reasonable timeframe.

21 Getting higher power efficiency: Neuromorphic Engineering 400MMAC / neuron at 20pW vs. digital (100mW) and analog SP (100 W) Neuromorphic processing = event-based processing uses power only when useful signals are present ( always on in sensors or further processing) Programmability and Configurability empowers neuromorphic design towards useful applications in a reasonable timeframe. - Address Event Representation (AER) / FPGAs - FPAAs / FG devices ~ sizes of largest custom neuro ICs Can model pryamidal cells in configurable fabric in ~1mm 2 area with realistic channel, dendrite, and synapse elements (power in nw level and decreasing)

Levels of Energy Efficiency Subthreshold Transistor Operation Highest throughput / amount of power Programmable Circuits (FG transistors) Analog Signal Processing Configurable Signal Processing

22 Levels of Energy Efficiency Subthreshold Transistor Operation Highest throughput / amount of power Programmable Circuits (FG transistors) Analog Signal Processing Configurable Signal Processing Eliminate mismatch Programmability ~ x1000 improvement in power efficiency Wide accessibility Moving analog approaches /conceptual framework to a system design approach, similar to digital s system transformation in the 1970 s / 80 s. Large need for tools to compile / program these systems. Link most useful at system /sig processing level Education / training / foundational theory is critical for designing. These techniques open further opportunities to utilize / explore biologically inspired techniques DARPA activity: ISP, CT2WS, SyNAPSE, Healics, TEAM

TEST WIRE FOR HIGH VOLTAGE POWER SUPPLY CROWBAR SYSTEM

TEST WIRE FOR HIGH VOLTAGE POWER SUPPLY CROWBAR SYSTEM Joseph T. Bradley III and Michael Collins Los Alamos National Laboratory, LANSCE-5, M.S. H827, P.O. Box 1663 Los Alamos, NM 87545 John M. Gahl, University