Czech Technical University in Prague Faculty of Information Technology Department of Digital Design

Transcription

1 Czech Technical University in Prague Faculty of Information Technology Department of Digital Design Digital Circuits Testing Based on Pattern Overlapping and Broadcasting by Ing. Martin Chloupek A dissertation thesis submitted to the Faculty of Information Technology, Czech Technical University in Prague, in partial fulfilment of the requirements for the degree of Doctor. Dissertation degree study programme: Informatics Prague, August 2016

2 Supervisor: prof. Ing. Ondřej Novák, CSc. Department of Digital Design Faculty of Information Technology Czech Technical University in Prague Thákurova Prague 6 Czech Republic Copyright c 2016 Ing. Martin Chloupek ii

3 Abstract and contributions The high test data volume and long test application time are two major concerns for testing scan based circuits. Broadcast-based test compression techniques can reduce both the test data volume and test application time. Pattern overlapping test compression techniques are proven to be highly effective in the test data volume reduction. This dissertation thesis presents a new test compression and test application approach that combines both the test pattern overlapping technique and the test pattern broadcasting technique. It presents a novel on-chip broadcast-based test decompressor architecture that utilizes these two techniques. Test compression algorithm and architecture configuration heuristics are presented as well. This dissertation thesis will illustrate that these new techniques are effective in both the test application time and the test data volume reduction with low hardware area overhead. The proposed methodologies are verified by simulations and through experiments. In particular, the main contributions of the dissertation thesis are as follows: 1. New on-chip test decompressor architecture utilizing broadcasting and overlapping test pattern decompression techniques 2. New test set compression method suitable for the novel decompressor architecture 3. Scan chain configuration method suitable for the novel decompressor architecture Keywords: Testing, DFT, test compression, pattern overlapping, pattern broadcasting, on-chip test decompressor. iii

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5 Acknowledgements First of all, I would like to express my gratitude to my dissertation thesis supervisor, prof. Ing. Ondřej Novák, CSc.. He has been a constant source of encouragement and insight during my research and helped me with numerous problems and professional advancements. I would like to thank to Ing. Jiří Jeníček, Ph.D., and Ing. Martin Rozkovec, Ph.D. for their valuable inputs and comments. Special thanks go to the staff of the Department of Digital Design, who maintained a pleasant and flexible environment for my research. I would like to express special thanks to the department management for providing most of the funding for my research. My research has also been partially supported by the Ministry of Education, Youth, and Sport of the Czech Republic under research program MSM , by the grant of the Czech Grant Agency GA102/09/1668 and by the grant of the Czech Technical University in Prague, SGS10/118/OHK3/1T/18 and SGS11/091/OHK3/1T/18. Finally, my greatest thanks go to my family members, for their infinite patience and care. v

6 Contents Abbreviations xi 1 Introduction Contributions of the Thesis Structure of the Dissertation Thesis Background and State-of-the-Art Theoretical Background Fault Models Combinational Circuit Test Combinational ATPG Sequential Circuit Test Design for Testability Scan Based Built In Self Test Hybrid BIST Test Compression State-of-the-Art Embedded Deterministic Test Synopsys MUX Based Decompressor VirtualScan Universal Multicasting Scan Architecture COMPAS & RESPIN Discussion Overview of Our Approach Broadcast Decompressor Architecture Structural Dependencies Scan Chain Configuration Scan Chain Configuration Method I vi

7 Contents Scan Chain Configuration Method II Compression Algorithm Hardware Overhead Conclusions Summary Contributions of the Dissertation Thesis Future Work Bibliography 47 Reviewed Publications of the Author Relevant to the Thesis 55 Remaining Publications of the Author Relevant to the Thesis 59 vii

8 List of Figures 2.1 Test principle A generic structural test generation procedure Combinational circuit test Scan cell Scan chain Test compression Broadcasting test patterns Illinois scan Pattern overlapping EDT Synopsys MUX based decompressor Example MUX based decompressor configuration VirtualScan Universal multicasting scan architecture RESPIN Proposed decompression hardware Structural dependencies in five parallel scan chains example Test Vector and Test Vector Mask Diagram of the general algorithm for merging TVMs Broadcast rate with the respect to the count of the parallel chains for the benchmark b22_opt_c General structure of the pattern overlapping compression algorithm Built-in test equipment Decompressor hardware overhead comparison viii

9 List of Tables 2.1 Comparison of bit lengths of compressed test sequences of COMPAS against different compression methods Benchmark circuits and test vector set properties Scan Chain Configuration Method I.: Broadcast rate Scan Chain Configuration Method II.: Broadcast rate B-COMPAS: Test application time and compression effectiveness comparison B-COMPAS: Hardware overhead comparison against commercial tool B-COMPAS: Test application time and tester memory requirements comparison against commercial tool ix

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11 Abbreviations ATE ATPG BIST COMPAS CUT DFT DI DUT FDR IC LFSR MUX PCL RESPIN SE SI SoC TAM TV TVM UMC Automatic Test Equipment Automatic Test Pattern Generator Built-In Self-Test COMpressed Pattern Sequencer Circuit Under Test Design For Test Data In Design Under Test Frequency-Directed Run-Length Integrated Circuit Linear-Feedback Shift Register Multiplexer Parallel Chain Length REusing Scan chains for test Pattern decompression Scan Enable Scan In System on the Chip Test Access Mechanism Test Vector Test Vector Mask Universal Multicasting scan xi

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13 Chapter 1 Introduction The manufacturing process of integrated circuits is not flawless. Due to the high complexity of the manufacturing process with high demands on raw materials purity is the probability of occurrence of defects in the manufactured circuits very high. Digital devices are now omnipresent in almost all electronic devices including electronics used for safety critical applications, such as medical equipment or car control units. Thereby delivering fault free products is imperative. Yield is traditionally low on newer manufacturing processes. When new technology is introduced, even only 30% manufactured high end circuits are defect free [1]. Integrated circuits must be carefully tested to screen out faulty parts. Devices should be tested before and after packaging, after mounting on board and periodically during operation. Different methods may be necessary for each case, but it is of the utmost importance that defective units should be detected as soon as possible in the production chain. Therefore, test is one of the indispensable parts of manufacturing process of Integrated Circuits (IC s). The production of reliable high quality integrated circuits requires high quality testing. Test cost is a significant part of the overall costs of manufactured IC s. With each new technology generation, the developments in this field has lead to digital circuits containing more complex logic, thus the complexity of the test is rapidly increasing. Integrated circuits are tested during manufacturing process using external tester device generally called Automatic Test Equipment (ATE). Conventional testing using ATE involves storing test patterns and test response on an external tester device. The test data volume often exceeds the storage capacity of the ATE. These tester devices have also limited speed and the count of I/O channels. The IC s are produced in large amounts so the reduction of the test application time and the test data volume reduction is imperative. Marketing issues also influence testing. Cost is a key factor, as is time-to-market. The time spent on the ATE directly affects the final cost of the device. Test compression is a well established method that overcomes issues related to deterministic external testing of integrated circuits. This method has been widely adopted by the industry. The test data are stored on the external tester device in compressed form and in this form are transfered to the circuit under test, thus saving significant amount of tester s 1

14 1. Introduction memory and bandwidth. The Compressed Test Pattern Sequencer (COMPAS) is a highly efficient test compression tool [2 4] based on pattern overlapping principle. It is a very well evolved tool that generates compressed tests extremely fast with low memory requirements. It is capable of compressing a test for large industrial circuit in reasonable time. COMPAS is designed to use RESPIN (Reusing Scan Chains for Test Pattern Decompression) [5] on-chip test decompressor. RESPIN architecture is intended to test the System on the Chip (SoC). It uses the scan chains of different cores to decompress the test vectors for the tested core. RESPIN is not suitable for a single core design. When RESPIN is used on a single core IC, the amount of scan cells needs to be doubled, so using RESPIN in such a way results in a serious hardware overhead. The most significant drawback of the RESPIN architecture is that decompression using RESPIN is very time consuming, hence, for every bit received from ATE, it needs to rewrite all of the tested core scan cells in a serial way. Our goal is to improve COMPAS tool by utilizing pattern broadcasting technique and to develop a new on-chip decompressor architecture, that will not suffer from RESPIN drawbacks and will utilize pattern overlapping. Thereby further advance the scientific knowledge of test compression techniques based on pattern overlapping. 1.1 Contributions of the Thesis We have developed a new broadcast decompressor architecture that is described in this dissertation thesis. This architecture utilizes pattern broadcasting technique and it is able to apply any test vector to the design under test and it imposes very low area overhead to the design. We discuss this architecture in more detailed way in Chapter 3. We have also developed several heuristic algorithms for scan chain configuration for this architecture. These heuristics configure the scan chains that form the decompressor architecture for a given test set in a way, that the test set can be compressed with high compression ratio. The test set compression algorithm based on pattern overlapping, however modified for the needs of the new decompressor architecture described in this dissertation thesis. This new algorithm is highly effective. This new test compression and application method is compared with COMPAS tool and with the state-of-the art commercial tool. In particular, the main contributions of the dissertation thesis are as follows: 2 1. New on-chip test decompressor architecture utilizing broadcasting and overlapping test pattern decompression techniques [A.1, A.5] 2. New test set compression method suitable for the novel decompressor architecture [A.2, A.4] 3. Scan chain configuration method suitable for the novel decompressor architecture [A.1, A.3]

15 1.2 Structure of the Dissertation Thesis The thesis is organized into 4 chapters as follows: 1.2. Structure of the Dissertation Thesis 1. Introduction: Describes the motivation behind our efforts together with our goals. There is also a list of contributions of this dissertation thesis. 2. Background and State-of-the-Art: Introduces the reader to the necessary theoretical background and surveys the current state-of-the-art. 3. Overview of Our Approach: Explains the basics of our contribution. The decompressor architecture, the architecture configuration heuristics and the compression algorithm are described here. This chapter also presents our experimental results. 4. Conclusions: Summarizes the results of our research, suggests possible topics for further research, and concludes the thesis. 3

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17 Chapter 2 Background and State-of-the-Art In this chapter, we provide necessary theoretical background and survey of the current state-of-the-art test compression techniques. 2.1 Theoretical Background Digital circuit testing traditionally involve stimulation of the circuit s inputs and observing the responses on outputs. If the circuit responds to the stimuli as expected, the circuit passes given test. The set of input values applied to the circuit under given time is called input test pattern. All the test patterns applied to the circuit during test are called the test set. The response of a circuit for a given test pattern is called an output response. The test principle is shown in Figure 2.1. This dissertation thesis deals with manufacturing testing, as opposed to design testing, which happens before manufacturing, and on on-line testing, which happens after. INPUT PATTERNS DIGITAL CIRCUIT OUTPUT RESPONSES COMPARATOR STORED CORRECT RESPONSES TEST RESULT Figure 2.1: Test principle At a general level, there are two basic types of testing, called functional testing (also known as black-box testing) and structural testing (also known as white-box testing). Functional testing attempts to validate the function of circuit under test according to its functional specification. Due to complexity of todays digital circuits, it may take extraordinary amount of processing to generate a test. It may take a long time to apply 5

18 2. Background and State-of-the-Art a test. The number of test vectors can be larger than the number of faults. It may be unreachable task for test engineers to design cost-effective functional test solutions when dealing with VLSI technology. Structural test, on the other hand, attempts to uncover any defects in the underlying gates and interconnect within a device due to fabrication process errors. The structural tests depend on the specific structure of the circuit, so the structural test patterns may not have a functionally meaningful output. The core of the structural testing is based on faults modeling and simulating the fault effect. A fault model identifies targets for testing and makes analysis possible. It allows us to measure effectiveness of a test by experiments. One of the greatest advantages of structural testing is that it allows development of algorithms [6]. A structural test for a given circuit is generated from its structural description - netlist. The test generation algorithm starts by identifying faults in the circuit - creating a fault list. Then for each uncovered fault, the algorithm generates a test and simulates which other faults are covered. A single fault test pattern usually covers more faults. Covered faults are removed form the fault list and the algorithm continues, unless desired fault coverage is reached or all detectable faults are covered. As shown in Figure Fault Models Fault models are analyzable approximations of defects and are essential for a test methodology [7]. Faults can be mainly divided into classes according to their time effect: Permanent faults: Faults are always present and stable. Temporary (intermittent, transient) faults: Faults appear and disappear in short intervals of time. The aim of this dissertation thesis is manufacturing tests, so only permanent faults are discussed. There are many fault models developed, for example: Gate Level Stuck-at Fault Model, Transition Delay Fault Model, Path Delay Fault Model, Bridging Fault Model. They can be further classified in numerous ways, can be modeled according to different levels of abstraction, however the basic fault model and the most widely used is the Stuck-at fault model. It assumes, that a defect causes a signal line to be permanently stuck at high or low logical level. Stuck-at tests form the core of digital testing. Every test plan includes a high coverage stuck-at test set. One of the greatest advantage of stuck-at fault model is, that it is so simple, it is independent of the technology. It represents many physical faults. Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests [8]. For digital logic single stuck-at fault model offers best advantage of tools and experience [9]. 6

19 2.1. Theoretical Background BEGIN Generate a fault list for given circuit Select an uncovered fault from the fault list Generate a test for the slected fault Evaluate a fault coverage, remove covered faults from the fault list NO Is coverage adequate? END YES Figure 2.2: A generic structural test generation procedure Combinational Circuit Test Combinational circuits are stateless circuits. There are no memory elements to hold a previous internal state and so these circuits are usually simpler in design. Structural testing of combinational test is pretty straightforward. A test set for a given fault model is generated by an Automatic Test Pattern Generator (ATPG). The test set with correct responses is stored in memory of ATE, see Figure 2.3. Each input test vector is applied to the inputs of the Circuit under test (CUT) in a sequence by a test controller. Each response of the circuit is compared by the test controller with stored correct response. If all responses to all test vectors match, the circuit passes given test Combinational ATPG When dealing with single stuck-at fault model, the task for an ATPG is to generate a test set, that will cover all detectable stuck-at faults. The fundamental principle of the ATPG is, that it injects a fault into a circuit and causes its effect to propagate to a circuit 7

20 2. Background and State-of-the-Art INPUTS IC MEMORY ATE CUT TEST CONTROLLER OUTPUTS Figure 2.3: Combinational circuit test output. A deterministic test pattern generation procedure based on path sensation can be summarized in following steps: Choose a fault to insert from a fault dictionary Fault activation or excitation: Drive a signal value at the fault model site that is opposite of the value produced by the fault model (trigger a fault). Fault propagation: Select a path from the fault site to an output and specify other signal values to propagate the fault along the path to the output (make fault visible at the outputs). Line justification or Path Sensitization: Specify input values so as to produce the signal values specified in fault activation and fault propagation. All deterministic test generation algorithms must perform these operations in some fashion, such as D-algorithm [10], PODEM [11], FAN [12], TPSA [13], SOCRATES [14], EST [15], Recursive learning [16]. These algorithms employ heuristics that try to find all necessary signal assignments for a test as early as possible. They try to search as little of the above decision space as possible. Another class of ATPGs worth of mentioning are ATPGs based on binary decision diagrams and SAT based techniques. These methods are based on formal techniques. They show better run times when dealing with hard faults. Some example algorithms are: CATAPULT [17], TSUNAMI [18], TG-PRO [19] and PASSAT [20]. 8

21 2.1. Theoretical Background Sequential Circuit Test Almost all of todays digital circuits are sequential. These circuits contain combinational logic and memory elements, usually flip-flops. Testing of sequential digital circuits is very difficult task. It may take an extraordinary amount of processing to generate a test for such a circuit. It may take a long time to apply a test, hence we usually need more than one test vector to test one fault. For example, if we want to observe activity on the most significant bit of a 32-bit counter, it can only be observed after 2 31 clock cycles. Some fault can be even untestable, hence we can not observe activity at certain point of the circuit because of its complexity. Several methods have been researched to generate a test for sequential circuits. Sequential ATPG are mostly based on time-frame expansion methods or simulation based methods. Many algorithms based on these methods have been developed, the most significant are GENTEST [21], CONTEST [22] and ATOMS [23], however due to problems mentioned before, there are not suitable for large VLSI circuits Design for Testability To overcome issues related to growing complexity of digital circuit testing and testing of sequential circuits, the research in this field has led to development of techniques, that significantly improve circuit testability by adding additional test support hardware to the design. The major breakthrough in testing complex digital circuits was invention of scan chain [24] DFT technique, thus scan based testing. This technology improves controllability and observability of a circuit. It allows us to set an internal node to a required logic value and propagate its logic value to a pseudo or primary output. The fundamental of a scan chain is scan cell. Basically, we create a scan cell from a flip-flop by adding a multiplexer to its D input, as Figure 2.4 shows. This multiplexer is Scan enable (SE) D in (DI) Scan in (SI) D Q Clock Figure 2.4: Scan cell driven by the signal Scan enable (SE). When the signal SE is not asserted, the scan cell behaves like regular flip-flop and the circuit is in mission mode. The DI input is active and is connected in the design as flip-flop s data input. When the SE signal is asserted, 9

22 2. Background and State-of-the-Art the circuit is in the test mode. The scan cells are then connected as a shift register. This means, that neighboring scan cells are connected from flip-flop s D output to neighboring scan-cell s SI input, as Figure 2.5 shows. This enables us to shift in and shift out any data COMBINATIONAL LOGIC Serial scan in (SI) D Q D Q D Q D Q Serial scan out Clock Scan enable (SE) Figure 2.5: Scan chain to circuit s flip-flops through Serial scan in and Serial scan out pins, when the signal SE is enabled. We create a full scan chain in the circuit by creating scan cells from all flip-flops in the circuit and connecting them as described above. This means, we can control and observe sequential elements in the circuit and by this means we can test the sequential circuit as combinational logic. The test of sequential elements of the circuit is done in a simple manner by shifting in series of logical ones and zeros through Serial scan in pin and observing if the same sequence is shifted out from the Serial scan out pin. Over the last couple of decades scientist have developed many techniques to improve the testability of scan based integrated circuits as well as to reduce test application time and test data volume. According to [25], these techniques can be categorized into three general approaches: a stand-alone Built-In Self-Test (BIST), a hybrid BIST, and test data compression Scan Based Built In Self Test Stand-alone BIST technique is usually based on Linear-Feedback Shift Registers (LFSR) for the test set generation and the test response compaction. BIST utilizes on-chip hardware to perform the test pattern generation, response verification and test control [26]. This is very useful for external testing, hence there is no need for an ATE memory. The ATE basically starts the test and awaits the response from the on-chip test controller, if the circuit passed or not the test. This can be very beneficial, hence in can be used for in-filed testing. However, a stand-alone BIST generally suffers from low fault coverage because of Random-Pattern-Resistant faults [27]. The BIST concept found a wide usage 10

23 2.1. Theoretical Background Compressed test patterns Decompressor S c a n c h a i n s Output compactor Compacted CUT responses Figure 2.6: Test compression in testing regular structures, such as random-access memories, read-only memories, and programmable logic arrays [28] Hybrid BIST A hybrid BIST is an approach, that stands between BIST and external testing. It combines a random test pattern generation and a deterministic test pattern generation. Deterministic test patterns or seeds are stored in an ATE memory and are applied to the Circuit Under Test (CUT) after the pseudo-random test phase to boost the overall fault coverage [29] Test Compression The test compression method generally involves generation of deterministic test set for a given circuit by an ATPG, the test set is then compressed by a compression tool and stored in the compressed form in ATE s memory. The compressed data is transferred to the CUT and decompressed using on-chip decompressor, so the original deterministic test vectors are applied to the scan chains of the circuit, as Figure 2.6 shows. The test data compression method requires adding a test pattern decompressor and response compressor block to the design. After decompression, deterministic test vectors (TV) are applied to the Design under Test (DUT), so all detectable faults can be invest- 11

24 2. Background and State-of-the-Art igated. This means, test vector compression is a lossless compression. Test compression technique is generally more time-effective than a hybrid BIST, which applies a large number of test patterns during pseudo-random test phase. The test compression is especially suitable for a reduced pin-count environment, where a narrow interface between the tester and the CUT is desirable. The test compression methods exploit two well know facts [25]: Test vectors are highly compressible, because only 1% to 5% of their bits are specified, the rest are don t cares. Test cubes (vectors with don t cares) tend to be highly correlated hence faults are structurally related Test compression techniques can be categorized according to core principle: Coding based Linear decompressor based SAT based Pattern overlapping based Pattern broadcasting based Coding Based Test Compression Techniques Coding-based methods provide effective test data reduction. These methods employ data compression codes to encode test cubes, such as run-length codes, Huffman coding, dictionaries and others. Examples of these techniques are: [30 35]. These methods are usually ineffective in test time reduction and require more complex control logic SAT Based Test Compression Techniques Boolean satisfiability problem solving (SAT) based [36,37] test compression methods show very promising results on test set reduction effectiveness. However, SAT-based algorithms suffer from an overhead for solving easy-to-test faults, which represent the majority of all faults. They also usually suffer from long test generation time Linear Decompressor Based Test Compression Techniques Linear decompressor based methods [38 47] decompress data by using LFSRs, ring generators [48] or XOR networks. The decompressor can by characterized as combinational (XOR network) or sequential (LFSR, cellular automaton or ring generator). The advantage of linear decompressor is that we are able to describe the decompressor by a set of linear equations. These equations can be computed in a reasonable time even for large circuits. 12

25 2.1. Theoretical Background Combinational linear decompressors are often used for data transfer bandwidth reduction as they represent a simple and powerful solution. Sequential linear decompressors rely on previous decompressor state. Free variables from earlier clock cycles are used when encoding a scan slice in the current clock cycle. The decompressor seeds can either be transfered on the begging of decoding (static reseeding) or continuously during scan chain loading (dynamic reseeding). Static reseeding is hardware consuming as it requires shifting the seed into a shadow shift register during the phase of previous test pattern decompression and actualizing the decompressor state by the new seed. Dynamic reseeding approach resets the decompressor state before pattern decompression. The reason for resetting the decompressor between test cubes is that it decouples the system of linear equations, that have to be solved when encoding each test cube. If the decompressor is not reset, then the complexity of the linear equations would grow very large, as each test cube would depend on all the free variables injected up to the point. All linear decompressors contain dependencies between their outputs. The amount of clock cycles is not optional, the care bit positions are fixed. There are few different strategies for handling uncodable test cubes. A simple approach is to just bypass the decompressor, another is to try different test cube using ATPG. A third approach is to redesign the linear decompressor so it uses more free variables. Trade-off between the flexibility and hardware overhead was studied in [49]. Another approach to increase decompressor s ability to encode test cubes is to utilize clock gating [38]. The number of free variables received form the ATE to decode each test cube varies in expense of more complex control logic and naturally less coding efficiency. It is possible to encode all test cubes and decode them using this approach. Changing the number of shift clock cycles wa used in [50]. A feedforward technique was used in [51] in order to improve the quality of the first vectors encoded after decompressor reset. The proposed approach adds additional XOR between decompressor output and scan chain input. The decompressor output is then XORed with value of last scan cell of a scan chain, thereby it expands the free-variable dependence of each scan cell, which increases the probability of encoding a test cube. It was also found that better compression parameters can be obtained when the similarity of test patterns testing different faults is exploited [52]. According to the paper each compressed pattern consists of three parts (parent, control and incremental) that can be treated separately. The parent part can be stored in dedicated scan chains and may form a stable part of a cluster of test patterns. It can be modified by the incremental parts according to the control signals from the control part. A drawback of these methods is that they generally need specific support during the ATPG process they need specialized ATPG. However these methods were adopted by the industry [41]. The representative of linear decompressor based method is described in section in more detail. 13

26 2. Background and State-of-the-Art Pattern Broadcasting Test Compression Techniques Broadcasting is the simplest way of test pattern decompression, as the patterns are decompressed in the fan-out network only. Broadcasting was originally proposed by Lee in [53,54]. The idea is to use a single ATE channel to drive multiple independent scan chains. This means, that the same data are shifted in multiple independent scan chains simultaneously (multiple circuits), as shown in Figure 2.7. If the scan chains are independent, i.e. the subcircuits corresponding to the scan chains need not be tested simultaneously by patterns belonging to more than one scan chain, the broadcast system does not impose constraints to testing the subcircuits. The number of broadcast scan vectors will be equal to the sum of scan vectors needed for each subcircuit in the worst case [25]. Data channel from ATE Figure 2.7: Broadcasting test patterns This type of decompression provides a lower number of encodable test cubes than all other methods, but it has an advantage of easier incorporation of decompressor imposed constraints to the ATPG. However, scan chains of a single circuit are dependent. By using this technique on dependent scan chains, some of the faults become untestable, hence some of the test vectors are inapplicable. This is called structural dependences in chains. The Illinois scan architecture [55, 56] was the first pattern broadcasting technique that addressed the issue of dependences. It was proposed to deal with these structural dependences by utilizing two modes of operations; the broadcast mode and serial mode. Figure 2.8 shows the basic structure of the Illinois scan architecture. The serial connection of the chains is used for solving the problem of setting different values in different scan chains that test one subcircuit. According to the figure, parallel chains are connected into a single scan chain in this mode. The parallel chains are not driven from one source, but rather the data flows from one chain to the other in a serial way. The multiplexers input in the figure are set to logic zero. When the multiplexers are set to logic one, the architecture is in broadcasting mode. This means, that the same data is shifted in the parallel chains 14

27 2.1. Theoretical Background SI MODE Figure 2.8: Illinois scan they are driven from the same source. The success of broadcasting methods depends on the ratio of the test patterns that can be broadcasted shifted in the parallel chains from one source. The broadcasting technique has been widely adopted by variety of companies. Several techniques were developed to deal with dependences, each company has developed their own methods. The representative of state-of-the-art technique is described in Section Linear decompressor based methods and broadcasting based methods are two commonly used approaches in commercial test compression tools Pattern Overlapping The main idea of pattern overlapping was firstly introduced in [57]. This method is based on finding the best overlap of test patterns for a given test set, that is pre-generated by an ATPG. This means, that we have current scan-chain value and we are trying to find a test vector that would share bit values from the test vector start with the scan-chains bit values at the end. By shifting the non-overlapped bits, we introduce the new test vector to the tested circuit. Figure 2.9 represents the overlapping principle. This method was firstly used on compacted test vectors and later than was discovered that it is more efficient on partially specified test vectors [5] test vectors with don t care values. The Compressed Test Pattern Sequencer (COMPAS) tool is a state-of-theart representative of pattern overlapping test compression methods. This tool is proven to have high compression ratio. COMPAS tool uses RESPIN architecture as an on-chip decompressor. The RESPIN architecture imposes serious area overhead when dealing with single core design. COMPAS tool and RESPIN architecture is discussed in more detailed way in Section

28 2. Background and State-of-the-Art 1 0 X X 0 X 1 X X 1 X 1 1 X 1 X 0 X 1 1 X 1 X 1 X X Figure 2.9: Pattern overlapping 16

29 2.2. State-of-the-Art 2.2 State-of-the-Art Embedded Deterministic Test Embedded Deterministic Test [41] is a DFT methodology that was brought by Mentor Graphics. The decompressor architecture consists of a ring generator and a phase shifter, as shown in Figure The ring generator is a distinct form of a linear finite state Data from ATE Ring generator Phase shifter Scan chain inputs Figure 2.10: EDT machine. It receives stimuli from the ATE through several input channels. The decompressed data goes then from the ring generator to a phase shifter. The phase shifter feds relatively large number of circuit s scan chains and reduces linear dependences between sequences entering scan chains. The compression of test patterns is accomplished by solving matrices of linear equations. The ATE data are used as boolean variables seeds. Equations are formed according to ring generator s and phase shifter s implementation. This process needs a specific support form the ATPG, hence some test patterns are inapplicable because of linear dependences. 17

30 2. Background and State-of-the-Art Synopsys MUX Based Decompressor The Synopsys test solution is based on broadcasting. Synopsys deals with dependences by using a MUX-based pattern decompressor. The ATE drives MUX-based decompressors data input and control, so several ATE input channels are necessary, as shown in Figure The decompressor is a multi-mode shared scan-in architecture implemented with Data from ATE MUX-based decompressor Scan chain inputs Figure 2.11: Synopsys MUX based decompressor MUX gates. The decompressor is switching on each clock cycle between different operation modes, so a different input sharing configuration can be chosen at every shift [58,59]. Example of a MUX configuration for such a decompressor can be seen in Figure There Data from ATE Scan chain inputs Figure 2.12: Example MUX based decompressor configuration is also a mode in which MUXs can be used to reconfigure the scan cells into a regular scan chains, without compression. This decompressor is intended to be used with constrained ATPG, that creates test patterns consistent with the shared scan-in dependences. 18

31 2.2. State-of-the-Art VirtualScan SynTest technologies introduced a solution called VirtualScan [60]. VirtualScan is also broadcasting based pattern decompressor. The VirtualScans decompressor consists of three blocks: the VirtualScan controller, the broadcasting network and the scan connector, as shown in Figure The broadcasting network distributes the test patterns from a Data from ATE Broadcasting network Scan connector VirtualScan controller Scan chain inputs Figure 2.13: VirtualScan few scan input channels to many internal signals. It is a combinational block constructed from one or more logic gates. Internal signals from broadcasting network end in the scan connector block. The scan connector block is constructed from MUX gates. It can switch from the broadcasting mode into a regular scan chain or different shared-in configuration, similarly to Synopsys solution. These blocks are driven by the VirtualScan controller block, which can be a combinational block, like decoder, or sequential block, like finite state machine. This solution of course needs special ATPG support Universal Multicasting Scan Architecture In this section we describe another approach, named multicasting. According to our knowledge, this technology was not adopted by industry. Multicasting is a scan based approach, that allows sending a selected test patterns to a selected scan chains. This approach can be used with standard ATPG. Specifically, we aim description to methodology named universal multicasting scan (UMC scan) [61]. The UMC scan architecture consists of Universal multicasting controller and clock gating logic, as show in Figure The Universal multicasting controller is driven by single ATE input channel. The data from ATE is received in form of packet. Each packet consists of a control bit sequence and a test pattern sequence. The control sequence directs the test pattern to a specific scan chain or to a group of scan chains. This is accomplished by the clock gating logic, the AND gates in the Fig- 19

32 2. Background and State-of-the-Art Single data channel from ATE Control bits Sub pattern Universal multicasting controller Clock gating Clock Figure 2.14: Universal multicasting scan architecture ure These AND gates are sourced from the Universal multicasting controller and the clock and they gate clock to each scan chain COMPAS & RESPIN The Compressed Test Pattern Sequencer (COMPAS) algorithm based on a pattern overlapping has proven to be highly effective in test data compression, see [2 4] and Table 2.1. COMPAS tool takes the pre-generated test set, that contains the partially specified test vectors as an input. These test vectors should have as many don t cares as possible. By overlapping the partially specified test vectors, we can significantly reduce the test data volume. Success of this method is heavily dependent on the test-cubes fill rate. However large industrial circuits usually have don t cares densities of more than 95%, according to [41] and [3]. COMPAS uses as an on-chip decompression architecture RESPIN (REusing Scan chains for test Pattern decompression) [5, 62] RESPIN The RESPIN on-chip decompressor architecture is intended to test the System on the Chip (SoC). It uses the scan chains of different cores to decompress the test vectors for the tested core. It is suited to decompress overlapped test patterns. An example of the RESPIN architecture is shown in Figure The RESPIN architecture operates as follows: In the 20

33 2.2. State-of-the-Art Table 2.1: Comparison of bit lengths of compressed test sequences of COMPAS against different compression methods Circuit MinTest Stat. LFSR Illinois FDR EDT RESPIN COMPAS Coding Reseeding Scan Codes ++ s s s s Test enable Scan in Other cores scan chain Tested cores scan chain Figure 2.15: RESPIN beginning, both scan chains are loaded with the first test pattern or the state after reset is used, for example both scan chains contain only logic zeros. For next pattern to be decompressed, we load just one bit from the ATE with the signal Test enable raised. Then we apply the same amount of clock cycles as the length of the other cores scan chain with the signal Test enable not raised. So the test pattern circulates in the other cores scan chain and at the same time it is copied to the tested cores scan chain. So the data in the tested cores scan chain can be rewritten by the test responses and we retain unchanged test pattern in the other cores scan chain for next overlapped pattern decompression. The RESPIN decompressor architecture is not suitable for a single core design. Using RESPIN in such a way results in a serious area overhead. This would mean doubling the amount of flip flops in the design, just for the test pattern decompressor. The most significant drawback of the RESPIN architecture is that decompression using RESPIN is very time consuming, hence, for every bit received from ATE, it needs to rewrite all of the tested core scan cells in a serial way. The authors idea was to use another faster clock source for the circular mode, so the time spent in the circular mode wouldn t be a bottleneck, however introducing another clock to the design may not be feasible. 21

34 2. Background and State-of-the-Art Discussion In this chapter we have provided survey of the state-of-the-art technology for testing digital circuits. Almost all of these technologies were brought by or adopted by industry. We do not provide descriptions of technologies that are only broadcasting or overlapping based but we provide description of technologies that are multicasting and linear decompressor based as well. It is a very difficult task to compare state-of-the-art test compression techniques. The authors of the publicized papers are reluctant to publish results on ITC 99 benchmark circuits [63]. Even if they do, the provided information is very plain. Fault coverage, parallel scan chain count, test application time, neither of these are usually described. Some authors demonstrate the efficiency on decompression of random resistant faults only and other authors compress and decompress the whole ATPG deterministic test sequence. The quality of a compressing method is influenced not only by the compression ratio but also by the size and complexity of the decompressing hardware, by the computational complexity of the algorithm for finding the compressed test sequence, by time and power consumed during the test and other aspects. 22

35 Chapter 3 Overview of Our Approach Complex circuits can be tested by deterministic test patterns with the help of dedicated instrumentation containing test access mechanism (TAM), test wrappers and scan chains. Unfortunately the test time is unacceptably high for this kind of testing because the patterns have to be shifted through long scan chains and narrow TAM otherwise more expensive parallel TAM channels and parallel scan chains have to be devoted for test. The volume of the test data stored in a tester is also a limiting factor. If random testing with relatively low fault coverage (<95%) provided by built-in self test mechanism is unacceptable, test compression will be the only remaining possibility how to reduce test time and data while keeping high test coverage. It is commonly accepted that for large circuits under test with scan chains it is necessary to adopt some test compression methodology that reduces test data volume, test time and energy consumption during test, see Section When looking for appropriate test compression method it is necessary to consider several parameters: test data, test time, TAM bandwidth, compression algorithm complexity and decompressor hardware overhead. Test compression is based on fact that modern circuits can be typically tested with deterministic test patterns containing more than 95% of don t care bits. The test pattern care bits are obtained on the decompressor outputs by unrolling the decompressor seeds while don t care test bits are replaced by pseudorandom values that are obtained on the resting decompressor outputs positions. Special automata that can easily reach a given specific value on some of its outputs in a given clock period and on the rest of outputs and clock periods generate pseudorandom values can be used for test pattern decompression. The sequence of the automaton seed, injected internal state values and control bits serves as one compressed test pattern, usually substantially smaller than the number of corresponding input CUT bits. In this dissertation thesis we propose a scheme that uses broadcasting of overlapped test patterns into parallel scan chains. The sequence of overlapped patterns is computed by a specialized algorithm called COMPAS that spares CPU time needed for finding suboptimal pattern overlapping. Each of the mentioned methods has its advantages that could be used in a methodology 23

36 3. Overview of Our Approach that combines several compression principles. It is useful to take use of similarity of test patterns detecting different faults. The similarity can be twofold: majority of test pattern bits are the same as in other test pattern or the bits are the same but reordered. These features can be addressed in the decompressor hardware by possibility of storing the value of the previous pattern and injecting modification bits or rotating its content. Broadcasting of patterns to parallel scan chains divides the test pattern length by the number equal to the number of chains. It can reduce the length of a shift register storing the backup of patterns for refreshing the scan chain content after corruption by test responses. In case of broadcasting the shift register length is only a fraction of the number of CUT flip/flops. Broadcasting is simple; the only structural dependency is formed by the same logical value distributed to the parallel scan chains in one clock cycle. Using a ring generator with several inputs makes the decompressor flexible in the sense that the decompressed test patterns can be decoded in a small number of clock cycles after the ring generator reset, see Section This feature is not necessary to be used for decompressors that concatenate internal states in order to obtain ordered pattern sequence employing pattern similarity. When concatenating such patterns it is useful to remember previously decoded patterns for decoding the actual one. It was found that test sequence can be ordered in such a way that decompressors need to have only a simple mechanism for next pattern decoding with a limited flexibility. When using a single LFSR or ring generator it is not feasible to search efficiently in the space of test vectors and to find the best suiting clusters of them that could be converted into the LFSR state sequence because of the complexity of the computations. Using a scan chain instead of the LFSR seems to be an alternative to the previously mentioned approach. The main advantage of the decompression scheme based on the scan chains is the simplicity of the future and previous content of the chain computation. No special arithmetical operation is necessary to be used for it, only fast instructions of field elements concatenation can be used. For practical application of the method there remains a problem with the necessity of high hardware overhead caused by existence of a shift register for storing the test patterns during the response capturing. This problem could be healed by use of pattern broadcast as mentioned above. As mentioned in Chapter 1, our goal is to improve COMPAS tool by utilizing pattern broadcasting technique and to develop a new on-chip decompressor architecture, that will not suffer from RESPIN drawbacks and will utilize pattern overlapping. For purpose of that, we have developed a new broadcast decompressor architecture that is described in Section 3.1. Description of the decompressor architecture is followed in Section 3.2 by description of several heuristic algorithms for scan chain configuration for the decompressor architecture. In Section 3.3 we propose an new compression algorithm called B-COMPAS that compresses test patterns in parallel scan chains by their overlapping. In Section 3.4 we demonstrate some experimental data and comparisons with an industrial compression tool. 24

37 Bypass CUT Preset SHreg Shift Counter Feedback Counter MISR 3.1. Broadcast Decompressor Architecture 3.1 Broadcast Decompressor Architecture We propose to use a broadcast architecture [A.1, A.5], based on the Illinois scan, however slightly different. 4 The 5 Illinois 1 scan 2 architecture 3 2 has been 3 discussed 4 5 in 1 Section The proposed decompression hardware is shown in Figure 3.1. It consists of an n-bit master shift register with a feedback multiplexer switching between the Tdi signal from a tester and last shift 1 register 2 3cell 4value. 5 The m-bit 1 parallel 2 scan 3 chains 4 5are connected to the master shift register outputs (m<n). The master shift register broadcasts the test sequence Broadcast decompressor Tdi DFF DFF DFF DFF DFF New bit Tclk CUT Parallel Chains SC0 0 SC1 0 SC2 0 SC3 0 SC4 0 SC0 1 SC1 1 SC2 1 SC3 1 SC4 1 SC0 2 SC1 2 SC2 2 SC3 2 SC4 2 Clk Shift Figure 3.1: Proposed decompression hardware from the Tdi input to the scan chains. After capturing the test responses in the parallel scan chains the master shift register refreshes the test pattern in scan chains during n+1 clock cycles with the current master shift register state modified by a Tdi. The proposed compression method uses the following advantageous features of the proposed decompressor architecture: 25

38 3. Overview of Our Approach Structural dependences between parallel scan chain bits are regularly distributed. Subsequent test patterns differ in a simple shift operation it is easy to search for optimized test pattern that maximally overlaps a test pattern. Broadcast Test System One scan Broadcast chain contains Controller independent bits only. We consider that a scan chain connects flip-flops of a functional block of hardware where Decompressor detection of faults may require setting Finite more flip-flop State Machine values to given logical values. The arrangement guarantees possibility of setting all necessary test patterns that test functional block faults. Setting test pattern Setup Resetcare bits on scan chain positions CUT that wrapper are structurally dependent in parallel scan chains into different values can be Scan done chains by shifting the structural dependences (Figure 3.2). Their shifting is done by parallel scan chain clock gating. The number of Test gated clock cycles between two master scan chain clock cycles defines the size of the dependences shift, see Section CUT Bypass Structural Dependencies Figure 3.2 demonstrates structural dependencies in parallel scan chains. Bits are denoted as 1, 2, 3, 4, 5 from the master shift register. Left figure demonstrates situation where Preset Shift Feedback the scan chains are clocked simultaneously with the master shift MISRregister. The right figure SHreg Counter Counter demonstrates shifting the dependencies by gating the scan chain clock for 1 period between master shift register clock cycles. By further extending the gating delay structural dependencies can be totally eliminated Figure 3.2: Structural dependencies in five parallel scan chains example Broadcast decompressor Tdi DFF DFF DFF DFF DFF New bit Tclk 26 CUT Parallel Chains SC0 0 SC1 0 SC2 0 SC3 0 SC4 0 SC0 1 SC1 1 SC2 1 SC3 1 SC4 1

39 3.2. Scan Chain Configuration 3.2 Scan Chain Configuration In this section, we provide the theoretical background and description of our heuristic algorithms for scan chain configuration. We are dealing with the problem of how to optimally partition a single long scan chain into several parallel short chains, that will form the decompressor architecture described above. The broadcasting rate of a test vector set is a major issue here, hence it influences the compression rate and the test application time. The broadcast rate of a test vector set is the amount of test cubes that are applicable to the CUT using the proposed decompressor architecture without gating the clock of parallel chains ( Clk signal in Figure 3.1). Obviously, the higher the broadcast rate the more effective is the test compression. The proposed methods later in this section as well as the compression algorithm described in Section 3.3, are neutral of an ATPG. Any standard ATPG that can generate test set with partially specified test vectors can be used. These methods take the pregenerated test as input and according to specified parameters (count of parallel scan chains and length of the master shift register) they compute the optimal arrangement of the scan chains by analyzing the the test cubes of the test set. A test engineer is required to customize these parameters and evaluate the broadcast rate. Each circuit is different and thereby optimal settings of the parameters do not necessary result in optimal broadcast rate, thus optimal test compression rate and test application time. The hardware area overhead imposed to the design by the master shift register must be taken into account as well. When targeting the lowest hardware are overhead (the shortest master shift register), the lengths of the parallel chains should be equal to each other and the count of parallel chains should be equal to the lengths of parallel chains. The length of the master shift register must greater or equal than the length of the longest parallel chain and also greater or equal than the count of parallel chains. This is the minimal length of the master shift register. However, if the master register is longer than the minimum, then there ale less structural dependencies in the parallel chains, thus higher broadcast rate Scan Chain Configuration Method I. When dealing with scan chain partitioning, we are not precisely ordering cells in the scan chains, hence, it is not suitable without layout awareness. Scan cell reordering without optimizations for routing could lead to an unroutable design or a design with a serious area overhead or performance degradation due to long wires between the scan cells [64,65]. That is why we deal, in our approach, with just which scan cell should belong to which parallel scan chain. We leave the parallel chain order and scan cell order of the parallel chains to the layout aware scan cells ordering techniques. For the purpose of this method we define a test vector mask. The test vector of length l contains the values: logical 1, logical 0 and don t cares. The test vector mask (TVM) of the test vector is a sequence of 1s and 0s that has the same length l as the test vector (TV), as Figure 3.3 shows. Each value of the TVM corresponds to a value of its test vector. If the bit in the test vector is set as logical 1 or logical 0, the corresponding bit in the TVM 27

40 3. Overview of Our Approach is set to 1. If the bit is set as don t care, the corresponding bit in the TVM is set to 0. The TVM may correspond to many test vectors. The TVM reflects care and don t cares of test cube. X 1 0 X X 1 TV TVM Figure 3.3: Test Vector and Test Vector Mask The basic idea of our heuristic algorithms [A.1] is that we merge together the TVMs that are close to each other, this means that they differ in the minimum of 1s. However, this is not sufficient, hence, there is no information about how many test vectors the TVM covers, so we include the number of test vectors covered by the TVM in our heuristic algorithms (TVM weight). Figure 3.4 shows the general structure of our heuristic algorithms. We present four heuristic algorithms in this dissertation thesis. These heuristics share the same general structure and differ only in criteria for selecting the TVMs for merging. BEGIN END Create mask for each TV Create last group from unmarked positions Mask that covers maximum number of TV - max(cover) Merge equal masks, create cover NO The number of 1s of mask multiplied by mask cover is maximum - max(cover * 1s) Select best mask YES Are there more unmarked positions left than desired parallel chain length? Mask cover divided by the number of mask 1s is maximum - max(cover/1s) Is no. of 1 s in selected mask less than desired parallel chain length? NO Create group from this mask, this group forms parallel scan chain, mark used positions as already set YES Selected masks differ in minimum of 1s - min(diff) Find best mask for merging, merge these masks The number of sum masks cover divided by number of 1s they differ in is maximum - max(sum cover / diff) Figure 3.4: Diagram of the general algorithm for merging TVMs 28

41 3.2. Scan Chain Configuration The heuristic algorithms take ATPG generated test vector set with partially specified test vectors as an input. It is the same test set, that is used by the compression algorithm. For each test vector in the test set, the algorithms create the TVM and then the equal TVMs are merged. By these operations, we gain the information of how many TV each TVM covers we count weight of TVM. Then the algorithms select the best two vector masks according to heuristic selection criteria and merges them. The merged vector mask covers all the test cubes covered by its predecessors. The merging continues, until the number of 1s of the merged TVM is equal to the desired length of the parallel chain (PCL). From the TVM that has the number of 1s equal to the desired length of the parallel scan chain we determine which inputs of the DUT should be included in the parallel scan chain. We also need to generate disjoint TVMs that form the individual parallel scan chains. For the purpose of that, we maintain a set of positions, that are not yet included in the already generated TVMs that form the parallel scan chains. We call this set the valid positions set. The heuristic algorithms ignore the TVMs longer than the parallel scan chain, because the test vectors covered by these long TVMs could never fit into a single parallel chain. We present four heuristic algorithms, named H1, H2, H3 and H4 in this dissertation thesis. These heuristics share the same general algorithm structure and they differ in criteria for the selecting the TVMs for merging. Heuristic H1 selects the TVM that covers the maximum number of test vectors as the best. The selected best TVM is merged with the other TVM according to a criterion, that these two TVMs differ in the minimum of 1s. Heuristic H2 selects the best TVM the same way as H1 does. Then the selected TVM is merged with the other TVM according to a criterion, that the number of TVs which the merged TVM covers divided by the number of 1s they differ in is maximal. Heuristic H3 selects the TVM that has the number of 1s in the TVM multiplied by the number of test vectors that the TVM covers maximum. The selected TVM is then merged with the other TVM according to a criterion, that the number of TVs which the merged TVM covers divided by the number of 1s in merged TVM is the maximum. Heuristic H4 selects the best TVM according to a criterion that the number of test vectors covered by the TVM divided by number of 1s of TVM is the maximum. The selected TVM is then merged with the other TVM according to the same criterion, as H3. 29

42 3. Overview of Our Approach Benchmark circuits We present our preliminary results on several ITC 99 benchmark circuits [63]. We presume the full scan chain in these circuits, so we have used the combinatorial parts of these benchmark circuits. The ATPG tool Atalanta [66] was used for the test vector set generation. The ATPG tool was set to generate one pattern for each fault and to generate test set with partially specified test vectors as alluded to Table 3.1. This shows the characteristics of the generated test sets. The column #Gates represents the number of gates in the benchmark circuit, taken from [63]. The column #Inputs is the number of inputs of the combinatorial benchmark circuits. This means the number of scan cells in the scan chain. The column captioned #TV shows the number of test vectors generated by the ATPG. This is equal to the count of detected faults. The column avg#cb denotes the arithmetic mean of the care bits in a test vector. The column avgcb is the ratio of care bits in the test vector set. Table 3.1: Benchmark circuits and test vector set properties Benchmark #GATES #PI #TV avg#cb avgc b05_opt_c % b06_opt_c % b07_opt_c % b08_opt_c % b09_opt_c % b10_opt_c % b11_opt_c % b12_opt_c % b13_opt_c % b14_opt_c % b15_opt_c % b17_opt_c % b20_opt_c % b21_opt_c % b22_opt_c % Scan Chain Configuration Method I. Results The results of the proposed heuristic algorithms are shown in Table 3.2. The column heading PCL is an abbreviation that stands for the parallel chain length. The column PC is the number of the parallel chains the scan chain is partitioned into. The columns labeled H1, H2, H3 and H4 are the results of the heuristic algorithms. The values in these columns are the test vector broadcast rates. Because of we are not dealing with 30

43 3.2. Scan Chain Configuration Table 3.2: Scan Chain Configuration Method I.: Broadcast rate Benchmark PCL #PC H1 H2 H3 H4 RND Max Improvement b05_opt_c % 69% 71% 68% 46% 71% 1.54 b06_opt_c % 96% 97% 97% 75% 97% 1.29 b07_opt_c % 57% 58% 57% 51% 58% 1.14 b08_opt_c % 64% 64% 60% 56% 64% 1.14 b09_opt_c % 80% 80% 80% 74% 80% 1.08 b10_opt_c % 61% 62% 59% 51% 62% 1.22 b11_opt_c % 52% 51% 43% 45% 52% 1.16 b12_opt_c % 72% 72% 73% 54% 73% 1.35 b13_opt_c % 88% 88% 85% 79% 88% 1.11 b14_opt_c % 31% 31% 31% 25% 31% 1.24 b15_opt_c % 47% 45% 42% 38% 47% 1.24 b17_opt_c % 62% 67% 62% 54% 67% 1.24 b20_opt_c % 33% 33% 38% 30% 38% 1.27 b21_opt_c % 32% 32% 33% 28% 33% 1.18 b22_opt_c % 45% 46% 45% 34% 46% 1.35 precise scan cells order, we performed 100 simulations when the scan cells order inside the parallel chains was randomized and we took the arithmetic mean value. The column RND means how many test vectors in a test vector set can be broadcasted in a scan chain configuration that is a product of a random assignment. For the random assignment we performed 1000 simulations and we took the arithmetic mean value. The column Max is the maximum from heuristic algorithms. Improvement is the ratio between the best results received from our heuristic and the random assignment. It is the value in the column Max divided by the value in the column RND. Furthermore, we performed experiments where the count of parallel chains was variable. Results for benchmark b22_opt_c are shown in Figure 3.5. Our experimental results show that it is possible to improve the test vector set broadcast rate for the presented architecture by an average factor of 1.24 against a random assignment by utilizing the heuristic algorithms described Scan Chain Configuration Method II. The scan chain configuration method in Section tries to fit all specified bits of a group of vectors into single parallel scan chain, thus avoiding structural dependences. However, it does not count with different values of specified bits in test vectors and with bit conflicts amongst other vectors. Therefore we have developed another more precise scan chain configuration method [A.3]. The fundamental difference between the method described in Section and method presented in this section is that the this one does not try to fit all bits in single parallel 31

44 3. Overview of Our Approach Figure 3.5: Broadcast rate with the respect to the count of the parallel chains for the benchmark b22_opt_c scan chain and hope that there will be no subsequent conflict, but it deterministically searches for all possible positions in scan chain to find the one with least possible bit conflict count. The algorithm precisely analyzes all test data, differentiating unspecified bits, logical ones and logical zeros, in order to build so called dependency chains from those scan cells, which will result in least possible amount of bit conflicts. The dependency chain is a group of scan cells, which are dependent on each other because of structural dependency. Elimination of bit conflicts in dependency chains results in smaller amount of necessary clock holds and thus to the better compression. The dependency chains are built from the longest to the shortest, because the creation of large chain of non-conflicting bits is more difficult. The structural dependences and built dependency chains inflict restrictions on layout aware scan cell reordering. As mentioned previously, according to [64, 65] scan cell reordering without optimizations for routing could lead to an unroutable design or a design with a serious area overhead or performance degradation due to long wires between the scan cells. It is still accomplishable to perform layout aware optimization, because it is possible to freely swap scan cells within any given dependency chain and it is also possible to swap whole dependency chains, as long as they have the same length. 32

45 3.2. Scan Chain Configuration Scan Chain Configuration Method II. Results Our experimental results of this method are shown in Table 3.3. They were performed on the same benchmark circuits shown in Table 3.1 and described in Section In the two parts of the table we compare algorithm efficiency obtained by heuristics described in Section and the new algorithm proposed in this section. The column heading Vectors OK is the broadcast rate, the resulting numbers of vectors for the given method that can be shifted into the broadcast scheme shown in Figure 3.1 without stopping the Clk clock. Column Bits in conflict gives the number of bits within the whole test that cannot be fed into the broadcasting scheme without stopping the Clk signal for both methods. The rest of columns give comparison with the heuristic method of scan chain configuration. For the column OK vector ratio the higher value means the better result, as more vectors are able to overlap without clock hold. For the values in the last column comparing bit conflicts in given two methods the lower value means the better result, because each bit conflict has to be solved by clock hold. Average improvement of the number of non-conflicting vectors and the average reduction of the conflicting bits for all exercised benchmark circuits are given in the last row of the table. The experiments show that the proper scan chain configuration can save substantial part of test time spent on breaking the pattern broadcasting by stopping of the circuits parallel chains. The performed experiments demonstrate that it is possible to configure the parallel scan chains for vector broadcasting and overlapping for relatively large circuits (<250K gates). The number of conflicting bits is after scan chain optimization so low that it leads to shorter testing time for the given test compression method. 33

46 3. Overview of Our Approach Table 3.3: Scan Chain Configuration Method II.: Broadcast rate SC configuration method I. SC configuration method II. Comparison Benchmark #VC Vectors OK Conflict bits Vectors OK Vectors OK Conflict bits Vectors OK OK ratio Conflict bits b % % 1.03x 58.0% b % % 1.00x 100.0% b % % 1.34x 16.5% b % % 1.18x 25.2% b % % 1.04x 38.2% b % % 1.17x 27.3% b % % 1.36x 22.4% b % % 1.22x 16.7% b % % 1.05x 0.0% b % % 1.81x 20.4% b % % 1.67x 11.2% b % % 1.42x 0.8% b % % 2.23x 10.6% b % % 2.20x 14.6% b % % 1.82x 10.1% Average improvement 1.44x 24.8% 34

47 3.3. Compression Algorithm 3.3 Compression Algorithm As mentioned previously, the proposed test compression algorithm [A.4] is based on pattern overlapping. It is designed to work with traditional ATPG. The only required feature of the ATPG is the ability to generate for each detectable fault one test vector with don t care values. Scan-cell arrangement in decompression hardware heavily affects the amount of test vectors suitable for broadcasting. The scan-cells are reordered according to the test set, so the maximal amount of test vectors can be decompressed on the proposed on-chip test decompression hardware according to broadcast schemes described in Figure 3.2. The decompression hardware optimization algorithm is briefly described in Section 3.2. The basic compression algorithm structure is denoted in Figure 3.6. In the beginning, the algorithm translates test vectors generated by the ATPG into decompressor seeds. The seeds are sequences of ones, zeros and don t care values that after shifting into decompressor have the same fault coverage as the original test vectors. Naturally, only patterns suitable for broadcasting according to currently used broadcast scheme are translated. Next, the algorithm initializes the startup scan chain configuration. These can be values after reset or a previous state of the scan chain. After this is done, the algorithm searches for a decompressor seed, that maximally overlaps with current scan-chain content. When the best seed is found, seed values are added to the compressed result and fault simulation is performed. Covered faults are removed from the fault list. This is necessary hence one test vector usually covers more than one fault. This scenario repeats in a loop until there any faults left in the fault list or all of the test patterns suitable for broadcasting with currently used broadcast scheme are used. As mention previously, the algorithm operates with faults, that have test cubes suitable for broadcasting. Some of the faults that have test vectors unsuitable for broadcasting are covered by broadcasting vectors without dependences, but not all of them. To cover the same fault set as the test set generated by ATPG, we use pattern compaction method on the patterns of uncovered faults. These compacted test patterns are used by the decompressor architecture by utilizing clock gating of parallel chains. The control of clock holds can be managed by simple counter. In early stages of our research, we have experimented with different approach when dealing with test cubes unsuitable for broadcasting. Instead of having highly compressed test set applicable effectively by broadcasting and a set of compacted test vector, we presumed two data streams simultaneously shifted from the ATE to the decompressor. One stream of decompressor data and the other stream of clock holds. As mentioned previously, any ATPG generated test pattern can by applied to the DUT using proposed decompressor scheme utilizing clock gating. The method publicized in [A.2] exploits this. The test compression algorithm of this approach firstly translates all ATPG generated test patterns to decompressor s data and clock sequences and then finds best overlapping of both sequences. We have abandoned this approach, hence it did not show very promising results. 35

48 3. Overview of Our Approach BEGIN Translate test patterns into seeds, load fault list FAULT LIST Initialize startup scanchain configuration Find decopmressor seed that overlaps at best with current scan-chain configuration YES Perform fault simulation, remove detected faults and their patterns from the fault list FAULT LIST Are there any faults left? NO END 36 Figure 3.6: General structure of the pattern overlapping compression algorithm

49 3.3. Compression Algorithm Test Application Time and Compression Effectiveness Results In this section, we evaluate the proposed decompression scheme and compression algorithm. Our experiment results are shown in Table 3.4. In this table we compare test application time by comparing clock ticks. The table is divided into two parts. The first part named COMPAS represents results obtained by COMPAS [4]. The column labeled Bits is the amount of compressed test data in bits. The column labeled Clk is the amount of clock ticks necessary for test decompression and application using RESPIN. The second part of the table labeled Compas with broadcasting represents the results obtained by the new tool B-COMPAS presented in this dissertation thesis that employs broadcasting. The benchmark circuits are described in Section The column heading PCL is an abbreviation that stands for the parallel chain length. The column #PC is the number of the parallel chains the original scan chain is segmented. The column labeled Brate is the broadcast rate of the test vector set. This means the number of test vectors that are decompressed using the decompressor architecture without clock holds. The column Bits under heading Vectors without dependences represents the length of compressed test stream of test vectors without dependences. The test stream generation for the largest benchmark circuit took less than ten minutes on a computer with AMD Opteron processor. The column labeled Clk is the amount clock ticks necessary for test decompression and application using decompressor architecture. The column labeled Undetected is the amount faults, that are not detected by the compressed test sequence using pattern overlapping and broadcasting. Column labeled TV is the amount of compacted test vectors that detect the undetected faults. These vector were generated by Atalanta [66]. The column labeled Bits is total amount of data that the compacted test vectors will occupy in memory of the ATE. The amount of clock ticks, that are necessary for application of compacted test vectors is the same as the amount of bits they occupy in memory. The column labeled Total Clk is the total amount of clock ticks necessary for decompression and application of compressed test vectors without dependences and compacted test vectors. The last column is the speedup factor of the test application time by the new method presented int this paper compared to COMPAS. From the experimental results we can see, that there is a trade-off between the test data volume and test application time by utilizing presented method. The reduction of the test application time led to increase in the data volume. However, the increased data volume mostly consists of compacted test vectors that cover only a small fragment of faults. The overlapped test vectors that are suitable for broadcasting cover most of the faults and occupy only negligible part of tester memory. From this we can presume, that the future research of this method should focus on finding different method than pattern compaction for covering faults undetected by overlapped test vectors. These experiments demonstrate that it is possible to significantly reduce test application time by utilizing test pattern overlapping and broadcasting. It is however at the expense of slight increase in the test data volume compared to the test application speedup. We have reduced the test application time by an average factor of 49 by an increase in test data volume by an average factor of 8 on larger benchmark circuits compared to COMPAS. 37

50 3. Overview of Our Approach Table 3.4: B-COMPAS: Test application time and compression effectiveness comparison Benchmark Compas Compas with broadcasting Speedup Bits Clk PCL #PC Brate Vectors without dependences Compacted vectors Total Clk Bits Clk Undetcted TV Bits b05_opt_c % b06_opt_c % b07_opt_c % b08_opt_c % b09_opt_c % b10_opt_c % b11_opt_c % b12_opt_c % b13_opt_c % b14_opt_c % b15_opt_c % b17_opt_c % b20_opt_c % b21_opt_c % b22_opt_c %

51 3.4. Hardware Overhead 3.4 Hardware Overhead In this section we compare proposed test compression scheme with state-of-the-art commercial tool. For purpose of that, we have developed a complete built-in test equipment [A.5], which includes scan chains, master shift register, signature register and a control automaton (Figure 3.7). This on-chip test equipment enables running test, reading signature Broadcast Test System Broadcast Controller Finite State Machine Decompressor Setup Reset Test Bypass CUT wrapper Scan chains CUT Preset SHreg Shift Counter Feedback Counter MISR Figure 3.7: Built-in test equipment Tdi New bit Tclk and writing or reading scan chain values independently on external hardware. The embedded test equipment is controlled via five control signals: Tclk, Tms, Tdi, Tdo and 1 Tse, 2 where 3 4the Tclk 5 is the1 primary 2 test 3 clock 4 and 5 the Tdi and Tdo signals are test data input and output respectively. The Tdi and the remaining signals are used to switch between different operating modes of the circuit: The functional mode is enabled by setting the Tse input low. In this mode, the clock Broadcast decompressor network of the CUT is driven from the circuit pin, on the contrary to the remaining test modes, where the clock signal is gated using internally generated signals The test-setup modedff is used to setup DFF the period DFF of parallel DFF scan chain DFFclock gating, or to reset the test CUT Parallel Chains

52 3. Overview of Our Approach The test-bypass mode allows users to bypass embedded test equipment and access parallel scan chains directly. In this mode parallel scan chains act as single scan chain. Since there are no multiplexers in the test equipment design, the bit sequences of test patterns and captured responses must be appropriately reordered. In the test mode the embedded test equipment in cooperation with external tester is used to decompress test patterns using settings preset in the test-setup mode. The decompression scheme was explained earlier in the text above. The Broadcast test system (Figure 3.7) was experimentally evaluated with benchmark circuits from the ITC 99 [63] benchmark set. Internally developed tools were used to insert parallel scan chains into benchmark circuits and to create built-in test circuitry. The area overhead of scan chains and embedded test equipment was measured as well as the time required for test. The broadcast test pattern decompression scheme was compared with a reference tool that uses an LFSR for test pattern decompression. This tool was set up to create a system similar to the proposed one. Settings were following: The number of parallel scan chains was set to the same as for the broadcast system, but the order of the scan cells was left up to the tool s decision. XOR tree response compaction was enabled by default as well as the option to bypass the built-in test circuitry. Remaining settings were left to their default values. All circuits were synthesized using AMS370 library in the Design Vision synthesis tool using default settings. The results of the experiments are shown in the Table 3.5. The measured area overhead was normalized to the size of the target benchmark circuit, thus the obtained results are displayed without units. Comparison between reference and broadcast results are also shown in the graph in Figure 3.8. The columns denoted as bcast refer to broadcast results and those marked ref refer to reference tool s result. It can be shown that in all of the cases the both methods offers comparable results in terms of hardware overhead. The test application time and tester memory requirements are also compared with the reference tool in the Table 3.6. The test time is evaluated in form of clock cycles that are necessary for the test application. The rows denoted as uncovered faults refer to amount of faults the test does not cover due to structural dependencies in the parallel chains. The Broadcast test system offers a testing mode in which all parallel scan chains act as a single long scan chain without any structural dependencies. By using this mode at the end of test procedure we can cover remaining undetected faults at the expense of longer test time and larger memory requirements. We have performed experiments on several ITC 99 benchmark circuits and compared hardware overhead, test application time and tester memory requirements of presented method with commercial tool. We have shown that the proposed method can offer similar results. 40

53 normalized area overhead 3.4. Hardware Overhead 600% 500% 400% 300% 200% 100% 0% ref b01 bcast b01 ref b02 bcast b02 Decompressor overhead original circuit scan overhead controller overhead ref b03 bcast b03 ref b04 bcast b04 ref b05 bcast b05 ref b06 bcast b06 decompress method & circuit ref b07 bcast b07 ref b08 bcast b08 Figure 3.8: Decompressor hardware overhead comparison ref b09 bcast b09 ref b10 bcast b10 41