Digital Video Encoder/decoder System. FPGAs give product a new lease of life

Transcription

1 Digital Video Encoder/decoder System FPGAs give product a new lease of life AE: - Number: TTN: - Abstract Mr. Norman Stock Technology Transfer Centre, Bournemouth University, Poole House, Talbot Campus, Fern Barrow, Poole, Dorset, BH125BB HDTV Ltd a company, located in Wokingham in England, with 6 employees and with a turnover of 290k, designs and manufactures innovative video products for the professional video and television broadcast markets (Prodcom Code 3230), in particular TV studios. Historically the majority of HDTV products have been designed utilising analogue circuit technology, together with some discrete logic and microcontrollers. However, the market place is now changing, demanding that new technology be employed utilising digital technology. The general range of products the market demands remains the same; the difference is the utilisation of digital technology. The product range includes distribution amplifiers, encoders and decoders, genlocking equipment, pulse generators, signal correctors and Time Code to RS232 converters. Within this range of products is an analogue video encoder and decoder system. These products convert baseband analogue video (luminance and colour difference) to composite video and back to baseband. This product has a high technical specification, and a high unit cost. There is a lot of demand in the market at the moment for a digital version of this system. The entire system can be broken down into a series of subsystems. Some of these subsystems HDTV have the ability to design and manufacture at the moment, however there is some digital technology namely FPGAs, that HDTV has no experience of using. It is this technology that the FUSE project concentrated on utilising. By adopting FPGA technology into the company, the resultant encoder/decoder will recapture the market that had been lost and also a range of new digital products can be now developed. The advantages of utilising FPGA technology are numerous. These Page 1AKTUALDATSEITEAKTUALDAT

2 include, tolerance free realisation of required filters, improved product reliability due to decrease component count and lack of dependence on component tolerances, reduced temperature drift, and also a reduction in the number of tests that have to be carried out before a product can be shipped. The presence of the video signal in digital form also enables the user to implement special effects on the signal should this be required. These attributes have been demonstrated by the produc tion of a prototype FPGA filter. The company can now develop the encoder / decoder product that will enable them to recapture their market share, and also use the acquired technology to develop a complete range of digital video products. Without the ability to realise both of these goals it is difficult to envisage the long term future of the company. The project commenced 1 st February 1997 and ended on 30 th April The total cost for the project was 48K and the Return on Investment has been estimated to be 1450% whilst the payback period is expected to be 29 months. Keywords FPGA, Video conversion, DSP, Digital Filtering, Analogue Encoder, Analogue Decoder, television, broadcast Signature UK 1. Company name and address H.D.T.V Ltd. Unit A4, Grovelands Ave., Winnersh, Wokingham, Berkshire, RG41 5LB Tel: Fax: HDTV_ltd@compuserve.com Page 2AKTUALDATSEITEAKTUALDAT

3 1.1 Contact Mr. Mike Hancock (Managing Director) 2. Company Size The company currently has six employees, three of which are engineering personal, and who s collective expertise covers a wide range of electronic disciplines. Mike Hancock, Managing Director of HDTV Ltd, has twenty-eight years experience in analogue and digital video gained from working with a variety of broadcast companies. Peter Greatorex, the newest member to HDTV has many years experience working in the field of RF design for both systems and PCBs. All of HDTV s prototype manufacturing is carried out in-house by our own very skilled wire-man Mark Giles. Capable of manufacture with through-hole and surface-mount technology for a range of standard and custom made racks. In the year ending 1998, HDTV's turnover was 290k. 3. Company Business Description HDTV Ltd. is a private company that has been designing and manufacturing equipment for broadcast television studios since Our experience has been with state of the art analogue designs, which we sell into the low volume, high cost, high reliability and high quality, broadcast market. We fully understand all the subtleties of the analogue video signal, which requires RF techniques to optimise performance and also the use of discrete logic as well as microcontroller technology. Our existing design activities encompass all the disciplines required to turn an idea into an electronic product, for example Computer Added Design (CAD) of printed circuit boards using plated through hole and surface mount hardware, production assembly and testing (using our comprehensive analogue video test facilities). Our current product range includes video and audio distribution amplifiers of varying flavours, in standard 3U frames, as well as an extensive line of portable equivalents. Our range of non-distribution products include - analogue encoders and decoders, genlocking equipment, PAL signal pulse generators, a composite video signal corrector with remote control option and longitudinal TC to RS232 converters for allowing time codes to be fed to a computer system. HDTV sells it s standard product line directly and also through agents. There are currently six agents selling HDTV s products in Europe. The U.K. agent is DT Electronics, others are based in Holland, Germany, Finland, Italy and Spain. HDTV also Page 3AKTUALDATSEITEAKTUALDAT

4 has an agent in Australia, while the British agent also covers the Middle East. There is also a separate agent working in Kuala Lumpa. As well as a line of standard products, HDTV has undertaken many systems jobs that include the design and installation of broadcast quality studios, reproduction and editing suites. All products and installations are fully supported by the technical staff at HDTV, for upgrades and maintenance. Predominantly it operates therefore within Prodcom Code Sound and Image. 4. Company markets and competitive position at start of programme The equipment that HDTV design and manufacture is low volume, high quality products for the professional video and broadcast markets and is designed to either operate under the appropriate local standard (PAL, SECAM, NTSC) or, where feasible to be dual standard. The equipment all has to be of a very high standard of design and manufacture. The market will not tolerate equipment that is prone to failure, or does not meet the required international standard. The products sold are mostly for television studio applications. At the present we sell an analogue decoder/encoder packages into two niche market areas: - 1. As a stand-alone product within our current product list. Because of the relative high cost of production and performance fixed by the use of older technology in the existing decoder/encoder, sales in the medium term are gradually reducing, pending the arrival of a more cost effective, high performance product. Our initial investigation demonstrated to us that the plan to introduce our new Digital Decoder/Encoder would immediately place us back in a growth situation. The Decoder/Encoder path also enables a number of spin-off products like a Decoder serialises, an Encoder de-serialiser, etc. and other new products utilising the FPGA nucleus. Therefore the ultimate projected sales will not only depend on the new digital Decoder/Encoder but sales will also increase thanks to the new family of products. 2. As an OEM product within the video system of a major US manufacturer selling world-wide our product in their systems. Again we have had difficulty maintaining sales because of manufacturing costs and older technology performance. Leading companies that manufacture competitive products both in Japan and the USA are already incorporating the new Digital Video technology within their new products. The application of the latest FPGA technology will enable us to compete directly and in our niche areas. This will allow HDTV to improve on the performance of competitors products. We will be using the very latest advances in FPGA design and technology which will allow us to achieve a better performance to Page 4AKTUALDATSEITEAKTUALDAT

5 cost ratio. These developments will induce confidence in our customers, by underlining our commitment to invest in new technology. The original Decoder/Encoder Product was introduced in 1989 and steadily increased in sales until 1995, after which sales began to drop sharply, see figure Sales Revenue in 1000 ECU's Sales revenue in 1000 ECU's Year in which product was sold Figure 1 - Sales revenue of existing analogue decoder/encoder product We are an OEM supplier to our main American customer for the existing analogue Decoder/Encoder product (this customer markets HDTV's decoder/encoder over Europe, Africa and the Middle East). During 1994 and 1995 HDTV's decoder/encoder had a market share of 28% of a European, African and the Middle Eastern market which increased from 621k to 821k, 90% of which was through this main customer. This dropped to a quarter of that figure over 1996 due to digital products emerging onto the market. The innovation was therefore required in order to transform this 7% market share back to the 28% previously enjoyed. However this market share is not lost as our main American customer for the analogue decoder/encoder also purchases other products in our range and has shown very strong interest in the proposed Digital decoder/encoder product which they propose to sell as a replacement for our existing analogue system, allowing HDTV to regain its market share of 28%, after the completion of the new digital encoder/decoder range. Page 5AKTUALDATSEITEAKTUALDAT

6 600 Sales revenue in 1000 ECU's Development cost for new Digital Decoder/Encoder Return on investment as a percentage of the new digital Decoder/Encoder sales revenue Projected sales revenue of new digital Decoder/Encoder Spin-off sales for future product utilising FPGA technology Year in which product is to be sold Figure 2- Projected sales revenue of new digital decoder/encoder showing return on investment on a year by year basis of the new product and spin-off sales from future development. Figure 2 shows the proposed sales revenue expected for the new digital decoder/encoder, which would be introduced at the end of Also shown are the development costs for the project and the projected sales revenue of future products utilising the FPGA technology and experience gained from the decoder/encoder experiment. With the introduction of the new digital decoder/encoder HDTV is planning to break into the American market which is now largely dominated by digital video broadcast products as opposed to analogue. The digital decoder/encoder experiment will allow us to design future digital video products that would be attractive to the American broadcast market, as well as increase our competitiveness in the rest of the world-wide market. Figure 2 also shows the development costs associated directly incurred during the experiment (not development of future products) and it can be seen from the projected sales of the new product that a return on investment will be recovered in a short space of time after the completion of the experiment. The projected sales expected from the development of new products will rapidly be made possible from the results of the experiment. The experiment will allow a cost benefit to be applied to future products and existing Page 6AKTUALDATSEITEAKTUALDAT

7 products to be improved, in that board size and complexity will be reduced, hence cost, less components will be needed since many design functions will be incorporated in the FPGA reducing labour costs and performance and reliability will increase synonymous with integrated technology - increasing our competitiveness on quality. Some of the market leaders in broadcast quality video products include companies such as Leitch, Snell &Willcocks, and Tekniche. All of these companies manufacture digital video products that utilise programmable logic. These companies were some of the first in the video market to use programmable logic as a solution to digital video products. 25% 40% Manafacturing Costs Overhead Overseas Agent Profit 25% 10% Figure 3 Analogue encoder/decoder costs and margins. The current price of HDTV analogue decoder is 2170 list price. A breakdown of the costs and margins is shown in Figure 3. HDTV normally bases its prices on a 50% margin. This is though, influenced by the cost of competing products. If competing products are sold at a much higher cost then the HDTV pricing will fall just below the competition. The main weakness of the current analogue encoder/decoder products is the diminishing market place. As the market for analogue encoder and decoder disappears, so the urgency for HDTV to develop a new range of digital products grew. The other weakness of the current product is the high manufacturing costs. This high cost is due to ageing technology and expensive parts that are becoming obsolete. The original strength of the encoder/decoder product line was it's cost. The cost of development, parts and manufacture meant that the products could be sold for less than the competitors. Now the competitors are able to sell newer digital products for less than Page 7AKTUALDATSEITEAKTUALDAT

8 the older analogue products. They can do this by reducing their costs in manufacturing. In figure 4 the price break down of the new digital encoder/decoder system can be seen. Programmable logic in the form of both complex programmable logic devices (CPLD) and field programmable gate arrays (FPGA), is still a moderately young area of electronics, the technology has existed for around ten years. For a number of these years companies such as Xilinx and Altera had a complete hold on the programmable logic market, with devices that were very small in terms of gate count and very slow in terms of system clock performance, in comparison with today s million gate count, 200MHz devices. Further more, there are now a range of companies competing on the programmable logic market, with devices boasting better performance or lower cost than the market leaders. The growth of the programmable logic market looks set to expand even further with time-to-market being cut with the aid of push button software from the EDA companies. The leading chip manufactures are claiming that systems-on-aprogrammable-chip will become a reality with the next release of silicon. 25% 40% 10% Manafacturing Costs Overhead Overseas Agent Profit 25% Figure 4 Digital decoder/encoder costs and margins With so much competition in the programmable logic market at the moment, companies are being forced to give away software and place and route tools for free, in an attempt to get companies to use their silicon. This level of competition puts HDTV in a very good position for using programmable logic for the first time. There are now many companies to choose from and many software solutions available. Furthermore the technology is now far superior, and far more reasonably priced, in a market that is maturing very quickly. Page 8AKTUALDATSEITEAKTUALDAT

9 5. Product to be improved and its industrial sector 5.1 Background The product that was the subject of this project is used in the television industry, where there is a need to convert the signals from the format which they are produced in (for example by a camera), into one in which they can be processed. The products may be used in a TV studio itself or in studio where programme editing takes place. 5.2 Current Analogue Encoder/Decoder system The majority of signal sources (studio cameras or outside broadcast cameras) provide a composite video signal i.e. a single signal that has all the required colour, brightness, luminance etc. information encoded within it. However within the studio this signal is not suitable for distribution or for processing (e.g. to increase the luminance or change the relative colour levels) because of the degradation that would inevitably occur. It is therefore necessary to decode the composite video signal into it's constituent parts and to be able to make these signals available for distribution and processing. Prior to transmission, however, the signals must be recombined into the composite video signal. The decoder/encoder performs these functions and is therefore a vital piece of equipment in any professional studio. The decoder/encoder product that HDTV currently manufactures is a system that utilises analogue technology for signal processing and signal conditioning. A block diagram for the system can be seen in figure 3. The PAL or NTSC Composite Video signal is transformed into a baseband YUV or RGBS signal by the decoding process, externally conditioned before returning to Composite form by the Encoder process. Composite Input and Clamp Y/C Seperation Process Y Delay Colour Decode Processor Output and Clamp Y U V Studio Environment Y U V Decoder Y Delay Y Y Input Studio Environment U V U V Clamp Matrix Colour Modulators Pulse Processor + Output Amplifier Composite Video Encoder Figure 5 Existing analogue encoder/decoder system The Composite Video signal enters the decoder and the input amplifier conditions the dc component and gain. The signal then passes through complex analogue filtering Page 9AKTUALDATSEITEAKTUALDAT

10 processes, which separates the luminance or Y channel, which has bandwidth of 5MHz, with the colour signal located within the luminance bandwidth at 4.43MHz. Simple notch filtering in the Y channel or complex comb filtering can accomplish this separation. After further analogue filtering and delay timing adjustments to recover time delays in the Y channel, the YUV or RGBS signal is output. Conversely, after signal manipulation the YUV or RGBS signal is encoded back to composite. The encoder utilises analogue transistor technology and 4000 series logic to produce high quality analogue video. This product has a high level of analogue circuit complexity that delivers a high quality video signal, however the market is now moving increasingly to the use of digital technology. This is most prominent in the area of digital signal processing for filtering purposes. Figure 6 - Existing product (from top to bottom - Genlock Board, Encoder, Decoder There are numerous advantages for converting the technology from analogue to digital. There will not be any changes in the parameters (i.e. the filter characteristics and the specifications for the various signals) which are pre-defined by the governing standards body. However there will be a number of improvements to the system which make the digital unit more attractive to the user. These included improved reliability, improved performance (in terms of stability and consistency), lower unit cost, improved maintainability, more simplified testability, but more importantly than any of these is the benefit of continued sales within the marketplace. The older technology is starting to become redundant and will shortly be phased out. HDTV needs to develop its product range if it is to remain active within the video market place, and without the introduction of digital technology the future of HDTV looked extremely uncertain. Most of the Page 10AKTUALDATSEITEAKTUALDAT

11 specifications for the new system have been defined by the international standards organisation the ITU and the CCIR. These standards have been put together after many detailed studies into possible conversion techniques for digital video. 5.3 Summary The driving force behind the innovation was the need to recapture the lost market share, which had plummeted from 28% to 7%. The market demand was for a digital product that met the standard of performance as laid down in the industry standard specification. This market therefore could only be recaptured if the product operated in the digital domain - no amount of price reduction would have produced the necessary sales. 6. Description of the technical improvements 6.1 Digital Encoder/Decoder system As previously discussed, the actual functionality and specification of the improved product is identical to that of the original. It is the implementation of that function which is different and which, in turn, provides the benefits to the user. The user is now provided with a more accurate and stable set of signals, and is able to perform far more operations on the signals using the "Studio Equipment" shown in the diagram below. Composite Decoder Y U V Analogue to Digital Converter Digital Filtering Parallel to serial converter Serial Output Studio Environment FPGA Studio Environment Serial Input serial to Parallel converter Digital Filtering Digital to Analogue Converter Y U V Encoder Composite Out FPGA Figure SEQARABISCH7 Digital encoder/decoder system. The digital decoder/encoder seen in figure 7 is to have Y, U and V digital inputs and outputs of 10 bit parallel data. The serialising system is to comply with the 4:4:4 and 4:2:2 standards (Rec. ITU-R BT.656-3). Note: 4:4:4 and 4:2:2 is a ratio of sampling frequencies used to digitise the Y (luminance) and U, V (colour difference) components of the YUV signal. The sample rate for Y is to be 13.5MHz (this corresponds to four times the colour subcarrier frequency). The sample rates for U and V are to be 13.5MHz or 6.75MHz (this corresponds to two times the colour sub-carrier frequency) depending on the format used (4:4:4/4:2:2). The filtering will be band-limited to a cut off frequency of 13.5Mhz in Page 11AKTUALDATSEITEAKTUALDAT

12 accordance with Rec. ITU-R BT Digital Decoder path specification Inputs of the component designed under FUSE: Y, U and V: 10 bits parallel data. Sample-rate for Y is 13.5MHz, sample rates for U and V are 13.5MHz or 6.75MHz depending on the format used (4:4:4 or 4:2:2) System clock from which 13.5MHz is derived, locked to the Y signal. Outputs of the component designed: Parallel data in 10 Bit words prepared to be serialised with all relevant time codes (i.e. EAV and SAV). Clock and control of the serialising system. The components designed consist of two subsystems: Filtering subsystem: The function of the digital processing filtering subsystem is to band-limit the sampled digital video information with a cut off frequency of 13.5Mhz, thus allowing a relaxed specification for the costly analogue filters. It implies oversampling of the incoming signal, phase linear digital filtering and a sample rate conversion before conditioning takes place. Choice of filtering techniques was one of the issues developed in the Fuse programme. Conditioning subsystem: The function of the conditioning subsystem is to prepare the three parallel filtered digital signals for serialisation. This involves the formation of 10 Bit words necessary for the serialising system to comply with the 4:4:4 and 4:2:2 standards. The 10 Bit words are a combination of video data (Y, U and V filtered), video timing, status, control, clocks, etc, all multiplexed into one 10-bit digital bit stream. 6.3 Digital Encoder path specification Inputs of the component designed under FUSE: Parallel data in 10 Bit words. Control of the de-serialising system. System's clock locked to the incoming serial signal. Outputs of the component designed: Y, U and V: 10 bits parallel data. Clock for the DACs Page 12AKTUALDATSEITEAKTUALDAT

13 The component designed consists of two subsystems: Deconditioning subsystem: The function of the deconditioning subsystem is to extract the parallel video data out of the 10 Bit words received from the de-serialising system. Filtering subsystem: The function of the digital processing filtering subsystem is to prepare the digital video for the Digital to Analogue converter in order to remove frequency components over 13.5Mhz. 6.4 Detailed study of the filter requirements for Encoder and Decoder The filter parameters are defined in the Rec. ITU-R BT.601 (formally CCIR 601) video specification. The specification for the filtering in the luminance path (Y) is as follows: - Pass band ripple: dB End of pass band: MHz -12 db point: MHz Stop band start: - 8MHz Stop band rejection: db The specification for the filtering of the colour difference (U and V) signals is as follows: - Pass band ripple: db End of pass band: MHz -6 db point: MHz Stop band start: - 4MHz Stop band rejection: - -40dB It is possible to meet these filter parameters using custom analogue filter such as the Faraday 601F0575. However the cost for such devices is approximately 50 for one off. As three are needed in each decoder/encoder system, one for each of the three input signals, then this cost is approximately 150. The total cost for the system needs to be around to remain competitive (see Competitive Product Analysis attachment 1). Page 13AKTUALDATSEITEAKTUALDAT

14 Because of the high price for the analogue filters an investigation into a cheaper digital filter alternative was employed. Intensive training for the FUSE team member was carried out at Bournemouth University over a period of three days as an introduction to the subject of digital signal processing. At the end of the course a detailed study of possible implementation techniques was carried out as an educational case study. The two possible design methods that were investigated for a solution to the luminance filtering where, one full band FIR filter or, two half band FIR filters cascaded. Matlab code was developed at the University to generate a graphical user interface that would allow for FIR filter design iterations that could be easily analysed and tested. There are two user interfaces one for each of the methods employed Single FIR filter A user interface was developed to experiment with various different FIR filter parameters in order to evaluate their usefulness.. The user interface would allow the following FIR filter parameters to be changed: - Windowing Function, either: - Bartlett, Boxcar, Hamming, Hanning and Kaiser Number of Taps (MAC units): - 1 to <1000 Beta Value: - Value used to define the shape of the Kaiser window Coefficient width: - Matlab uses floating-point binary with very high precision. To create a more realistic model a floating point to fixed point number conversion is employed. The generated coefficients can be seen in figure 8. Page 14AKTUALDATSEITEAKTUALDAT

15 Figure SEQARABISCH8 Generated Coefficients Page 15AKTUALDATSEITEAKTUALDAT

16 The expected frequency response using floating point representation of data and coefficients can be seen in figure 9. Pass Band Ripple -12 db Point SEQARABISCH Figure SEQARABISCH9 Frequency response of digital FIR filter using floating-point binary. Page 16AKTUALDATSEITEAKTUALDAT

17 The decoder/encoder system is to use fixed-point binary representation of data. This limits the performance of the filter. The result of using only eight bit wide coefficients can be seen in the next figure, 10. Floatingpoint Fixed-point Representatio Figure 10 - Frequency response of filter using 8 bit coefficients Page 17AKTUALDATSEITEAKTUALDAT

18 6.4.2 Two Cascaded Half-Band FIR filters The graphical user interface for the two cascaded half-band filters is very much the same as the one for a single FIR filter, it has though two control panels for controlling the two individual filters. It was found that using two half band filters would lead to a reduction in the total number of coefficients needed to implement the design. This would in turn lead to a reduction in the number of multiply accumulate modules. When using half-band techniques in FIR filter designs, every second coefficient is equal to zero. As the multiplication of any number by zero, is zero then that leads to a reduction of the number of multipliers. However the number of registers remains the same. Various windowing functions were tested and the most appropriate was found to be the Hanning window. Figure 11 shows the two frequency responses of the half-band filters. Frequency response of one Half-band filter Frequency response of cascaded FIR Filters FigureSEQ Figure ARABISCH11 SEQARABISCH9 Coefficients Two for Cascaded cascaded Half-Band half-band FIR digital filters FIR filter. Page 18AKTUALDATSEITEAKTUALDAT

19 Advantages6.5 Advantages gained by Technical Improvements The technical advantages of using digital technology over analogue are numerous: As there are fewer passive components (resistors, capacitors and transistors), with digital technology then the manufacturing costs will be less. With analogue systems there are numerous potential dividers to adjust to set the video levels up. In a digital system there are only potential dividers on the analogue inputs, so the cost of testing the system is reduced. With fewer solder connections to be made, there should be a higher yield of working units. The filtering and signal conditioning applied to signals are not subject to the same phase distortion that occurs in analogue decoding/encoding systems. Digital technology has a high consistency of parameters as tolerances do apply to binary processing. Because of the digital sampling process different frequencies are sampled by the same clock therefore there would be no differential propagation delays within the digital domain. As FPGAs are programmable devices it is possible to upgrade software with relative ease. This allows products to be kept easily maintainable. As VLSI technology advances, so the current used by ICs decreases, making a power saving on the PCB. The design cycle time for new or modified products will be reduced as the staff get more experienced at designing FPGAs. Using hardware description languages, HDTV will develop reusable code that can be plugged in to different products, reducing the development time of new products. Digits are much more robust with respect to noise or power supply variations and any form of amplitude modulation on top of the signal. As HDTV is entering a maturing programmable logic market, there should be room for cost savings in product development over the competition. This will be possible with the reduction in unit cost for the ICs and reduction in software costs. The dominant improvement to the product, since the parameters of the unit could not change since they were dictated by the Industry Standard, was the use of digital technology which fulfilled the market requirements and their expectations. 6.6 Implementation of Improvements Figure 12 shows a block diagram for the system surrounding and including the FPGA. The three feeds of digital data from each of the FIR filters will be truncated to 10-bits internally inside the filter. This filtered data will be sent to the FPGA where it will multiplex the data into a single 10 bit video stream. During horizontal and vertical timing intervals of the video signal the state-machine inside the FPGA will insert the relevant timing codes. These will be compliant with the ITU-656 standard. At the front porch of Page 19AKTUALDATSEITEAKTUALDAT

20 the horizontal signal there will be an End of Active Video (EAV) signal that will comprise three reference bytes (FF h, 00 h, 00 h ), followed by a timing reference signal know as XY byte. This is broken down as follows: - Bit Fourth word(xy) Field signal status 2 Vertical signal status 3 Horizontal status 4 P 3 (Protection bit 3) 5 P 2 (Protection bit 2) 6 P 1 (Protection bit 1) 7 P 0 (Protection bit 0) At the start of the active video, another code is generated known as a Start of Active Video code. This is the same as the EAV code except the horizontal status will be inverted. The data words occurring during digital blanking intervals that are not used for the timing reference code or for ancillary data are filled with the sequence 80.0 h, 10.0 h, 80.0 h, 10.0 h etc. corresponding to the blanking level of the Cb, Y, Cr, Y signals respectively, appropriately placed in the multiplexed data. Analogue Video ADC Y Channel ADC U Channel FIR Digital Filter FIR Digital Filter M U X FPGA State-machine Based system for inserting EAV and SAV codes ADC V Channel FIR Digital Filter Sync Separator And Genlocking circuitry Horizontal and Vertical video information Fig. 12 -Sub-System Block Diagram for 3 channel Filter Page 20AKTUALDATSEITEAKTUALDAT

21 Figure 13 - Prototype assembly Page 21AKTUALDATSEITEAKTUALDAT

22 7. Choice and rational for the selected technologies, tools and methodologies 7.1 Technology Options The requirements for the technology where :- 1. Provide a digital implementation of the required characteristics (that is the characteristics as laid down in the industry standard specification Rec. ITU-R BT.601). These characteristics where, in essence, already met by the analogue system but the use of a digital implementation was required in order to meet the market requirements for stability and post-system signal manipulation. 2. Provide a cost effective solution to enable HDTV to regain the lost market share. 3. Provide a platform for the future product development strategy of HDTV. The initial investigation into possible solutions for the encoder and decoder path concentrated on the implementation of the digital filter since this was the key element for the improved product. A number of options were considered. 1. Discrete Logic: - An uneconomic proposition. This complex high - speed design would result in a large, complex board, a high manufacturing cost, poor reliability, and high power consumption. High-speed board issues would further complicate the design. The number of logic gates would be in excess of 2000, which would imply a chip count in excess of Digital Signal Processor (DSP): - A DSP is a processor optimised for Multiply- Accumulate (MAC) operations, which occur frequently in signal processing and filtering applications. A DSP typically has one MAC circuit on chip, and one MAC cycle is required for each filter tap. Therefore the data rate and filter length influence the required DSP specification. For example, if a DSP were to implement a 32 tap FIR filter, with a data rate of 54MHz (13.5MHz oversampled by 4) then 1728MIPs are required. This is clearly unrealistic for a single device, and a multi-processor solution would be needed. The advantages of using DSP include a well-established design methodology for implementing filters from their specifications, rapid prototyping, and excellent design flexibility. However, for the proposed high-speed design, several DSP processors would be required, increasing the cost of the product, the overall power dissipation, and board complexity. 3. Field Programmable Gate Arrays (FPGA): - With FPGA or CPLD devices, it is possible to design an optimised high-speed logic function. This allows for the parallel processing of digital data. The major difference between this method and the DSP approach for implementing digital filters is the ability to perform many MAC operations per cycle. Digital Filtering applications require high-end FPGA or CPLD Page 22AKTUALDATSEITEAKTUALDAT

23 devices due to the requirement for many digital multiplication and addition functions. The choice of device architecture can be crucial to the performance of the design. For example, fine-grained FPGA architectures are suited for data path intensive designs, whereas some CPLD architectures perform well when implementing state machines or decoders, also some devices which utilise a look-up table architecture are well suited to multiplication / addition functions. Therefore, a match must be made between the structure of the design and the chosen device architecture. The advantages of using programmable logic include flexibility (especially with RAM based devices), rapid prototyping, and a low cost migration to semi or full custom ASICs can be achieved. 4. Application Specific ICs (ASIC): - ASIC designs imply high NRE costs, but low unit cost. High speeds are obtainable due to a full custom design of a logic function, ASICs also enable large scale integration of system components with low power consumption. Custom or semi-custom approaches allow a design architecture that is optimised for the target application. Implications for the whole design include easier board layout and a reduced parts count. The option of using ASIC technology is heavily influenced by the projected sales volume of the product, since high NRE costs and a lengthy design flow usually make ASIC designs uneconomic for low volume designs. The investigation involved the TTN in order to obtain both an independent view and also to be able to utilise their knowledge of the available technologies. The specification of the requirements was used and an estimation of the costs involved was formulated. The conclusion to the original investigation favoured FPGAs as a solution. Discrete logic was discounted on size, manufacturing cost and reliability, a DSP was discounted on speed, cost and number required and an ASIC solution was discounted on high NRE costs for a product aimed at the low volume, high value, broadcast market place. Therefore the original choice of design methodology was to use an FPGA to implement the digital filtering. However after this initial investigation, the company carried out a detailed investigation into the implications of employing FPGAs to implement the FIR filter design. The investigation proved that to implement a 55-tap FIR filter with 10-bit data width and 16- bit coefficient width would require an FPGA that contained < 4000 configurable logic blocks or macrocells. A costing for such a device was carried out and for a Xilinx FPGA of this size in the maximum speed grade, (this would be needed as the device would be running in excess of 27MHz) was As this is equal to the entire system cost then it can be seen that this excessiveprice is far too high. As investigations into various competitive products were being carried out, it came to light that there existed on the market, an off the shelf IC that could implement the digital filtering. The cost of this off the shelf IC (i.e. Gennum GF9102A or Logic Devices LF3320 (X2) see attachment 3) would be around 18. One IC would be sufficient for one channel of the design, of which there are normally a total of three (YUV). Page 23AKTUALDATSEITEAKTUALDAT

24 However these devices could not, of themselves, provide the full solution because some high speed, complex logic was still required in order to combine the three channels and to insert the necessary timing reference codes into the resultant bit-stream. Such a task is ideally suited to an FPGA for the reasons already referred to and our investigations concluded that this proposed configuration would meet the system specification requirements as well as the system cost requirements. In order to verify the validity of the potential solutions, prototypes of both the FPGA only filter and the FPGA and External Digital Filter, were constructed and evaluated. The tests results indicated that both units performed to the required specification, however the cost differential between the two alternatives meant that an FPGA only filter was not currently a commercially viable proposition. The need for FPGA technology within the company still exists, but the role it will take may change. A simpler FPGA device will still be required to configure the custom part, and to provide the preparation of the digital signal. 7.2 Tools and Methodologies Options SEQARABISCH Having selected the most appropriate technology it was then necessary to determine the most appropriate tool and methodology for the implementation. The criterion that were used were as follows:- 1. Ability of HDTV staff to utilise tools - it was essential that HDTV acquire the technology within their own workforce 2. Tools should be PC based for lower cost of ownership 3. Ability to use a high level of abstraction in order to verify any proposed solution at all stages of it's development 4. Ability to model the solution prior to implementation 5. Ability to remain independent of final target device (within the technology) for as long as possible in order to cater for the introduction of new devices and amendments in the required performance criteria 6. The tools should be supported by training providers Once again the services of the TTN were utilised in order to benefit from the experiences that they had. The options included schematic capture, the use of an HDL (for example VHDL or Verilog) together with logic synthesis and the use of a mathematical modelling tool such as Matlab. The final choice was for VHDL (as described elsewhere) and synthesis together with the use of Matlab. VHDL and synthesis was chosen because of the wide availability of the appropriate tools and their applicability to the chosen technology. The use of schematic capture would not have met the criteria 1) and 3) given above. Matlab was used because Page 24AKTUALDATSEITEAKTUALDAT

25 of the vast experience in the tool that existed at the TTN, making it possible for them to provide a training course allowing HDTV to quickly acquire the knowledge and skills necessary to use it within the project. 8. Expertise and experience in microelectronics of the company and the staff allocated HDTV expertise revolves around the design and manufacture of equipment using analogue and discrete digital logic design for use in professional broadcast equipment and services. Mike Hancock, Managing Director of HDTV Ltd, has over twenty-eight years experience of designing and manufacturing equipment for the video and broadcast market. Most of his experience is with analogue electronics, and systems as well as digital design techniques. He has gained experience working for many video and broadcast companies including the BBC and other leading manufacturers. Mike's role within the project was as project leader and analogue design engineer. As well as this Mike carried out competitive product analysis, and studies into available FPGA technology. Peter Greatorex has experience working within a wide range of electronic areas, including RF electronics, logic design and embedded systems. Peters role within the project was focused mainly upon video filtering and the digital signal processing. Peter was not with the company at the start of the project, however the engineer who was assigned to the project at the start of the project left and we had a great deal of difficulty recruiting a replacement. It was essential that a replacement was recruited in order that the company had sufficient resources to complete the project and continue to service our existing customer base. Although there was a good understanding of analogue filtering techniques there was little experience in digital signal processing for digital filtering applications. There was also no experience or expertise in the area of programmable logic, FPGAs and CPLDs. 9. Work-plan and rational The company has many years experience of analogue video design techniques but has not got experience in digital signal processing and digital filter design. Bournemouth University has been teaching digital signal processing to its students for a number of years and as such has a wealth of in-house knowledge. It was therefore necessary to create a workplan that would enable HDTV to initiate the project, acquire the necessary skills and expertise from Bournemouth University, and then to implement the design and evaluate the results. Training costs given below include cost of course, engineers time (salary) and accommodation/travel costs. Training provided by School of Design Engineering and Computing at Bournemouth Page 25AKTUALDATSEITEAKTUALDAT

26 University unless stated. The following information shows both the original workplan and the final workplan, items that were not included in the final workplan are shown in italics (see table comparing planned and actual tasks). Variations are explained in the text below and in the table that follows. Training - Total Effort 45 person days Training A: Introduction to Digital Video Standards proposed effort in person weeks: 2 actual effort in person weeks: 2 Milestone(s): The company has to learn about specific Digital Video standards involved in the project. Deliverable(s): Initial specification. The costs involved will be: - acquisition of publications: 150 ECU It was Mike Hancock s role to obtain, read and understand the various digital video standards that have been developed by the international standards committees. Training B: Introduction to digital processing techniques proposed effort in person weeks: 1 actual effort in person weeks: 1 Milestone(s): Acquisition of general digital processing techniques. Deliverable(s): Certificate of attendance for DSP course. The costs involved will be: - subcontractor's course: 1200 ECU Peter Greatorex was given an introductory course on digital signal processing. This was carried out at Bournemouth University where Peter was given lectures on the following subjects: - Conversion Techniques Interfacing between analogue and digital domains; From time to Frequency domain; The Z-Domain in DSP; The Fast Fourier Transform; Digital Filtering; FIR Design Methods; IIR Filter Design Methods and Multi-rate Signal Processing. Practical laboratory experiments were also carried out and completed in Matlab. At the end of the course a case study on determining the video filter design was carried out and completed by Mr. Greatorex. Training C: Training on CAD tools related to the FPGA proposed effort in person weeks: 1 actual effort in person weeks: 1 Milestone(s): Acquisition of FPGA CAD techniques. A course on the Computer Added Design tools is necessary because they will be totally new to the user. Deliverable(s): Certificate of attendance for CAD course. The costs involved will be: - subcontractor's course, 5 days = 1700 ECU Training D: Design training on digital filtering/processing with FPGAs proposed effort in person weeks:1 actual effort in person weeks: 2 Milestone(s): Acquisition of FPGA digital filtering and processing techniques. This was essential since it will improve the company's knowledge of the FPGAs internal functions and will allow more efficient use. Deliverable(s): Certificate of attendance for FPGA digital filtering and processing Page 26AKTUALDATSEITEAKTUALDAT

27 course. The costs involved will be: - subcontractor's course, 5 days = 1700 ECU Training D: Training on design simulation tools proposed effort in person weeks:2 actual effort in person weeks: 0 Although planned initially, this activity was fulfilled during the visits by the FPGA company representatives. Training F: Investigate Decimation Techniques proposed effort in person weeks: 1 actual effort in person weeks: 1 Milestone(s): Confirm feasibility of using programmable logic Some consideration was given to the topic of investigating decimation, and it was agreed that this problem could be better tackled after the DSP training course booked at Bournemouth University which took place on the 15 th January 99. This was revisited after the course. Training G: DSP Training proposed effort in person weeks: 2 actual effort in person weeks: 2 The cost involved will be: ECU per day Deliverable(s): Matlab software routine to generate filter coefficients The course covered the following topics: - Conversion Techniques Interfacing between analogue and digital domains From Time to Frequency domain The Z-Domain in DSP The Fast Fourier Transform Digital Filtering FIR design methods IIR design methods Multi-rate signal processing (including a video filter design exercise) This intensive course run at Bournemouth University by Mr S. Holloway has been a good method of getting some DSP knowledge into the company. Specification - Total Effort 97 person days Specification A: Specification of the system to be designed proposed effort in person weeks: 2 actual effort in person weeks: 2 Milestone(s): Full specification of top level system. Deliverable(s): Specification document will be produced. Mike Hancock completed this task. With Mikes many years experience designing video systems, and with the knowledge acquired obtaining the video standards, putting this specification together did not take too long. Page 27AKTUALDATSEITEAKTUALDAT

28 Specification B: Investigation of available FPGA proposed effort in person weeks: 2 actual effort in person weeks: 5 Milestone(s): Assessment of available FPGAs, size, speed, availability, price, peculiarities. Deliverable(s): Available FPGAs evaluation report. This part of the project took many weeks longer than expected. The acquiring of information about FPGAs was carried out in a number of ways. Firstly the University gave some brief guidelines on the various types of technology available. They explained the differences between the programmable logic architectures (FPGA over CPLD) and the available implementation options (SRAM, Anti-Fuse, etc.). At the same time meetings with the distributors of FPGAs were arranged and carried out at HDTV. The meetings were conceived to ascertain a number of things about FPGAs. Firstly they were intended to let the distributors know about HDTVs interest in FPGA technology and to get data books and information about FPGA technology into the company. The meetings were also held to try and ascertain exactly how the various distributors deal with technical problems that customers have. It was found that with a mixture of support from the United States and from Field Applications Engineers from the distributors, most problems with regards design development could be fixed with ease. This took some time to arrange as there where a number of companies to see, they cannot always come at yours or their convenience and getting the right information from them can take time. Specification C: Selection of make of FPGA proposed effort in person weeks: 1 actual effort in person weeks: 1 Milestone(s): Particular make of FPGA selected in order to continue with the programme. Deliverable(s): FPGA manufacturer details listed in specification document Specification D: Subsystems specification proposed effort in person weeks: 3 actual effort in person weeks: 3 Milestone(s): Detailed system functions specified. Deliverable(s): Detailed specification document produced. Specification E: Analyse Competition proposed effort in person weeks: 1 actual effort in person weeks: 3 Milestone(s): Analyse competitive products, prices and determine technology used. Deliverable(s): Competitive product spreadsheet. Mike Hancock contacted known international broadcast competitors to investigate their product specification and price. Page 28AKTUALDATSEITEAKTUALDAT