Lab 3 : CMOS Sequential Logic Gates

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1 CARLETON UNIERSITY epartment of Electronics ELEC-3500 igital Electronics Januar 20, 2004 Lab 3 : CMOS Seuential Logic Gates esign an Specification of Seuential Logic Gates an Librar Cell igital circuits are mae of gates. Up to now ou use gates as boxes. You assume the give out 0 or an their ela is alwas constant. Gates are mae of transistors. Transistor gates o not alwas give out = 5. Without proper precautions it ma be less than 3. The gate propagation ela is not constant. It epens strongl on output loas an input loas. In a two input gate it will be ifferent for each input. In this lab ou will buil gates from transistors, an observe how the properties of the transistors makes the gates less than ieal. You will esign the gates that make up a flip-flop an finall a flip-flop. The seuence of circuits ou will buil are:r a) The transmission gate, an electronic switch. b) The MUX, both analog an igital. c) The latch built from a MUX ) The master-slave flip-flop, mae from latches.. Transistors as Pass Switches MOS transistors can also be use as pass switches for igital or analog signals. The are use to switch auio signals aroun insie stereo sstems. The NMOS Pass Switch There are some limitations on these switches. Reraws FIGURE 2.a as FIGURE 2.9b. Then remembers from Section 0.3 that the source can never rise above G - TH. You shoul be able to euce that near the peak of the waveform the output will be clippe. Q. Using simulations sketch the output for FIGURE 2.. Explain our results in FIGURE 2.a G +5 S 0. OUT (+sin(ωt)) in G S 0. FIGURE 2.9b /home/rshreih/ta_3500/lab3w4.fm IGITAL ELECTRONICS J.Knight, /3/94, moifie b Maitham Shams

2 Carleton Universit , Lab 3 : CMOS Seuential Logic Gates, The PMOS Pass Switch The PMOS pass switch is harer to unerstan than the NMOS one. Think of the capacitor holing a charge an acting as the of the circuit. The istortion will come when in is low. Q2. Using simulations sketch the output for FIGURE 2.2. Explain our results. FIGURE 2.2a FIGURE 2.0b PMOS switch rerawn +5 5 in (+sin(ωt)) The CMOS Transmission Gate The transmission gate contains two transistors. One conucts well for the signals for which the other conucts poorl. Q3. Sketch the output for FIGURE 2.3 as seen from our simulation in FIGURE OUT 0. Q4. Explain the results as compare to the previous two cases 2. The Mux The MUX switches an output between two inputs as ictate b a control signal. Here: if(= =) =; else =; Transmission-Gate MUX. Buil a MUX out of two of the transmission gates an an inverter. You will nee to put voltmeters at an. Signal Inputs Connect a suare wave generators to. Connect some voltage, (mabe 4.5) at, an another for, (mabe 0.5) at This allows to be seen to change when the MUX switches from to. Q5. Sketch the circuit an output. Ctrl Ctrl MUX G FIGURE 2.4 FIGURE Electronic Engineering Januar 20, 2004 page 2, of 5

3 Carleton Universit , Lab 3 : CMOS Seuential Logic Gates, Testing the MUX etermine the propagation ela between the time the rises an the switche output appears at. This is calle t CHY (time from Control High to Y ali). Most of these propagation elas are measure between 50% points. Make the rise an fall times fast enough (uner ns). Otherwise ou will be reporting that t CHY is proportional to the input rise/fall time. The Spice pulse generator can be set from its attributes as shown in FIGURE 2.6. t RISE t ELAY FIGURE 2.6 t CHY t FALL t PULWITH t PERIO Q6. Recor t CHY an the similar signal t CLY (Control Low Y ali). 3. The -latch Convert the MUX to a -Latch. FIGURE 2.5b will work for a MUX constructe of gates but not transmission gates. The conservation of energ has everthing to o with this. A gate has gain. Q7. A components to our latch work to make it work with transmission gates. FIGURE 2.7 MUX mae from gates In orer to check the setup time of the latch one must change an clk at the same time. Use two suare-wave generators, has a perio about 0.25 ns faster than but with [(/2 perio) + 2ns] larger initial ela (TELAY). This will allow the an clk input eges to slie past each other. FIGURE 2.8 FIGURE 2.5b latch from a MUX MUX G 20K T L T L T L T L Testing The Latch Make sure our latch functions as a transparent latch. If the output ecas with time, ou are just looking at the storage on a charge capacitor. This is not a static latch! It will forget if the clock is slow. The 0K loa resistor was use to be sure the output eca woul be fast enough to see easil Q8. Sketch our circuit an the part of our test waveform that proves the latch functions as a transparent latch. FIGURE 2.9 C LATCH 0K. The emonstration Pspice is limite to 0 transistors. You will have to use the inverter mae without transistors or use the full Pspice simulator. /home/rshreih/ta_3500/lab3w4.fm Januar 20, 2004 page 3, of 5

4 Carleton Universit , Lab 3 : CMOS Seuential Logic Gates, The Setup Time If the input changes too close to the ege the input will not be capture as. However if the input is Setup time stable at least a setup time before the ege, the at approximate stable value will be capture. Note was capture as Q9. Measure the setup time using our sliing waveforms. You ma want to exten the time of the simulation. The FIGURE 2.0 length is controlle b the attributes in the oscilloscope or the.tran comman in SPICE. The smbol for a transmission gate is or Your latch shoul be as shown in FIGURE 2. or FIG- URE 2.2. A a 2pf capacitive loa to an see if that effects the setup time. Q0. Measure the new setup time. Comment on wh an output loa woul change the setup time which woul appear to be associate onl with the input. Commercial latches a an extra inverter as a buffer amplifier to keep the loa from influencing the setup time. Q The Hol Time Q The hol time is the length of time the signal must be stable after the clock changes FIGURE 2.2 to be sure of capturing the correct value. Goo latches have zero or even a negative hol time. The same sliing waveforms use to measure the setup time can also measure the hol time. Q. Measure the hol time. FIGURE 2.3 testing for zero hol time 4. The Flip-Flop The master-slave flip-flop is mae b connecting two latches in series. The two are transparent on opposite clock eges. X FIGURE 2. 20K Longer hol time neee Zero hol time Less than zero hol time STORE Q M STORE Q S Q MASTER SECTION FIGURE 2.4 SLAE SECTION Electronic Engineering Januar 20, 2004 page 4, of 5

5 Carleton Universit , Lab 3 : CMOS Seuential Logic Gates, CLOCK LOW CLOCK HIGH FIGURE 2.5 HOL When the master is high it hols the output an the transparent slave lets it through. When the master goes transparent, the slave hols the previous output so it oes not change. HOL esign esign a flip-flop an implement a moel in Spice. Use the moel to etermine the following specifications: (i) the setup time, (ii) the hol time, (iii) the clock to output time t CHQ, (iv) the high output voltage with a 0.5 ma output current (The output high an loae with a 0K resistor), an (v) the low output voltage when sinking 0.5 ma. ( The output low an loae with a 0K resistor connecte to.) 5. eliverables: - Fill out a cover sheet. - emo our work to a TA. - Answer all uestions. /home/rshreih/ta_3500/lab3w4.fm Januar 20, 2004 page 5, of 5

Lab 3 : CMOS Sequential Logic Gates

Lab 3 : CMOS Sequential Logic Gates CARLETON UNIERSITY epartment of Electronics ELEC-3500 igital Electronics September 30, 2005 Lab 3 : CMOS Seuential Logic Gates esign an Specification of Seuential Logic Gates an Librar Cell igital esigns