Configuring FLASHlogic Devices

Transcription

1 Configuring FLASHlogic s April 995, ver. Application Note 45 Introduction The Altera FLASHlogic family of programmable logic devices (PLDs) is based on CMOS technology with SRAM configuration elements. This technology supports in-circuit reconfigurability (ICR) via the Joint Test Action Group (JTAG) interface without requiring any special programming voltages. FLASHlogic devices can be reconfigured with the FLASHlogic Download Cable or an intelligent host. Each FLASHlogic device has on-board, non-volatile FLASH or EPROM memory that stores a single configuration. An external controller, such as a microcontroller or state machine, is required for reconfiguration. When the device is powered up, the configuration information is written into the on-board SRAM and the device is ready to perform its intended function. The FLASH or EPROM memory is programmed with Altera s PENGN software, which is not discussed in this application note. For more information on programming FLASHlogic devices, refer to the PLDshell Plus/PLDasm User s Guide V5.0, available from Altera Literature at (408) JEDJTAG Operation To reconfigure a FLASHlogic device, you must first use Altera s PLDshell Plus software or third-party software to create a JEDEC (.jed) that contains the FLASHlogic device configuration information. You can then process the file with Altera s JEDJTAG software and use it to reconfigure the device. The JEDJTAG software is included with PLDshell Plus. The Altera MAX+PLUS II development system provides programming-only support for FLASHlogic devices. Full device support is planned for the second half of 995. JEDJTAG converts a JEDEC into one of three different output formats: a Bit (.bit), a Binary (.bin), or a Hexadecimal (Intel- Format) (.hex). The output format you choose depends on the type of controller used to reconfigure the device. The controller then uses the selected output format to send the configuration data to the FLASHlogic device via the JTAG interface. Table describes the JEDJTAG input files. f Go to the PLDshell Plus/PLDasm User s Guide V5.0 for additional information on the FLASHlogic Download Cable, the JEDJTAG software, and FLASHlogic device configuration. Altera Corporation A-AN-045-0

2 Table. JEDJTAG Input s String Description (.sdl) <file name>.jed jtag.dvc Description Describes the JTAG chain, which is the series of connected devices on a circuit board. JEDEC (s) generated with PLDshell Plus software can be used to configure the FLASHlogic devices. Library file, included with the PLDshell Plus software, that contains a description of several common JTAG devices. You can easily add information for other JTAG devices from device data sheets or from the appropriate Boundary Scan Description Language (BSDL). Instructions on adding devices are included in the jtag.dvc file. The JEDJTAG software produces one of the output formats shown in Table. Table. JEDJTAG Output s <file name>.bit <project name>.bin <project name>.hex Description JEDJTAG intermediate file. JEDJTAG creates one Bit for each JEDEC, then compares the time stamps. If the JEDEC is more recent, JEDJTAG recreates the Bit. Bin containing the JEDJTAG stream of JTAG signals. This file is used to create a Hex or is sent to the computer s parallel port. The Bin is created from Bit s. Hex used for programming standard memory devices. To start the JEDJTAG software, type the following command at the DOS prompt: jedjtag <project name> 9 Figure shows a block diagram of JEDJTAG operation. Altera Corporation

3 Figure. JEDJTAG Block Diagram String Description.sdl Hex.hex ICR via Intelligent Host JEDEC.jed JEDJTAG Software Parallel Port Reconfiguration via FLASHlogic Download Cable Library jtag.dvc Binary.bin Custom Reconfiguration Scheme (i.e., Board Tester or Other Process) The String Description lists the JTAG device chain and any associated JEDEC s, as shown in the example.sdl file in Figure. Figure. String Description (example.sdl) In this example, a pipe character ( ) indicates a comment line. FILE: example.sdl -Simple Prototype Board { Port_Num Port_Type STRING 3 BIN_FILE Port_Num - for LPT: Port_Type must be PARALLEL_PORT or BIN_FILE Loc. Ref JEDEC DEVICE 0 U3 EPX780QC3 RIGHT.JED DEVICE U4 EPX780LC84 LEFT.JED DEVICE U TI_74BCT8373 } The STRING instruction in the String Description controls which operations JEDJTAG uses for the JTAG chain. To create a Hex or a Bin, specify the following: STRING 3 <file type> where 3 specifies the configuration option that enables you to generate a file, and <file type> is either HEX_FILE or BIN_FILE. Altera Corporation 3

4 To send the configuration via the PC s parallel port, you must specify parallel port instructions in the String Description as follows: STRING <parallel port> PARALLEL_PORT where <parallel port> is to specify LPT and to specify LPT. The example.sdl file shown in Figure describes the JTAG device chain shown in Figure 3. In this example, does not have a JEDEC, and will not be reconfigured by JEDJTAG. Figure 3. JTAG Chain (example.sdl) External Connector TDI TDO TDI TDO TMS & TCK TDI TDO 0 Configuring FLASHlogic s Using ICR In-circuit reconfigurability (ICR) enables you to reconfigure devices that are already soldered onto a printed circuit board. For example, you can use the FLASHlogic Download Cable or an intelligent host to change the logic in add-on card applications that interface with different buses. In-Circuit Reconfiguration with the FLASHlogic Download Cable If a printed circuit board has a JTAG chain with a header, you can use the FLASHlogic Download Cable to reconfigure devices in-circuit. 4 Altera Corporation

5 To use the FLASHlogic Download Cable:. Connect one end of the cable to your PC s parallel port, and connect the other end of the cable to the JTAG header on your printed circuit board.. Create the JEDEC (s) for the design. 3. Create a String Description that describes the JTAG chain. Be sure to include the appropriate parallel port STRING instruction. 4. Run JEDJTAG. This software generates a Bin and downloads it to your board to reconfigure the FLASHlogic device(s). In-Circuit Reconfiguration with an Intelligent Host When you reconfigure a device using an intelligent host, your system must have the appropriate storage capability, such as ROM, external peripherals, or disk drives. To reconfigure a device with an intelligent host:. Create the JEDEC (s) for the design.. Create a String Description that describes the JTAG chain. Be sure to include the appropriate Hex STRING instruction. 3. Run JEDJTAG to create the Hex. 4. Program the storage memory with the Hex. 5. Develop software using the guidelines specified by your microcontroller manufacturer to download the configuration data from the storage device into the FLASHlogic device(s). You can use almost any combination of CPU and memory to reconfigure FLASHlogic devices in-circuit. For example, you can use an Intel 87C5 microprocessor as an intelligent host. See Figure 4. Altera Corporation 5

6 Figure 4. Implementing ICR with an Intelligent Host 87C5 Memory Hex (.hex) JTAG FLASHlogic FLASHlogic The interconnect between the CPU and the JTAG chain requires four I/O signals (TMS, TCK, TDI, and TDO), plus a RESET signal, if necessary. See Figure 5. Figure 5. Sample Schematic for Implementing ICR with an Intelligent Host MHz C Y 33 pf 4 37 V CC LED DS R3 3 C 33 pf V CC R 5 S XTAL XTAL 0.5 k V CC 35 R9 EA# C 4.7 µf XTAL XTAL EA-/V PP C5-Reset 0 Reset R.5 AL/Prog- 33 ALE P00/AD0 43 ADO0 P0-AD 4 ADO P0/AD 4 ADO P03/AD4 40 ADO3 P04/AD5 39 ADO4 P05/AD5 38 ADO5 P06/AD6 37 ADO6 P07/AD7 36 ADO7 4 A08 P0/A8 5 A09 P/A9 6 A0 P/A0 7 A P3/A 8 A P4/A 9 A3 P5/A3 30 A4 P6/A4 3 A5 P7/A5 87C5FA 3 PSEN- OC- C D 3 D 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D 74HCT573 9 AO0 Q 8 AO Q 7 AO 3Q 6 AO3 4Q 5 AO4 5Q 4 AO5 6Q 3 AO6 7Q AO7 8Q FLASH Memory 56KX8 CE V 4 PP OE 3 WE A0 A I/O 3 0 A I/O 4 9 A3 I/O3 5 8 A4 I/O4 7 7 A5 I/O5 8 6 A6 I/O6 9 5 A7 I/O7 0 7 A8 6 A9 3 A0 5 A 4 A 8 A3 9 A4 3 A5 I/O8 JTAG Chain of FLASHlogic s LED_R RESET_R# TDI_Port_R TDO_Port_R TMS_R TCK_R P0/T 3 P/TEX 4 P/ECI 5 P3/CEX0 6 P4/CEX 7 P5/CEX 8 P6/CEX3 9 P7/CEX4 P30/RXD P3/TDX 3 P3/IN0-4 P33/IN - 5 P34/T0 6 P35/T 7 P36/WR - 8 P37/RD - 9 Flash-CE# A6 A7 Write# Read# 30 A6 A7 V CC C4 0. µf C5 C6 0. µf 0. µf C7 0. µf 6 Altera Corporation

7 Figure 6 shows the code used by the 87C5 microprocessor to control the JTAG chain. Figure 6. Hex Download Algorithm for the 87C5 (Part of ) ;******************************************************************** ;* JTAG STAND-ALONE LOADER CODE ;** ;* This program usually executes in an embedded controller from an ;* executable memory bank. It transmits data from a local nonvolatile ;* data memory bank to a JTAG IEEE 49. chain, typically to load the ;* SRAM control memory in the FLASHlogic devices in the chain. ;** ;* Data is stored in the non-volatile memory off-line, e.g., with a PROM ;* programmer. It is formatted as a JTAG data stream. Each byte ;* contains TDO/TMS data for 4 TCK cycles. Bit 0 of each byte is the ;* first TDO, bit is the first TMS, bit is the second TDO, etc. ;* No inversion occurs between memory and TMS/TDO. ;** ;* The first four bytes in the non-volatile memory specify the Ending ;* Address +. The least significant byte is at data address 0. The ;* JTAG data stream starts at data address 4. ;** ;* Data is automatically downloaded each time the embedded controller ;* is reset, including power-on. ;******************************************************************** ; Initialization SET LED# port bit ; turn off LED DELAY (500) ; delay 500 ms. ; Give time for host JTAG string to completely power-up before beginning. CLR TICK port bit ; init TCK to LOW CLR RESET# port bit ; init RESET# to LOW (activate host RESET) CLR CE# port bit ; enable FLASH memory CLR LED# port bit ; turn on LED ; Transmit data adrs = 0; initialize data address and last-adrs = (adrs) ; last address + (these are 3 bit values) adrs = adrs + 4; WHILE (adrs < last_adrs) ( ; loop until all data is moved from memory to JTAG chain ; output lst TMS/TDO MOVE bit 0 of (adrs) to TDO port bit MOVE bit of (adrs) to TMS port bit SET TCK port bit ; pulse TCK CLR TCK port bit Altera Corporation 7

8 Figure 6. Hex Download Algorithm for the 87C5 (Part of ) ; output nd TMS/TDO MOVE bit of (adrs ) to TDO port bit MOVE bit 3 of (adrs) to TMS port bit SET TCK port bit ; pulse TCK CLR TCK port bit ; output 3rd TMS/TDO MOVE bit 4 of (adrs) to TDO port bit MOVE bit 5 of (adrs) to TMS Port bit SET TCK port bit ; pulse TCK CLR TCK port bit ; output 4th TMS/TDO MOVE bit 6 of (adrs) to TDO port bit MOVE bit 7 of (adrs) to TMS port bit SET TCK port bit ; pulse TCK CLR TCK port bit adrs = adrs + ) ; Completion SET RESET# port bit ; release host SET LED# port bit ; turn off LED SET CE# port bit ; disable memory to save power SLEEP ; disable embedded controller to save power Conclusion Altera s FLASHlogic family of PLDs provides the features and flexibility designers need for many of today s applications. These devices can be reconfigured in-circuit, allowing quick and easy design iterations and field upgrades. 60 Orchard Parkway San Jose, CA (408) Applications Hotline: (800) 800-EPLD Customer Marketing: (408) Literature Services: (408) Altera, MAX, MAX+PLUS, and FLEX are registered trademarks of Altera Corporation. The following are trademarks of Altera Corporation: MAX+PLUS II, AHDL, and FLEX 0K. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog and Verilog-XL are registered trademarks of Cadence Design Systems, Inc. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Synopsys is a registered trademark of Synopsys, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright 996 Altera Corporation. All rights reserved. 8 Altera Corporation Printed on Recycled Paper.