Implementation of New Low Glitch and Low Power dual Edge Triggered Flip-Flops Using Multiple C-Elements

Transcription

1 Implementation of New Low Glitch and Low Power dual Edge Triggered Flip-Flops Using Multiple C-Elements I. Pavani Akhila Sree P.G Student VLSI Design (ECE), SVECW D. Murali Krishna Sr. Assistant Professor, Dept of ECE, SVECW ABSTRACT-New designs of dual-edge-triggered ( DET) flip-flops that uses C-elements were presented in this paper. Which were the improvements made upon the basic Latch-MUX DET flip-flops. In the improved designs the output does not suffer any deviations due to glitches at the input, so that the designs can ensure low power consumption. FiveDET flip-flops presented were simulated 45nm CMOS technology.when compared to existing DET flip-flops the presented DET flip-flops are having less power consumption and power-delay-product. KEY WORDS- C-elements, Dual-edge-triggered flip-flops, low power I. INTRODUCTION Flip-flops and latches are principal elements that are used for the storage purpose in electronic systems. The overall performance of the electronic system is directly affected by the performance of Flip-flop.So it is imperative to design Flip-flops with high speed and low power consumption. Dual-edge-triggered (DET) flipflops triggers at the both edges of the clock in order to produce the same data rate as if Single-edge-triggered (SET) Flip-flops at half of the clock frequencyand low power dissipation of synchronous circuits [1], [2]. The paper present novel Flip-flops designs which were based on C-elements. This paper has five sections. Section I is introduction, Section II is circuit description which presents low-glitch-power LG_C Flip-flop, Implicit-pulsed IP_C Flip-flop, Floating-node FN_C flip-flop and Two Conditional toggle Flip-flops CT_C and CTF_C Flip-flops, Section III is simulation results where the simulated results are compared with existing flip-flops and finally Section IV concludes this paper. II. CIRCUIT DESCRIPTION A C-element introduced in [3] bye Muller C, so it was named as C-element. It has three terminal, two inputs and one output. When both the inputs are equal (i.e. either both are 1 or 0) the output switches to the input value, previous output will be appeared in remaining cases. C-elements can be used in Finite state machines (FSMs) and in the designing of the Flip-flops and Latches. The C-element has different structures which gives the same operation,in this paper we use weak feedback and dynamic implementations of the C-elements as shown in Figure 1 and Figure 2 respectively. 89 I. Pavani Akhila Sree, D. Murali Krishna

2 Fig 1: Schematic of Weak feed back C-element Fig 2: Schematic of Dynamic C-element i. Low-Glitch-Power DET LG_C Flip-Flop Low glitch power LG_C DET flip-flop uses three C-elements. LG_C flip-flop can be designed using both inverting and non inverting configuration of C-elements, but we prefer inverting configuration of C-element as it is having less delay when compared to non-inverting configuration of C-element. The transistor level schematic of LG_C flip-flop is as shown in the figure 3. The operational waveforms of the LG_C flip-flop are as shown in the figure4. In this flip-flop D and CK are two inputs, A and B are the two internalnodes and Q is the output. The input C-elements are driven by the opposite clocks same as if in the Latch MUX DET flip-flop design. Another input to the input C-elements is D and the inputs to the output C-element are A and B which are the outputs of the input C-element, the final output is Q. When D becomes equal to CK and CKbar the internal nodes A and B switches to CKbar and CK respectively. At least one the node A or B should be Dbar in between the clock transitions. When clock changes the node that is not at Dbar will be switched to Dbar( i.e. both A and B are at Dbar for while after every clock transition). Which results the output C-element switching Q to D. Fig-3: Transistor-Level schematic of the novel LG_C DET flip flop using inverting C-elements. 90 I. Pavani Akhila Sree, D. Murali Krishna

3 Fig 4: Operational waveforms of LG_C DET flip-flop ii. Implicit Pulsed IP_C Flip-Flop The LG_C flip-flop is having high power consumption due to the latches that are present at the nodes A and B (Latches mean the back to back connection of inverters). The purpose of latches at nodes A and B is to keep those nodes at CKbar and CK respectively and to allow them to be switched to Dbarat clock transitions. At a particular moment only one latch either A or B is required, because there is no moment when D is CK nor CKbar. So LG_C flip-flop is modified to IP_C flip-flop by adding two additional inner C-elements to get the same operation of LG_C flip-flop without using the latches. The transistor level diagram of the IP_C flip-flop is as shown in the figure 5.The IP_C flip-flop has superficial resemblance with common Latch-MUX flip-flop, its operation is quite different. The operational waveforms of the IP_C flip-flop are as shown in the figure 6. The D input is only responsible for timing of the inversions of the nodes A and B, whenever the clock changes one of the A or B that is not at Dbar changes to Dbar with the help of strong transistors of the input C- element, the other node is toggled with the help of weak transistors. The output Q switches to D after every clock transition when both A and B are equal to Qbar. Fig-5: Transistor Level schematic of the novel IP_C DET flip flop. 91 I. Pavani Akhila Sree, D. Murali Krishna

4 Fig-6:Operational waveforms of IP_C DET flip-flop iii. Floating Node FN_C Flip-Flop The IP_C flip-flop consumes more power because the signal levels at A and B toggles after every clock transitions irrespective of D and Q. In order to get correct output few conditions has to be satisfied at the flipflops input stage. One of the node either A or B should be kept at Qbar in between the clock edges in order to avoid the switching of output. Both the nodes should be at Dbar for a small interval of time after every change in clock. These requirements are satisfied in LG_C flip-flop by using the two independent latches at A and B, In IP_C flip-flop this operation is performed by the cross-connection of the weak inner C-elements by fulfilling the requirements that are needed to perform the correct operation. The transistor level schematic of FN_C is as shown in figure 7and the operation wave forms are shown in figure 8. Because of the crosscoupling, nodes at A and B are at opposite signal levels which ensures one of the node at Qbar, The correct operation is performed. The improved floating node FN_C flip-flop design does not for look the node that is at Qbar and does not reinforce the signal levels, using the weak feedback of X this behavior is implemented(x is the Q that follows into the inner cross couple weak C-elements). This FN_C DET flip-flop is said to have better performance when compared to IP_C DET flip-flop due this feedback connection. The FN_C disadvantages are rectified and new designs CT_C and CTF_C flip-flops were proposed which were improvements on FN_C flip-flop. Fig 7: Transistor Level schematic of the novel FN_C DET flip flop 92 I. Pavani Akhila Sree, D. Murali Krishna

5 Fig 8: Operational waveforms of FN_C DET flip-flop iv. Conditional Toggle CT_C and CTF_C Flip-Flops The number of transistors in the FN_C flip-flop are more, If we reduce the transistor count and obtain the same operation of the DET flip-flop, High performance can achieved. The FN_C flip-flop is modified to CT_C flip-flop using only 20 transistor for input, output and clock buffering. The transistor level implementation of the CT_C flip-flop is as shown in the figure 9 and its operational waveforms in figures 10. The inputs D and the signal that mirrors the Q in between the clock transitions. When D and Q are equal, the signal level at X is kept at Qbar by the weak C- element, when D and Q are not equal X I kept at Qbar by using the latch. The back to back connection of inverters and 2to1 MUX with its output connected to X constitutes a latch part. But this latch part consumes high power so CT_C flip-flop is modified to CTF_C flipflop. Fig 9:Transistor Level schematic of the novel CT_C DET flip flop The transistor level implementation of CTF_C is as shown in the figure 11. The operation of the CTF_C flipflop is same as CT_C flip-flop and the operational waveforms are as shown in the figure below. The CTF_C flip-flop is having high performance in term of switching speed and power consumption when compared to the CT_C flip-flop. 93 I. Pavani Akhila Sree, D. Murali Krishna

6 Fig 10: Operational waveforms of CT_C DET flip-flop Fig 11: Transistor Level schematic of the novel CTF_C DET flip flop III. SIMULATION RESULTS The flip-flops presented in this paper were simulated, power and delay of these flip-flops were calculated in 45 CMOS technology with the help of cadence virtuoso tool.the s Latch-MUX flip-flop[5] and the LM_C flip-flop[6] are the previously existing deign which were compared with designs presented in this paper. The designs were simulated at 0.85V supply voltage and 1GHZ frequency which results in cycle time of 0.5ns. 94 I. Pavani Akhila Sree, D. Murali Krishna

7 Table1: Comparison of delay and power of different DET flip-flops in 45nm CMOS Technology Name of flip-flop # of T Power(uw) Delay(ps) PDP(fJ) Latch-MUX Flip-flop [5] LM_C Flip-flop [6] LG_C DET Flip-flop IP_C DET Flip-flop FN_C DET Flip-flop CT_C DET Flip-flop CTF_C DET Flip-flop IV. CONLUSION The five flip-flop designs were presented in this paper. The designs are the improvements made upon common Latch-MUX design in order reduce the effect input glitches at the output. The designs CT_C flip-flop and CTF_C flip-flop are having low power and power delay product (PDP) is also optimized when compared to the Latch-MUX design. The CT_C flip-flop and CTF_C flip-flop designs can be used in high performance scenarios as they are having superior characteristics such as power and PDP product REFERENCES [1] N. Nedovic and V.G. Oklobdzija, Dual-edge triggered storage elements and clocking strategy for low-power systems, IEEE Trans. Very Large Scale Integr.(VLSI)Syst., vol. 13,no.5,pp ,May [2] A.G.M.Strollo,E.Napoli, and C.Cimino, Analysis of power dissipation in double edge-triggered flip-flops, IEEE Trans. Very Large Scale Integr. (VLSI)Syst., vol. 8,no. 5,pp , Oct [3] D.E Muller, Theory of asynchronous circuits, Internal Rep. o 66, Digit. Comp Lab.,Univ. Illinois at Urbana- Champaign, [4] M. Shams, J.C. Ebergen, and MI Elmasry, Modeling and comparing CMOS implementations of the C-element, IEEE Trans. Very Large Scale Integr.(VLSI)Syst.,vol.6,no.4,pp ,Dec.1998 [5] R.Hossain, l.. D Wronski, and A.Albicki, Low power designs using double edge triggered flip-flops, IEEE Trans. Very Large Scale Intefr. (VLSI) Syst., vol.2, no.2, pp , Jun.1994.b [6] S.V. Devarapalli, P.Zarkesh-Ha, and S.C. Suddarth, A robust and low power dual data rate (DDR) flip-flop using C-elements, in Proc. 11 th IntSymp. Quality Electron. Des. (ISQED), Mar , pp, I. Pavani Akhila Sree, D. Murali Krishna