Testing Digital Systems II
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1 Testing Digital Systems II Lecture 7: Built-in Self Test (III) Instructor: M. Tahoori Copyright 206, M. Tahoori TDS II: Lecture 7 BIST Architectures Copyright 206, M. Tahoori TDS II: Lecture 7 2 Lecture 7
2 Logic BIST Architectures Four Types of BIST Architectures: No special structure to the Make use of scan chains in the Configure the scan chains for test pattern generation and output response analysis Use concurrent checking circuitry of the design Copyright 206, M. Tahoori TDS II: Lecture 7 3 Centralized and Separate Board-Level BIST (CSBL) Two LFSRs and two multiplexers are added to the circuit. The first LFSR acts as a, the second serves as a SISR. The first multiplexer selects the inputs, another routes the PO to the SISR. PIs n n M U X n TEST (C or S) m k MUX k = [log 2 m] SISR POs CSBL Architecture [Benowitz 975] Copyright 206, M. Tahoori TDS II: Lecture 7 4 Lecture 7 2
3 Built-In Evaluation and Self-Test (BEST) Use a and a. Pseudo-random patterns are applied in parallel from the to the chip primary inputs (PIs) is used to compact the chip output responses PIs P R P G (C or S) M I S R POs BEST Architecture [Perkins 980] Copyright 206, M. Tahoori TDS II: Lecture 7 5 Separate PR-BIST In addition to the internal scan chain, an external scan chain comprising all primary inputs and primary outputs is required. The External scan-chain input is connected to the scan-out point of the internal scan chain. S in SISR S out PIs R R 2 (C) S i S o POs LOCST Architecture SRL SRL [Eichelberger 983] Copyright 206, M. Tahoori TDS II: Lecture 7 6 Lecture 7 3
4 Separate PR-BIST Ctl R R2 Shift Test Pattern BIST Ctl ORA R3 ORA Shift Test Response NORMAL Shift Test Pattern In, Response Out Apply Pattern, Get Response Drawbacks: Long Test Time, Poor Delay Fault Cover Advantages: Low Overhead, Simple Control Logic Copyright 206, M. Tahoori TDS II: Lecture 7 7 Test-per-Clock System New fault set tested every clock period Shortest possible pattern length 0 million BIST vectors, 200 MHz test / clock Test Time = 0,000,000 / 200 x 0 6 = 0.05 s Copyright 206, M. Tahoori TDS II: Lecture 7 8 Lecture 7 4
5 Test-per-Scan System New fault tested during clock vector with a complete scan chain shift More time required per test than test-per-clock Advantage: Combination of scan chains and reduces bit width Disadvantage: Much longer test pattern set length, causes fault simulation problems Input patterns time shifted & repeated Become correlated reduces fault detection effectiveness Use XOR network to phase shift & decorrelate Copyright 206, M. Tahoori TDS II: Lecture 7 9 STUMPS Self-Test Using and Parallel Shift register sequence generator Originally proposed to reduce overhead of LFSR/ for application to testing multi-chip boards, each of which has only the Shift Registers Can also be used on a single chip with multiple scan chains Copyright 206, M. Tahoori TDS II: Lecture 7 0 Lecture 7 5
6 STUMPS Example SR SRn 25 full-scan chains, each 200 bits 5000 chip outputs, need 25 bit (not 5000 bits) (C or S) Linear Phase Shifter (C or S) Linear Phase Compactor STUMPS A STUMPS-based Architecture Copyright 206, M. Tahoori TDS II: Lecture 7 STUMPS Test procedure: Scan in patterns from LFSR into all scan chains (200 clocks) Switch to normal functional mode and clock x with system clock Scan out chains into (200 clocks) where test results are compacted Overlap Steps & 3 Requirements: Every system input is driven by a scan chain Every system output is caught in a scan chain or drives another chip being sampled Copyright 206, M. Tahoori TDS II: Lecture 7 2 Lecture 7 6
7 Built-In Logic Block Observer (BILBO) The architecture applies to circuits that can be partitioned into independent modules (logic blocks). Each module is assumed to have its own input and output registers (storage elements) Or such registers are added to the circuit where necessary. The registers are redesigned so that for test purposes they act as s or s. Copyright 206, M. Tahoori TDS II: Lecture 7 3 Embedded PR-BIST BILBO Ctl R R2 Shift R3 Shift NORMAL Apply Test, Compact Response Shift Signature Out Drawbacks: Multiple Test Sessions, Complex Control Register Self-adjacency Concerns Advantages: At-speed Test, Reuse System Bistables Copyright 206, M. Tahoori TDS II: Lecture 7 4 Lecture 7 7
8 Built-In Logic Block Observer B 2 Y 0 Y Y 2 B 0 D Q D Q D Q Scan-In SCK X 0 X Scan-Out/X 2 A 3-stage BILBO Copyright 206, M. Tahoori TDS II: Lecture 7 5 Another BILBO Register B and B2 configure as Shift register for scan (BB2= 00), LFSR (BB2 = 0), (BB2 = ) Normal (BB2 = 0) Copyright 206, M. Tahoori TDS II: Lecture 7 6 Lecture 7 8
9 Example BILBO Usage SI Scan In SO Scan Out Characteristic polynomial: + x + + x n s A and C: BILBO is, BILBO2 is LFSR B: BILBO is LFSR, BILBO2 is Copyright 206, M. Tahoori TDS II: Lecture 7 7 Register self-adjacency Register R2 is self-adjacent It should act as LFSR and at the same time Cannot use BILBO register Ctl R R2 Copyright 206, M. Tahoori TDS II: Lecture 7 8 Lecture 7 9
10 Embedded PR-BIST Circular Ctl R R2 R3 Normal Test Drawbacks: Scan Dependence Concerns Advantages: At-speed Test, Reuse System Bistables Simple Control Logic, Short Test Time Copyright 206, M. Tahoori TDS II: Lecture 7 9 Concurrent Built-In Logic Block Observer (CBILBO) Y 0 Y Y 2 B Scan-Out 0 0 D Q D 2D Q SEL D Q D 2D Q SEL D Q D 2D Q SEL [Wang 986c] Scan-In B 2 SCK X 0 X X 2 A 3-stage concurrent BILBO (CBILBO) Copyright 206, M. Tahoori TDS II: Lecture 7 20 Lecture 7 0
11 Circular Self-Test Path CIRCULATE S in 0 PIs SR TEST S out (C) Y i X i- 0 CLK D Q Xi POs (a) The CSTP architecture (b) Self-Test cell CSTP architecture Copyright 206, M. Tahoori TDS II: Lecture 7 2 Concurrent Self-Verification (CSV) n Functional Circuitry m Duplicate Circuitry m Checking Circuitry two-rail checker CSV Architecture Copyright 206, M. Tahoori TDS II: Lecture 7 22 Lecture 7
12 Summary B: board-level testing C: combinational circuit S: sequential circuit Representative Logic BIST Architectures Copyright 206, M. Tahoori TDS II: Lecture 7 23 Lecture 7 2
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