Topic 8. Sequential Circuits 1
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1 Topic 8 Sequential Circuits 1 Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Rabaey Chapter 7 URL: p.cheung@ic.ac.uk 1 Based on slides from Prentice-Hall Topic 8-1
2 Mux-Based Latches Negative latch (transparent when CLK= 0) Positive latch (transparent when CLK= 1) 1 Q 0 Q D 0 D 1 CLK CLK Topic 8-2
3 Mux-Based Latch Topic 8-3
4 Mux-Based Latch NMOS only Non-overlapping clocks Topic 8-4
5 Master-Slave (Edge-Triggered) Register Two opposite latches trigger on edge Also called master-slave latch pair Topic 8-5
6 Master-Slave Register Multiplexer-based latch pair Topic 8-6
7 Reduced Clock Load Master-Slave Register Topic 8-7
8 Overpowering the Feedback Loop Cross-Coupled Pairs NOR-based set-reset Topic 8-8
9 Cross-Coupled NAND Cross-coupled NANDs Added clock This is not used in datapaths any more, but is a basic building block for memory cell Topic 8-9
10 Sizing Issues Output voltage dependence on transistor width Transient response Topic 8-10
11 Storage Mechanisms Static Dynamic (charge-based) Topic 8-11
12 Making a Dynamic Latch Pseudo-Static Topic 8-12
13 Master-Slave Static Flip-flop Overlapping Clocks Can Cause Race Conditions Undefined Signals Topic 8-13
14 Two-phase dynamic flip-flop Topic 8-14
15 Use 2-phase non-overlapping clocks Topic 8-15
16 Latch + Logic Topic 8-16
17 Other Latches/Registers: C 2 MOS Keepers can be added to make circuit pseudo-static Topic 8-17
18 Insensitive to Clock-Overlap V DD V DD V DD V DD M 2 M 6 M 2 M 6 D M X M 8 Q D X Q 1 M 3 1 M 7 M 1 M 5 M 1 M 5 (a) (0-0) overlap (b) (1-1) overlap Topic 8-18
19 Pipelining Reference Pipelined Topic 8-19
20 Other Latches/Registers: TSPC Positive latch (transparent when CLK= 1) Negative latch (transparent when CLK= 0) Topic 8-20
21 Including Logic in TSPC Example: logic inside the latch AND latch Topic 8-21
22 TSPC Register Topic 8-22
23 μ π latches: Poor man s TSPC Latch What is wrong with this TSPC Latch? Second attempt: Topic 8-23
24 μ π latches Final solution Topic 8-24
25 Pulse-Triggered Latches An Alternative Approach Ways to design an edge-triggered sequential cell: Master-Slave Latches Pulse-Triggered Latch Data L1 L2 L D Q D Q Data D Q Clk Clk Clk Clk Clk Topic 8-25
26 Pulsed Latches Topic 8-26
27 Pulsed Latches Hybrid Latch Flip-flop (HLFF), AMD K-6 and K-7 : Topic 8-27
28 Hybrid Latch-FF Timing Topic 8-28
29 Latch-Based Pipeline Topic 8-29
30 Non-Bistable Sequential Circuits Schmitt Trigger VTC with hysteresis Restores signal slopes Topic 8-30
31 Noise Suppression using Schmitt Trigger Topic 8-31
32 CMOS Schmitt Trigger Topic 8-32
33 Schmitt Trigger Simulated VTC Topic 8-33
34 CMOS Schmitt Trigger (2) Topic 8-34
35 Multivibrator Circuits Topic 8-35
36 Transition-Triggered Monostable Topic 8-36
37 Monostable Trigger (RC-based) Topic 8-37
38 Relaxation Oscillator Topic 8-38
39 Astable Multivibrators (Oscillators) Topic 8-39
40 Voltage Controller Oscillator (VCO) Topic 8-40
41 Differential Delay Element and VCO V o 2 V o 1 v 3 in 1 in 2 v 1 v 2 v 4 V ctrl delay cell 3.0 two stage VCO 2.5 V 1 V 2 V 3 V time (ns) simulated waveforms of 2-stage VCO Topic 8-41
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