Analog to Digital Converter. Last updated 7/27/18

Transcription

1 Analog to Digital Converter Last updated 7/27/18

2 Analog to Digital Conversion Most of the real world is analog temperature, pressure, voltage, current, To work with these values in a computer we must convert them into digital representations Three steps to this conversion Sampling Quantizing Encoding 2 tj

3 Sampling A to D Conversion takes a finite amount of time What if the input changes during this time? We must take a snapshot of the input Sample and Hold Vin Sample Vout 3 tj

4 Sampling Sampling is a kind of MODULATION Modulation systems are subject to Aliasing Fin < fs/2 Frequency 0 Fs: Nyquist rate LPF the input (anti-aliasing filter) Frequency 0 fs Frequency 0 fs 4 tj

5 Sampling Example of analog aliasing 5 tj

6 Sampling Example of digital aliasing html 6 tj

7 Quantizing In the A to D process we are converting an infinite resolution analog signal into a finite number of digital bits Converters use reference voltages to set the range of allowed input voltages - Vref-H, Vref-L Each binary step represents (V ref-h V ref-l ) / 2 n for an n bit conversion e.g. 0V 1V input converted to 3 bit digital value each binary step represents 0.125V since 000 typically represents 0.0V, 111 represents 0.875V 7 tj

8 Quantizing Quantization error looks like noise on the signal (Quantization Noise) Dynamic Range is a measure of signal to noise ratio. (SNR in db) For an AtoD the Dynamic Range is the measure of signal to Quantizing Noise ratio (SQNR) SQNR = 20 log 10 (2 n /(1/2 (-1/2)) = 20 log 10 2 n 8bit 48dB 10bit 60dB n steps Step Size rel to Vref-H - Vref-L SQNR (db) tj

9 Conversion Example 10 bit converter with VrefH=3.0V, VrefL=0.0V If the input is 2V, what is the output code VrefH-VrefL = 3V range 10 bit converter step size = range/2 10 = mV/step 2V / mV/step = 682 steps from VrefL tj

10 Successive Approximation A to D Uses an iterative process to determine the correct digital value for the analog input Requires Input (sample and held) A register to hold the current estimate of the digital value D to A converter to convert the digital estimate back to analog A comparator to determine if the estimate is above or below the actual input value Control logic to run the process Uses a binary search to find the nearest code value to the input value 10 tj

11 Successive Approximation A to D Vin + _ Clk CONTROL VrefH VrefL D to A Successive Approximation Register OUTPUT LATCH Output Code 11 tj

12 Successive Approximation A to D The control logic resets the SAR before each conversion The control logic then sets the msb The DtoA converts this to ½ the reference voltage The comparator tests to see if the input is above or below this value if above, the 1 in the msb stays if below, the msb is reset to zero The control logic then sets the msb-1 bit The DtoA converts this to the appropriate voltage level The comparator tests to see if the input is above or below this value if above, the 1 stays if below, the msb-1 bit is reset to 0 The control logic then sets the msb-n bit The DtoA converts this to voltage The comparator tests to see if the input is above or below this value if above, the 1 stays if below, the msb-n bit is reset to 0 Vin Clk D to A + _ CONTROL Successive Approximation Register Output Code VrefH 12 VrefL tj OUTPUT LATCH

13 Steps relative to VrefH-VrefL A to D Convertor 1V, 5 bit example Test to see if input is > or < midpoint if <, clear msb if >, set msb Input DtoA output SAR 13 Cycle 1 tj

14 Steps relative to VrefH-VrefL A to D Converter Test to see if input is > or < midpoint if <, clear msb if >, set msb Input DtoA output SAR 14 Cycle 1 tj

15 Steps relative to VrefH-VrefL A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SAR DtoA output 15 Cycle 1 Cycle 2 tj

16 Steps relative to VrefH-VrefL A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SAR DtoA output 16 Cycle 1 Cycle 2 tj

17 Steps relative to VrefH-VrefL A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SAR DtoA output 17 Cycle 1 Cycle 2 Cycle 3 tj

18 Steps relative to VrefH-VrefL A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SAR DtoA output 18 Cycle 1 Cycle 2 Cycle 3 tj

19 Steps relative to VrefH-VrefL A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SAR DtoA output 19 Cycle 1 Cycle 2 Cycle 3 Cycle 4 tj

20 Steps relative to VrefH-VrefL A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SAR DtoA output 20 Cycle 1 Cycle 2 Cycle 3 Cycle 4 tj

21 Steps relative to VrefH-VrefL A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SAR DtoA output 21 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 tj

22 Steps relative to VrefH-VrefL A to D Converter Test to see if input is > or < new midpoint if <, clear bit if >, set bit Input SAR DtoA output 22 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 tj

23 Example 1 Nbits: 4 VrefH: 3v VrefL: 0v D/A D/A Code Output Voltage HEX C E F tj

24 Example2 Nbits: 4 VrefH: 3v VrefL: 0v Input Voltage Output Code Hex C 2.85 F 3.3 F 24 tj

25 Example3 Nbits: 4 VrefH: 3v VrefL: 0v Input Output D/A Voltage Code Output Voltage Hex C F F Error Voltage Error Bits tj