CC-PC Gluecard Application and User's Guide

Transcription

1 CC-PC Gluecard Application and User's Guide LHCb Technical Note Issue: Public Revision: 1.0 / LPHE Created: 25 June 2003 Last modified: 1 April 2004 Prepared By: Flavio Fontanelli, Beat Jost, Giuseppe Mini, Niko Neufeld (LPHE EPFL), Ramy Abdel-Rahman, Kuno Rolli, Mario Sannino (INFN Genoa)

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3 CC-PC Gluecard Application and User's Guide Abstract This document describes the use of the Credit- Card PC (CC - PC) and the gluecard in a board design. Document Status Sheet Table 1 Document Status Sheet 1. Document Title: CC-PC Gluecard Application and User's Guide 2. Document Reference Number: [Document Reference Number] 3. Issue 4. Revision 5. Date 6. Reason for change P u b l i c April 2004 Rework D r a f t / 0 8 / First Draft page i

4 CC-PC Gluecard Application and User's Guide Table of Contents 1 INTRODUCTION USING THE CC- PC IN A B O A R D D E S I G N G LUECARD FEATURE PCB GUIDELINES M ECHANICS Dimensions of the Gluecard CC-PC and Gluecard relative positioning CONNECTORS Male Connector Female connector Ethernet Screen, keyboard and mouse (for evaluation boards only) S IGNALS TO ROUTE BETWEEN CC -P C AND GLUECARD S IGNALS REQUIRED BY THE GLUECARD S IGNALS AND ADDRESSES WITH SPECIF IC USE BY THE G LUECARD T HE LHCB CONNECTOR I2C JTAG Local bus Local Bus Address Map Reset P O W E R R E Q U I R E M E N T S CREDIT -C ARD P C G LUECARD A L H C B C O N N E C T O R P I N O U T S E E N F R O M G L U E C A R D B USE OF THE GLUECARD A N D T H E C C- P C O N T H E TELL1 BOARD B. 1 LOCAL B US T ERMINATION B. 2 LOCAL B US ADDRESS M AP REFERENCES page ii

5 CC-PC Gluecard Application and User's Guide 1 Introduction The CC-PC and the gluecard are used to control electronics boards used in the counting room (on the good side of the wall, away from radi at i o n ). This document tries to summarise hardware issues arising when designing a board around these two components. It is a summary of experience gained in designing proto-type and evaluation boards and of the following documents: and In the following it is assumed that the CC-PC is used in conjunction with the gluecard. Introduction page 1

6 2 Using the CC-PC in a board design In this chapter the design guide-lines for using a CC-PC and the gluecard in a board design are detailed. The carrier or mother board is simply referred to as the board in the following text. 2.1 Gluecard Feature The gluecard accompanying the CC-PC was designed by the Genoa section of Istituto Nazionale di Fisica Nucleare. A block diagram of the gluecard is shown in Figure 1. Figure 1 Block diagram of the gluecard Heart pieces of the module is a PCI9030 from PLX technologies [2] and a small FPGA (XCS05XL) from XILINX ([3] ). The PCI9030 acts as a bridge between the PCI bus of the CC-PC and a simpler parallel bus while the FPGA interfaces the I2C and JTAG controllers to the parallel bus of the PCI9030. The parallel bus is gated by bus switches towards the carrier card such that the gluecard can be isolated from the main board. This is useful to prevent interference of the main board s activity when the CC-PC is rebooting. It was also required that the gluecard should provide 3 JTAG master ports and 4 I2C master ports. The JTAG master ports are provided by a 3-port JTAG bridge (SCANSTA111) by National Semiconductors ([4] ) which is driven by a JTAG controller (SN74LVT8980A) from Texas Instruments ([5] ). page 2 Using the CC-PC in a board design

7 The I2C buses are provided through an I2C hub (PCA9516) driven by an I2C controller (PCF8584) both from Philips ([6] ). Programming of the XILINX FPGA is performed through the parallel port of the CC-P C. The MAX211 RS232 line driver/receiver from TI provided RS232-compatible signals that can be directly connected to a serial connector on the c arrier board. 2.2 PCB Guidelines Integrating a CC -PC to a board design must follow some general guidelines, which are listed in the following [1] : 10 x 100 nf filtering capacitors should be placed on the 5V line as close as possible to the power pins. Separate Power and ground planes should be used. Even though also 5V equipment is in principle supported by the CC-PC, only 3.3V equipment should be used. 5 to 10 x nf and 2 x 100 µf filtering capacitors should be places as near as possible to the 3.3 V power pins. Pull-up resistors should be of 10K type. If buffers are needed, it s recommended to use 74HC/HCT245/244, or 74ABT245/244. The CC-PC unused pins can be left open. It is not recommended to place components underneath the CC -P C. P C I-CLOCK should not be shared with another load. All clocks should be routed on internal layers, with minimum vias usage. Board impedance should be 55? ± 15 %. All clocks should have 1:2 width-to-space ratio. Using the CC-PC in a board design page 3

8 2.3 Mechanics P i n A1 Figure 2 Dimensions are in mil limet ers (see also [1] ). Top and Bottom view of the CC-PC (SM520PCX) Figure 3 Side view of the CC-PC. Note that LHCb will not use the fan nor the hood Dimensions of the Gluecard The dimensions of the gluecard are 88 x 48.5 mm 2 and t he distance between the two connectors is 30.0 mm (see Figure 4). page 4 Using the CC-PC in a board design

9 P i n A1 Figure 4 Schematics of the gluecard with the dimensions indicated. All dimensions are in mm. (top view, J3 and J4 are seen in transparency) Figure 5 Photograph of the gluecard PCB. Component side on the left and connector side on the right CC-PC and Gluecard relative positioning Figure 6 shows the relative positioning of the CC -PC and the gluecard on a carrier board. The gluecard is designed with the assumption that the connector J2* of the gluecard is a 1-1 image of the connector J2 of the CC-PC. It is therefore recommended the connectors of the gluecard have the same orientation as the connectors of the CC-P C since otherwise all signals would need to be Using the CC-PC in a board design page 5

10 crossed A1 A1 A1 A Gluecard CC-PC LHCb J2* J2 J Figure 6 Relative positioning of the CC-PC (right) and the gluecard (left) on a carrier board. The view is on the top of the modules, i.e. the connectors are below. All measures are in mm 2.4 Connectors The connectors used to plug the CC-PC on the board are MOLEX 240 pin connectors, which exactly match the Digital Logic SmartBus480 connectors. They are sur face mount connectors of mm pitch and 5 mm high and have the following specifications [1]. In case of mounting any component under the CC-PC, its height should not be more than 2 mm; however this is not recommended. 4 (female) connectors are needed per board (see 2.4.2). Connectors will be bought centrally please register your required quantity with either Beat Jost or Niko Neufeld. page 6 Using the CC-PC in a board design

11 Table 1 Connector properties Molex Parameter Condition Specification Material Contact: Housing: Electrical current: Voltage: Termination resistance: Insulation resistance: Mechanical Mating cycle: Connector mating force: Connector unmating force: Beryllium Copper. Thermoplast Molded. 0.5 AMP. 100 VAC. 20 m?. 500 M? N per contact. 0.4 N per contact Male Connector The male connector (MOLEX ) is mounted on the Gluecard [1]. Figure 7 Mechanical sketch on the MOLEX connector 1 Experience in using the evaluation board shows a much higher mating cycle, when care is taken. Using the CC-PC in a board design page 7

12 Table 2 Mechanical Dimensions of the MOLEX connector (see also Figure 7 A B C D mm mm mm mm Female connector Female connector (MOLEX ) is mounted on the Test board [7]. Figure 8 Mechanical sketch of the MOLEX connector page 8 Using the CC-PC in a board design

13 Table 3 Mechanical dimensions of the MOLEX connector (see also Figure 8) A B C D mm mm mm mm Ethernet Ethernet connection to the smart-card was implemented using a PulseJack RJ45 jack (J0035 from Pulse Engineering) with integrated magnetics. The differential output signals are terminated with 120? resistors. The RJ 45 jack is connected directly to the CC-PC connector J9 as shown below in Figure 9. CC-PC J9 A92 TX A93 A94 A TX100- RX100+ RX RJ nf 400 V 10 nf 50 V Figure 9 Connection of the RJ45 connector for Ethernet to the CCPC connector. Note that the resistors on the differential lines should be as close to the CC-PC connector as possible. 2 The Ethernet Media Access Controller (MAC) is a part of the CC-PC, it is an i82559 from Intel. The two differential RX and TX signals need to be connected to the RJ45 connector on the edge of the board. Ethernet requires a suitable magnetic filtering circuit as close as possible to the connector, which is the reason for using the recommended RJ45 connector with integrated magnetic filtering. The pin connectivity of the PulseJack J0035 RJ 45 connector is listed in T a b l e 4: 2 NOTE: The resistors are extremely important especially when operating with long cables. Using the CC-PC in a board design page 9

14 Table 4 Pin designation of the J0035 RJ 45 connector from PulseJack Pin No. Destination 1 RX RX Connect to PCB GND via 10 nf/50 Volt 4 PCB GND 5 PCB GND 6 Connect to PCB GND via 100 nf/1 kvolt 7 TX TX 100+ Figure 10 shows the dimensions and the mechanical specifications of the RJ 45 jack from front, side and back view, in addition to the size it occupies on the PCB. Figure 10 Mechanics of the recommended RJ45 connector page 10 Using the CC-PC in a board design

15 2.4.4 Screen, keyboard and mouse (for evaluation boards only) These connectors are implemented for testing and the y will not exist on a production board. The standard CC-PC will not even have support for graphics. The required parts and design gu ide-l i n e s for the connectors for these interfaces can be seen from the reference design. 2.5 Signals to route between CC-PC and gluecard The connection between the Gluecard and the CC-PC has been reduced to the minimum number of signals according their importance. C o n s e q u e n t l y from connector J1 (see also Figure 2 and Figure 6) of the CC-PC ONLY the Power and Ground pins are routed on the PCB as follows: Table 5 Signals of J1 on the CC-PC to be connected to the carrier PCB. PIN No. Description PIN No. Description A1 VCC B81 GND A57 GND B90 GND A66 GND B99 GND A88 GND B120 VCC A97 GND A106 GND 2.6 Signals required by the gluecard The complete list of signals of J2 of the CC-P C to be routed between the CC-PC and the gluecard can be found in Figure 1 1 and Figure 12. these signals are basically mirrored on connector J2* of the gluecard. Using the CC-PC in a board design page 11

16 Figure 11 Signals to be routed between the CC-PC J2 connector and the gluecard s J2* connector (rows 1-60) page 12 Using the CC-PC in a board design

17 Figure 12 Signals to be routed between the CC-PC J2 connector and the gluecard s J2* connector (rows ) Using the CC-PC in a board design page 13

18 2.7 Signals and Addresses with specific use by the Gluecard The gluecard uses a few signals internally: The signals of the printer port of the CC-P C GPIO7 and GPIO8 Chip-Select 0 (CS0), Local Bus Addresses 0x0 to 0x40 These signals should not be used by the electronics of the carrier card. The address decoding on the carrier card should make sure that the there is no clash with the addresses used by the gluecard (respect Chip-Select 0) page 14 Using the CC-PC in a board design

19 2.8 The LHCb Connector Table 6 describes the signals on the LHCb connector of the gluecard (see e.g. Figure 6) Table 6 Pin assignment of the LHCb connector as seen from the Motherboard Pin Name Class Direction Comment Pin Name Class Direction Comment A1 VCC(5V) POWER in B1 GND POWER A2 GND POWER B2 LAD16 PLX in/out A3 LAD0 PLX in/out B3 LAD17 PLX in/out A4 LAD1 PLX in/out B4 LAD18 PLX in/out A5 LAD2 PLX in/out B5 LAD19 PLX in/out A6 LAD3 PLX in/out B6 LAD20 PLX in/out A7 LAD4 PLX in/out B7 LAD21 PLX in/out A8 LAD5 PLX in/out B8 LAD22 PLX in/out A9 LAD6 PLX in/out B9 LAD23 PLX in/out A10 LAD7 PLX in/out B10 GND POWER A11 GND POWER B11 LAD24 PLX in/out A12 LAD8 PLX in/out B12 LAD25 PLX in/out A13 LAD9 PLX in/out B13 LAD26 PLX in/out A14 LAD10 PLX in/out B14 LAD27 PLX in/out A15 LAD11 PLX in/out B15 LAD28 PLX in/out A16 LAD12 PLX in/out B16 LAD29 PLX in/out A17 LAD13 PLX in/out B17 LAD30 PLX in/out A18 LAD14 PLX in/out B18 LAD31 PLX in/out A19 LAD15 PLX in/out B19 GND POWER A20 GND POWER B20 NC Reserved A21 ADS# PLX out B21 NC Reserved A22 LW/R# PLX out B22 NC Reserved A23 ALE PLX out B23 NC Reserved A24 NC Reserved B24 NC Reserved A25 READYi# PLX in B25 GND POWER A26 CS0# PLX out Chip Select Address Space 0 B26 TCK1 JTAG out (used internally) A27 CS1# PLX out Chip Select Address Space 1 B27 TDO1 JTAG in A28 NC Reserved B28 TMS1 JTAG out A29 GND POWER B29 TDI1 JTAG out A30 LRESETo Asserted with PCI PLX out # RST (don't use) B30 TRES1 JTAG out A31 BLAST# PLX out B31 GND POWER A32 LCLK PLX in B32 TCK2 JTAG out A33 LINTi1 PLX in B33 TDO2 JTAG in A34 GND POWER B34 TMS2 JTAG out A35 LINTi2 PLX in B35 TDI2 JTAG out A36 LA6 PLX out Local Bus Address B36 TRES2 JTAG out A37 LBE0# PLX out B37 GND POWER A38 LBE1# PLX out B38 GND POWER A39 LBE2# PLX out B39 GND POWER A40 LBE3# PLX out B40 GND POWER Important notice: the gluecard does not work, if there is no local bus clock (pin A32). The local bus clock has to be present when the BIOS scans the PCI bus, i.e. basically at power-up. Using the CC-PC in a board design page 15

20 A41 GND POWER B41 NC Reserved A42 LA7 PLX out Local Bus Address B42 NC Reserved A43 LA8 PLX out Local Bus Address B43 GND POWER A44 LREQ PLX in Local Bus Request B44 GND POWER A45 LGNT PLX out Local Bus Grant B45 VCC(5V) POWER in A46 LA11 PLX out Local Bus Address B46 I2C1D I2C in/out External Pull-ups A47 LA12 PLX out Local Bus Address B47 I2C1C I2C out External Pull-ups A48 GND POWER B48 GND POWER A49 GPIO4 PLX in/out or LA27 B49 I2C2D I2C in/out External Pull-ups A50 GPIO5 PLX in/out or LA26 B50 I2C2C I2C out External Pull-ups A51 GPIO6 PLX in/out or LA25 B51 GND POWER A52 GPIO7 PLX out Used By Gluecard Do NOT use B52 I2C3D I2C in/out External Pull-ups A53 GPIO8 PLX out Used By Gluecard Do NOT use B53 I2C3C I2C out External Pull-ups A54 LA18 PLX out Local Bus Address B54 GND POWER A55 GND POWER B55 I2C4D I2C in/out External Pull-ups A56 LA19 PLX out Local Bus Address B56 I2C4C I2C out External Pull-ups A57 LA20 PLX out Local Bus Address B57 GND POWER A58 RD# PLX out Read Strobe (active Low) B58 GND POWER A59 WR# PLX out Write Strobe (Active Local Bus B59 LA21 PLX out Low) Address A60 LA23 PLX out Local Bus Address B60 LA22 PLX out Local Bus Address A61 GND POWER B61 DCDV1 RS232 in A62 NC Reserved B62 RXDV1 RS232 in A63 NC Reserved B63 TXDV1 RS232 out A64 NC Reserved B64 DTRV1 RS232 out A65 NC Reserved B65 GND RS232 A66 GND POWER B66 DSRV1 RS232 in A67 VCC(5V) POWER in B67 RTSV1 RS232 out A68 NC Reserved B68 CTSV1 RS232 in A69 GND POWER B69 RTV1 RS232 in A70 Reseved LHCb in B70 GND POWER A71 Reserved LHCb in B71 NC Reserved A72 Reserved LHCb in B72 NC Reserved A73 Reserved LHCb in B73 NC Reserved A74 Reserved LHCb in B74 NC Reserved A75 Reserved LHCb in B75 NC Reserved A76 Reserved LHCb in B76 GND POWER A77 Reserved LHCb in B77 NC Reserved A78 Reserved LHCb out B78 NC Reserved A79 Reserved LHCb out B79 NC Reserved A80 Reserved LHCb out B80 NC Reserved page 16 Using the CC-PC in a board design

21 A81 Reserved LHCb out B81 NC Reserved A82 Reserved LHCb out B82 NC Reserved A83 Reserved LHCb out B83 NC Reserved A84 Reserved LHCb out B84 NC Reserved A85 Reserved LHCb out B85 GND POWER A86 GND POWER B86 NC Reserved A87 LA2 PLX out Local Bus Address B87 NC Reserved A88 LA3 PLX out Local Bus Address B88 NC Reserved A89 LA4 PLX out Local Bus Address B89 NC Reserved A90 GND POWER B90 VCC(5V) POWER in A91 3.3V POWER in B91 3.3V POWER in A92 GND POWER B92 VCC(5V) POWER in A93 GND POWER B93 GND POWER A94 GPIO0 PLX in/out or WAITo# B94 VCC(5V) POWER in A95 LA5 PLX out Local Bus Address B95 GND POWER A96 LA9 PLX out Local Bus Address B96 VCC(5V) POWER in A97 LA10 PLX out Local Bus Address B97 GND POWER A98 LA13 PLX out Local Bus Address B98 RESET# CORE in 3.3V Active Low A99 NC Reserved B99 GND POWER A100 NC Reserved B100 9 Reserved A101 VCC(5V) POWER in B101 GND POWER A102 GND POWER B102 GND POWER A103 GND POWER B103 GND POWER A104 VCC(5V) POWER in B V POWER in A105 GPIO1 PLX in/out or LLOCKo# B V POWER in A106 GPIO2 PLX in/out or CS2# B V POWER in A107 GPIO3 PLX in/out or CS3# B V POWER in A108 BTERM# PLX in B V POWER in A109 LA14 PLX out Local Bus Address B V POWER in A110 LA15 PLX out Local Bus Address B V POWER in A111 LA16 PLX out Local Bus Address B111 NC Reserved A112 GND POWER B112 GND POWER A113 GND POWER B113 VCC(5V) POWER in A114 GND POWER B114 GND POWER A115 LA17 PLX out Local Bus Address B115 TCK3 JTAG out A116 BCLKo PLX out Buffered PCI clock B116 TDO3 JTAG in A117 JPWR1 JTAG in JTAG1 Signaling Level B117 TMS3 JTAG out A118 JPWR2 JTAG in JTAG2 Signaling Level B118 TDI3 JTAG out A119 JPWR3 JTAG in JTAG3 Signaling Level B119 TRES3 JTAG out A120 GND POWER B120 GND POWER Usage Note: the pinout is that of the connector on the motherboard. As a guideline of the usage take for example pin B116 (TDO3). This pin has to be connected to the TDO signal of the last IC in the 3 rd JTAG chain. It is considered an Input of the connector I2C The I2C is a simple bi-directional bus consisting of two wires, serial data (SDA) and serial Clock (SCL) that c arry information between the devices connected to the bus. Each device is recognized unique address can work either as a transmitter and/or a receiver, depending on the Function of the device. The device which initiates a data transfer on the bus is considered the bus master, while all other devices connected to the bus are regarded as bus slave. Using the CC-PC in a board design page 17

22 Figure 13 The I2C bus The bus performs serial, 8-bit oriented, bidirectional data transfer, which can be made up to 100 KHz in the standard mode, up to 400 KHz in the fast mode, or 3.4 MHz in the high speed mode. The gluecard supports 100 khz mode only. As the number of devices and the bus length is restricted by the 400 pf capacitance of the I2C bus, a 5-channel I2C hub (PCA9516) is used on board which buffers the data and the clock lines, enabling five buses of the 400 pf as shown in figure. It can also be used to run different buses at 5V or 3.3V JTAG The Gluecard provides three JTAG buses each one using the following five dedicated signals, which must be provided on each chip that supports the standard: T R S T : Is a Test-R e s e t i n put which initializes and disables the test interface. TCK: Is the Test Clock input which controls the timing of the test interface independently from any system clocks. TCK is pulsed by the device controlling the test and not by the tested device. It can be pulsed at any frequency (up to a maximum of some MHz), or at varying rates. T M S : Is the Test Mode Select input which controls the transitions of the test interface state machine. TDI: Is the Test Data Input line, which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO: Is the Test Data Output line, which is used to serially output the data from the JTAG registers to the device controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. The normal organization of the test circuit on a board that incorporates several chips with JTAG support is to connect TRST, TCK, and TMS to e v e r y chip in parallel, and to connect TDO from one chip to TDI of the next in a single loop. This way the board presents a single test interface that has the same five signals discussed above. A simpler arrangement, for boards that have only a few chips with JTAG interfaces, is to provide one JTAG test-port for every such chip, and control the tests independently. page 18 Using the CC-PC in a board design

23 2.8.3 Local bus Local Bus helps PCI- Bus to communicate with non PCI devices. It s a 32 -bit bus 3 that can operate in both multiplexed or non-multiplexed mode, with memory, which can be programmed for 8-, 1 6 -, or 32-bit width. The gluecard only supports the non-multiplexed mode. It can operate at frequencies up to 60 MHz, and is asynchronous to the PCI clock. The PCI 9030 is the local bus master, which can transfer data between the local and internal registers and memories. The bus width depends on the local address space register settings. There are four address spaces and one default space from which space 0 is used internally. Figure 14 Local Bus Block Diagram Local Bus Arbitration The Gluecard only supports Single Master operation, i.e. the gluecard is the ONLY master on the local bus Local Bus Transaction The local bus is capable of performing four types of transaction which are listed as follows: Read W ri t e Read Burst Write Burst The address bus LA [27:2] drives a valid address and continues until the cycle ends. At same time the LAD [31:0] address data bus, derives a valid address onto LAD [27:0] one clock cycle prior to the address strobe assertion (ADS #). The data is then driven onto the LAD [31:0] data bus one clock cycle after the de- assertion of the ADS# and continues until the cycle ends. The READY# signal is then asserted to indicate that there is a valid read data on the bus to accept or a write da t a phase has been completed. Below there is a an example single cycle timing diagram [2]. 3 Note: the address space of the Local Bus is only 28 b i t s, i. e MB. Using the CC-PC in a board design page 19

24 Figure 15 Local Bus Single-Cycle Timing Diagram Local Bus Address Map The gluecard uses a few addresses in the PLX 9030 address space (24 bits) for addressing the I2C and JTAG controllers and the other control registers. The total address space needed is 64 Bytes. This address space is also associated to Chip Select 0 (CS0 #) of the PLX Most of the cards using the CC-PC with the gluecard will also use the LHCb quad Gigabit Ethernet plug-in card. This card has 64 kb of address space (16 bits) starting at 0 and reacts to Chip Select 2 (CS2) of the PLX The PLX 9030 features that the offset of an address window has to be a multiple of its size. To maximize the useful address space on the carrier board the following address mapping is specified Table 7 Local bus address ranges and decoding strategy Address Range S i z e C S 0 # C S 1 # C S 2 # Addressed Carrier Equipment Action 0x x0000 FFFF 64 kb Gluecard Ignore 0x x0001 FFFF 64kB GbEthernet Plug-in Ignore Table 7 demands that the carrier card should ignore all addresses which are blow 128 kb and/or when either CS0 or CS2 are asserted. 4 Note that the Chip selects of the PLX are active -l o w s i g n a l s. page 20 Using the CC-PC in a board design

25 2.8.5 Reset Its required that it must be possible to reset the controls interface of an electronics board without impairing the main function of the board. Resetting in this context means the action to bring the controls interface from any state into a known state. As an example, for a Credit-Card PC resetting means a hardware reboot by pulling the hardware reset line, similar to pushing the reset button on a desktop PC. The way to reset the ECS interface is to use the VME reset signal (SysReset# in VME terms 5 ), a 3.3Volt active-low signal which is part of the standard VME crates. For standard VME crates there is also a provision in the control interface of the VME crate to remotely activate this line through the fan-tray of the crate. This is true for the Cern standard 6U VME crates and also for the Cern standard 9U crates. Of course also a reset -button or similar can be used to activate the reset line. This is optional, whereas the connection to the VME reset line (or alike for the backplane in use) for remote reset is mandatory. Figure 16 shows schematically the connection of the VME Reset signal to the CC-PC and the Gluecard. ResetIn # LHCb/B98 ResetIn#/PowerGood J2/A79 SysReset # J1/C12 V M E C o n n e c t o r CC- PC GlueCard LHCb J2* J 2 J 1 Figure 16 Connection of the VME SysReset# line to the Gluecard and the CC-PC. The Line is connected to the ResetIn pin (B98) of the LHCb specific connector (J5) on the Gluecard and to the ResetIn#/PowerGood pin (A79) on connector J2 of the CC-PC 5 This signal is present on the standard VME backplane. In cases where a special backplane is used the position of this signal can change. The signal is, for Cern standard crates, driven by the crate fan tray. Using the CC-PC in a board design page 21

26 3 Power Requirements 3.1 Credit-Card PC The credit -card PC needs only +5 Volts as supply voltage. At this voltage it draws approx. 1 A, hence a power consumption of ~5 W. 3.2 Gluecard The power and voltage requirements of the gluecard are as follows 1 W at 3.3 Volts 200 mw at 5 Volts No other voltages are needed. page 22 Power Requirements

27 A LHCb Connector Pinout seen from Gluecard The following tables give the pinout of the LHCb connector as it s seen from the gluecard. Table 8 Pinout of the LHCb specific connector as seen from the gluecard Pin Name Class Direction Comment Pin Name Class Direction Comment A1 VCC(5V) POWER out B1 GND POWER A2 GND POWER B2 LAD16 PLX in/out A3 LAD0 PLX in/out B3 LAD17 PLX in/out A4 LAD1 PLX in/out B4 LAD18 PLX in/out A5 LAD2 PLX in/out B5 LAD19 PLX in/out A6 LAD3 PLX in/out B6 LAD20 PLX in/out A7 LAD4 PLX in/out B7 LAD21 PLX in/out A8 LAD5 PLX in/out B8 LAD22 PLX in/out A9 LAD6 PLX in/out B9 LAD23 PLX in/out A10 LAD7 PLX in/out B10 GND POWER A11 GND POWER B11 LAD24 PLX in/out A12 LAD8 PLX in/out B12 LAD25 PLX in/out A13 LAD9 PLX in/out B13 LAD26 PLX in/out A14 LAD10 PLX in/out B14 LAD27 PLX in/out A15 LAD11 PLX in/out B15 LAD28 PLX in/out A16 LAD12 PLX in/out B16 LAD29 PLX in/out A17 LAD13 PLX in/out B17 LAD30 PLX in/out A18 LAD14 PLX in/out B18 LAD31 PLX in/out A19 LAD15 PLX in/out B19 GND POWER A20 GND POWER B20 NC Reserved A21 ADS# PLX in B21 NC Reserved A22 LW/R# PLX in B22 NC Reserved A23 ALE PLX in B23 NC Reserved A24 NC Reserved B24 NC Reserved A25 READYi# PLX out B25 GND POWER A26 CS0# PLX in Chip Select Address Space 0 B26 TCK1 JTAG in (used internally) A27 CS1# PLX in Chip Select Address Space 1 B27 TDI1 JTAG out A28 NC Reserved B28 TMS1 JTAG in A29 GND POWER B29 TDO1 JTAG in A30 LRESETo# PLX in Asserted with PCI RST (don't use) B30 TRES1 JTAG in A31 BLAST# PLX in B31 GND POWER A32 LCLK PLX out B32 TCK2 JTAG in A33 LINTi1 PLX out B33 TDI2 JTAG out A34 GND POWER B34 TMS2 JTAG in A35 LINTi2 PLX out B35 TDO2 JTAG in A36 LA6 PLX in Local Bus Address B36 TRES2 JTAG in A37 LBE0# PLX in B37 GND POWER A38 LBE1# PLX in B38 GND POWER A39 LBE2# PLX in B39 GND POWER A40 LBE3# PLX in B40 GND POWER LHCb Connector Pinout seen from Gluecard page 23

28 A41 GND POWER B41 NC Reserved A42 LA7 PLX in Local Bus Address B42 NC Reserved A43 LA8 PLX in Local Bus Address B43 GND POWER A44 LREQ PLX out Local Bus Request B44 GND POWER A45 LGNT PLX in Local Bus Grant B45 VCC(5V) POWER out A46 LA11 PLX in Local Bus Address B46 I2C1D I2C in/out External Pull-ups A47 LA12 PLX in Local Bus Address B47 I2C1C I2C in External Pull-ups A48 GND POWER B48 GND POWER A49 GPIO4 PLX in/out or LA27 B49 I2C2D I2C in/out External Pull-ups A50 GPIO5 PLX in/out or LA26 B50 I2C2C I2C in External Pull-ups A51 GPIO6 PLX in/out or LA25 B51 GND POWER A52 GPIO7 PLX in A53 GPIO8 PLX in Used By Gluecard Do NOT use Used By Gluecard Do NOT use B52 I2C3D I2C in/out External Pull-ups B53 I2C3C I2C in External Pull-ups A54 LA18 PLX in Local Bus Address B54 GND POWER A55 GND POWER B55 I2C4D I2C in/out External Pull-ups A56 LA19 PLX in Local Bus Address B56 I2C4C I2C in External Pull-ups A57 LA20 PLX in Local Bus Address B57 GND POWER A58 RD# PLX in Read Strobe (active Low) B58 GND POWER A59 WR# PLX in Write Strobe (Active Low) B59 LA21 PLX in Local Bus Address A60 LA23 PLX in Local Bus Address B60 LA22 PLX in Local Bus Address A61 GND POWER B61 DCDV1 RS232 out A62 NC Reserved B62 RXDV1 RS232 out A63 NC Reserved B63 TXDV1 RS232 in A64 NC Reserved B64 DTRV1 RS232 in A65 NC Reserved B65 GND RS232 A66 GND POWER B66 DSRV1 RS232 out A67 VCC(5V) POWER out B67 RTSV1 RS232 in A68 NC Reserved B68 CTSV1 RS232 out A69 GND POWER B69 RTV1 RS232 out A70 Reseved LHCb out B70 GND POWER A71 Reserved LHCb out B71 NC Reserved A72 Reserved LHCb out B72 NC Reserved A73 Reserved LHCb out B73 NC Reserved A74 Reserved LHCb out B74 NC Reserved A75 Reserved LHCb out B75 NC Reserved A76 Reserved LHCb out B76 GND POWER A77 Reserved LHCb out B77 NC Reserved A78 Reserved LHCb in B78 NC Reserved A79 Reserved LHCb in B79 NC Reserved A80 Reserved LHCb in B80 NC Reserved page 24 LHCb Connector Pinout seen from Gluecard

29 A81 Reserved LHCb in B81 NC Reserved A82 Reserved LHCb in B82 NC Reserved A83 Reserved LHCb in B83 NC Reserved A84 Reserved LHCb in B84 NC Reserved A85 Reserved LHCb in B85 GND POWER A86 GND POWER B86 NC Reserved A87 LA2 PLX in Local Bus Address B87 NC Reserved A88 LA3 PLX in Local Bus Address B88 NC Reserved A89 LA4 PLX in Local Bus Address B89 NC Reserved A90 GND POWER B90 VCC(5V) POWER out A91 3.3V POWER out B91 3.3V POWER out A92 GND POWER B92 VCC(5V) POWER out A93 GND POWER B93 GND POWER A94 GPIO0 PLX in/out or WAITo# B94 VCC(5V) POWER out A95 LA5 PLX in Local Bus Address B95 GND POWER A96 LA9 PLX in Local Bus Address B96 VCC(5V) POWER out A97 LA10 PLX in Local Bus Address B97 GND POWER A98 LA13 PLX in Local Bus Address B98 RESET# CORE out 3.3V Active Low A99 NC Reserved B99 GND POWER A100 NC Reserved B100 9 Reserved A101 VCC(5V) POWER out B101 GND POWER A102 GND POWER B102 GND POWER A103 GND POWER B103 GND POWER A104 VCC(5V) POWER out B V POWER out A105 GPIO1 PLX in/out or LLOCKo# B V POWER out A106 GPIO2 PLX in/out or CS2# B V POWER out A107 GPIO3 PLX in/out or CS3# B V POWER out A108 BTERM# PLX out B V POWER out A109 LA14 PLX in Local Bus Address B V POWER out A110 LA15 PLX in Local Bus Address B V POWER out A111 LA16 PLX in Local Bus Address B111 NC Reserved A112 GND POWER B112 GND POWER A113 GND POWER B113 VCC(5V) POWER out A114 GND POWER B114 GND POWER A115 LA17 PLX in Local Bus Address B115 TCK3 JTAG in A116 BCLKo PLX in Buffered PCI clock B116 TDI3 JTAG out A117 JPWR1 JTAG out JTAG1 Signaling Level B117 TMS3 JTAG in A118 JPWR2 JTAG out JTAG2 Signaling Level B118 TDO3 JTAG in A119 JPWR3 JTAG out JTAG3 Signaling Level B119 TRES3 JTAG in A120 GND POWER B120 GND POWER LHCb Connector Pinout seen from Gluecard page 25

30 B Use of the Gluecard and the CC-PC on the Tell1 Board The Gluecard and the CC -PC is used on the Tell1 -board designed for LHCb. In this appendix we show a few specific implementation issues used in the design of the Tell1 board. B.1 Local Bus Termination All Local Bus lines should be terminated with an RC network to ground as shown in Figure 17 LHCb Connector Local Bus Line Bus End 47W 47W 22 pf 22 pf Figure 17 RC Termination network of the local bus lines. The RC network should be located as close as possible to the extremities of the bus. B.2 Local Bus Address Map Table 9 shows the address map of the local bus as implemented on the Tell1 board. Table 9 Local bus address ranges and decoding strategy Address Range S i z e C S 0 # C S 1 # C S 2 # Addressed Carrier Equipment Action 0x x0000 FFFF 64 kb Gluecard Ignore 0x x0001 FFFF 64kB GbEthernet Plug-in Ignore 0x x0FFF FFFF 128 kb to 256 MB Carrier Card Access Chip Select CS1 is associated with the maximum address space of the PLX Local Bus (256 MB). However t he Tell1 address deco d i n g ignores addresses below 128 kb where also CS0 or CS2 are set. page 26 Use of the Gluecard and the CC-PC on the Tell1 Board

31 References [1] [2] PLX PCI9030 Data Book. ( [3] [4] [5] [6] [7] References page 27