GSM TELEPHONE SGH-D600 CONTENTS GSM TELEPHONE. 1. Specification. 2. Circuit Description. 3. Exploded Views and Parts List. 4. Electrical Parts List

Transcription

1 GSM TELEPHONE SGH-D600 GSM TELEPHONE CONTENTS 1. Specification 2. Circuit Description 3. Exploded Views and Parts List 4. Electrical Parts List 5. Block Diagrams 6. PCB Diagrams 7. Flow Chart of Troubleshooting

2 This Service Manual is a property of Samsung Electronics Co.,Ltd. Any unauthorized use of Manual can be punished under applicable International and/or domestic law. csamsung Electronics Co.,Ltd. September Printed in Korea. Code No.: GH A BASIC.

3 1-1. GSM General Specification GSM850 phase1 GSM900 Phase 1 EGSM 900 Phase 2 DCS1800 Phase 1 PCS1900 Freq. Band[MHz] Uplink/Downlin k 824~ ~ ~ ~ ~ ~ ~ ~ ~ ~1990 ARFCN range 128~251 1~124 0~124 & 975~ ~ ~810 Tx/Rx spacing 45MHz 45MHz 45MHz 95MHz 80MHz Mod. Bit rate/ Bit Period kbps 3.692us kbps 3.692us kbps 3.692us kbps 3.692us kbps 3.692us Time Slot Period/Frame Period 576.9us 4.615ms 576.9us 4.615ms 576.9us 4.615ms 576.9us 4.615ms 576.9us 4.615ms Modulation 0.3GMSK 0.3GMSK 0.3GMSK 0.3GMSK 0.3GMSK MS Power 33dBm~13dBm 33dBm~13dBm 33dBm~5dBm 30dBm~0dBm 30dBm~0dBm Power Class 5pcl ~ 15pcl 5pcl ~ 15pcl 5pcl ~ 19pcl 0pcl ~ 15pcl 0pcl ~ 15pcl Sensitivity -102dBm -102dBm -102dBm -100dBm -100dBm TDMA Mux Cell Radius 35Km 35Km 35Km 2Km -

4 1-2. GSM TX power class TX TX TX TX Power control GSM850 Power control GSM900 Power control DCS1800 ower control PCS1900 level level level level 5 33±3 dbm 5 33±2 dbm 0 30±2 dbm 0 30±2 dbm 6 31±3 dbm 6 31±2 dbm 1 28±3 dbm 1 28±3 dbm 7 29±3 dbm 7 29±2 dbm 2 26±3 dbm 2 26±3 dbm 8 27±3 dbm 8 27±2 dbm 3 24±3 dbm 3 24±3 dbm 9 25±3 dbm 9 25±2 dbm 4 22±3 dbm 4 22±3 dbm 10 23±3 dbm 10 23±2 dbm 5 20±3 dbm 5 20±3 dbm 11 21±3 dbm 11 21±2 dbm 6 18±3 dbm 6 18±3 dbm 12 19±3 dbm 12 19±2 dbm 7 16±3 dbm 7 16±3 dbm 13 17±3 dbm 13 17±2 dbm 8 14±3 dbm 8 14±3 dbm 14 15±3 dbm 14 15±2 dbm 9 12±4 dbm 9 12±4 dbm 15 13±3 dbm 15 13±2 dbm 10 10±4 dbm 10 10±4 dbm 16 11±5 dbm 16 11±3 dbm 11 8±4dBm 11 8±4dBm 17 9±5 dbm 17 9±3dBm 12 6±4 dbm 12 6±4 dbm 18 7±5 dbm 18 7±3 dbm 13 4±4 dbm 13 4±4 dbm 19 5±5 dbm 19 5±3 dbm 14 2±5 dbm 14 2±5 dbm 15 0±5 dbm 15 0±5 dbm

5 2-1. SGH-D600 RF Circuit Description RX PART - FEM(F100 SWICHPLEXER) Switching Tx, Rx path for GSM850, GSM900, DCS1800 and PCS1900 by logic controlling. - ANTENNA SWITCH Control Logic (F100) Truth Table VC_1 VC_2 VC_3 GSM850/900 Rx Mode L L L DCS Rx Mode L L L PCS Rx Mode H GSM Tx Mode (GSM850/900) H L L DCS/PCS Tx Mode L H L - FILTER To convert Electromagnetic Field Wave to Acoustic Wave and then pass the specific frequency band. - GSM850 FILTER (L113,C133,C134,C135) For filtering the frequency band between 869 ~ 894 MHz. - GSM900 FILTER (L106,C122,C123,C124) For filtering the frequency band between 925 ~ 960 MHz. - DCS FILTER (L108,L109,C129,C130) For filtering the frequency band 1805 and 1880 MHz. - PCS FILTER (L110,L111,C131,C132) For filtering the frequency band 1930 and 1990 MHz. - VC-TCXO (U102) To generate the 26MHz reference clock to drive the logic and RF. After additional process, the reference clock applies to the U100 Rx IQ demodulator and Tx IQ modulator. The oscillator for RX IQ demodulator and Tx modulator are controlled by serial data to select channel and use fast lock mode for GPRS high class operation. - TRANSCEIVER (U100) This chip fully integrated GSM GPRS quad-band transceiver with transmit baluns, loop filters and most of the passive component in it. And also fully integrated fractional N RF synthesizer with AFC control possibility, RF VCO with integrated supply regulator. semi integrated reference oscillator with integrated supply regulator. RF Receiver front-end amplifies the GSM850, E-GSM900, DCS1800 and PCS1900 aerial signal, convert the chosen channel down to a low IF of 100kHz. In IF section, further amplifies the wanted channel output level to the desired value and rejects DC TX PART The transmitter is fully differential using a direct up conversion architecture. It consists of a signal side band power up mixer. Gain is controlled by 6 db via 3-wire serial bus programing. The fully integrated VCO and power mixer achieve LO suppression, quadrature phase error, quadrature amplitude balance and low noise floor specification. Output matching/balun components drive a standard 50 ohms single ended load.

6 2-2. Baseband Circuit description of SGH-D PCF50603 (U400) - Power Management Eight low-dropout regulators designed specifically for GSM applications power the terminal and help ensure optimal system performance and long battery life. A programmable boost converter provides support for 1.8V, 3.0V SIMs, while a self-resetting, electronically fused switch supplies power to external accessories. Ancillary support functions, such as RTC module and High Voltage Charge pump, Clock generator, aid in reducing both board area and system complexity. I2C BUS serial interface provides access to control and configuration registers. This interface gives a microprocessor full control of the PCF50603 and enables system designers to maximize both standby and talk times. Supervisory functions. including a reset generator, an input voltage monitor, and a temperature sensor, support reliable system design. These functions work together to ensure proper system behavior during start-up or in the event of a fault condition(low microprocessor voltage, insufficient battery energy, or excessive die temperature). - Clock Generator The Clock Generator (CG) generates all clocks for internal and external usage. The khz crystal oscillator provides an accurate low clock frequency for the PCF50603 and other circuitry LCD LCD is consisted of main LCD(color 262K TFT LCD). Chip select signals in the U301, LCD_MAIN_CS, can enable LCD. BACKLIGHT signal enables white LED of main LCD. 16-bit data lines(ld(0)~ld(15)) transfers data and commands to LCD. Data and commands use "RS" signal. If this signal is high, Inputs to LCD are commands. If it is low, Inputs to LCD are data. The signal which informs the input or output state to LCD, is required. But this system is not necessary this signal. So "L_WRB" signal is used to write data or commands to LCD. Power signals for LCD are "VDD_IO_HIGH" Key This is consisted of key interface pins KEY_ROW(0:4) and KEY_COL(0:4) in PCF5212EL1. These signals compose the matrix. Result of matrix informs the key status to key interface in the PCF5212EL1. Power on/off key is seperated from the matrix. So power on/off signal is connected with PCF50603 to enable PCF Key LED is consisted of six white LEDsforsubkeyandtwelvewhiteLEDsformainkey. White LED for sub key use the VBAT voltage. "SLIDER_KEY_ON" signal enables Transistor for sub key backlight. Main key LED use the 3.3V LDO for a supply voltage. KEY_LED_ON signal enables eight white LED. "FLIP" informs the status of slide (open or closed) to the PCF5213EL1. This uses the hall effect IC, EM-1681 A magnet under LCD enables EM-1681.

7 EMI ESD Filter This system uses the EMI ESD filter, U500 to protect noise from IF CONNECTOR part IF connetor It is 18-pin connector. They are designed to use VBAT, V_EXT_CHARGE, USB_D+, +VBUS, USB_D-, TXD1, RXD1, AUX_ON, EXT1, EXT2, HFK_SPK, HFK_MIC and GND. They connected to power supply IC, microprocessor and signal processor IC Battery Charge Management A complete constant-current/constant-voltage linear charger for single cell lithium-ion batteries. If TA connected to phone, "V_EXT_CHARGE" enable charger IC and supply current to battery. When fault condition caused, "CHG_ON" signal level change low to high and charger IC stop charging process Audio HFR_P and HFR_N from PCF5212El1 are connected to the main speaker via analog switches. MIC_P and MIC_N are connected to the main MIC as well. EAR1 is the source of External Speaker. AK4642 is 16-bit stereo audio CODEC with a built-in microphone - Amplifier and Headphone - Amplifier. I2S signals from CL8522S5 are decoded with audio analog signals. SAPA1D2-24ELP amplify these signals and deliver to stereo speakers Memory This system uses Samsung's memory, KBH10PD00M-D414. The KBH10PD00M is a Multi Chip Package Memory which combines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory and two 1Gbit OneNAND Flash and 256Mbit Synchronous Burst UtRAM. It has 16 bit data line, HD[1~16] which is connected to PCF5212 and CL8522S5, also has 24 bit address lines, HA[1~24]. There are 3 chip select signals, CS0n_FLASH, CS4n_NAND, and CS1n_RAM. In the Wrting process, WEn is fallen to low and it enables writing process to operate. During reading process, OEn is fallen to low and it enables reading process to operate. Each chip select signals in the PCF5212 choose different memories.

8 PCF5212EL1 The PCF5212EL1 is mainly composed of embeded DSP and ARM core. The DSP subsystem includes the Saturn DSP core with embedded RAM and ROM, and a set of peripherals. It has 24kx16 bits PRAM, 104k*16 bits, 32k*16 XYRAM and 63k*16 XYROM in the DSP. The ARM946E-S consists of an ARM9E-S processor core, 8 kbyte instruction cache and 8 kbyte data cache, tghtly-coupled ITCM(Instruction Tightly Coupled Memory) and DTCM(Data Tightly Coupled Memory) memories, a memory protection unit, and an AMBA(Advanced Microcontroller Bus Architecture) AHB(Advanced High-performance Bus) bus interface with a write buffer. HD(0:15), data lines and HA(0:23), address lines are connected to KBJ10KB00M (memory), MV319DNQ (image dsp) and YMU765 (melody IC). It has 64 kbyte SC RAM (0.5 Mbit) and 32 kbyte SC program ROM for bootstrap loader in the ARM core. HD(0:15), data lines and HA(0:23), address lines are connected to memory and YMU765 to communicate. MV319DNQ(Camera DSP Chip) controls the communication between ARM core and DSP core. OEn, WEn control the access of memory. KROW, and KCOL recognize the key string input status. It has J-TAG control pins (TDI/TDO/TCK) for ARM and DSP core. J-SEL signal controls different access to ARM and DSP core. ADC(Analog to Digital Convertor) receives the condition of temperature, battery type and battery voltage TCO-5888T (26MHz) This system uses the 26MHz TCXO, TCO-5871U, Toyocom. AFC control signal form PCF5212 controls frequency from 26MHz x-tal. It generates the clock frequency. This clock is connected to PCF5212, YMU765 and UAA Multimedia Chip (CL8522S5) CL8522S5 is the hardware based MPEG4 CODEC is available to capture the video signal of up to CIF Resolution (352X288, at 30FPS). CL8522S5 directly transmits and previews the RGB Data to the LCD graphic memory by processing the sensor output data. It can save the raw RGB data up to 1600x1200 into its image buffer and allows the host processor to download with scalable sized compressed data.

9 3-1. Exploded View QFR01 QMW01 QCR32 QKP01 QFU01 QCR12 QCA02 QKP02 QAU01 QMO01 QVK01 QME01 QMP01 QCA01 QLC01 QCR32 QME02 QSP02 QSP01 QAN06 QAN05 QAN02 QFL01 QCR26 QSC11 QCK01 QRE01 QIF01 QHI01 QVO01 QRF01 QCR31 QBA01 QPC01

10 3-2. Parts List Location No Description Sec Code QAN05 MEC-INTENNA CONN RUBBER;SGH-D600,EU, GH A QAN06 MEC-INTENNA CONN RUB SM;SGH-D600,EU, GH A QAU01 AUDIO-RECEIVER;32ohm,109dB±2dB,11X QBA01 BATTERY-900MAH,BLK,ENG,M;BST4389BE,S GH A QCA01 UNIT-CAMERA;SGH-D600,IC04001AA,-,EU, GH A QCA02 UNIT-CAMERA KEY;SGH-D600,H/K F.P.C A GH A QCK01 PMO-CAMERA KEY;SGH-D600,PC(K2261),BL GH A QCR12 SCREW-MACHINE;PH,+,M1.4,L2.5,ZPC(BLK QCR26 SCREW-MACHINE;CH,+,M1.7,L3,ZPC(BLK), QCR31 SCREW-MACHINE;CH,+,M1.7,L3,ZPC(BLK), QFR01 MEC-FRONT COVER;SGH-D600,EU,-,-,-,-, GH A QFU01 MEC-SLIDE UPPER;SGH-D600,EU,-,-,-,-, GH A QIF01 PMO-IF COVER;SGH-D600,PC+UREATHANE,B GH A QKP01 MEC-KEYPAD MAIN;SGH-D600,EU,-,-,-,-, GH A QKP02 MEC-KEYPAD SUB;SGH-D600,EU,-,-,-,-,C GH A QLC01 LCD-LCD MODULE;LTS200QV-F03-0,SGH-D6 GH A QME01 UNIT-METAL DOME;SGH-D600,-,-,EU,12V, GH A QME02 UNIT-KEY PAD;SGH-D600,HUW GH A QMO01 MOTOR DC-SGHZ130;DMJBRV83CG,SGH-Z130 GH B QMP01 PBA MAIN-SGHD600;SGH-D600,EU,EU,PBA GH A QMW01 PCT-WINDOW MAIN;SGH-D600,ACRYL,TRP,- GH A QPC01 PCB-FPCB;SGH-D600,POLYIMIDE,3L,-,0.0 GH A QRE01 MEC-REAR COVER;SGH-D600,EU,-,-,-,-,C GH A QRF01 MPR-R/F CAP;SGH-D600,PC SHEET,P5.4XT GH A QSC11 RMO-LOWER SCREW CAP;SGH-D600,CR RUBB GH A QVK01 UNIT-VOLUME KEY;SGH-D600,SGH-D600 V/ GH A QVO01 PMO-VOLUME KEY;SGH-D600,PC(K2261),BL GH A QSP02 UNIT-SPEAKER MODULE;SGH-D600,SS-SGH- GH A QSP01 SPEAKER;0.7W,8.0ohm,87dB±2dB,700Hz, QAN02 INTENNA-SGHD600;EWPADG006A,SGH-D600, GH A QFL01 MEC-SLIDE LOWER;SGH-D600,EU,-,-,-,-, GH A QCR32 SCREW-MACHINE;CH,+,M1.4,L2,ZPC(BLK), QHI01 MEC-HINGE MODULE;SGH-D600,EU,-,-,-,- GH A

11 Description Sec Code BAG PE;LDPE,T0.05,W80,L180,TRP,-, CBF INTERFACE-AV CABLE;SGH-D600,10 p CBF INTERFACE-DATA LINK CABLE;SGH-D6 ADAPTOR-SGHD500 BLK;TAD137EBE,SGH-D5 S/W CD-SAMSUNG PC STUDIO;SGH-D600,SG UNIT-EAR PHONE(BLK);SGH-D600,AEP421S LABEL(P)-WATER SOAK;COMM,NORGE,100G, MANUAL-WEEE CARD;COMM,SEC,ENGLISH,UN LABEL(R)-MAIN(EU);SGH-D600,EU,POLYES MANUAL-USER;SGH-D600,XEF,FRENCH,FRAN BOX(P)-SLIPCASE(EU);SGH-D600,SC300+S CUSHION-CASE(1-2);SGH-D600,PULP,T0.8 BOX(P)-UNIT(EU);SGH-D600,SC300g+S120 ICT-BATT LOCKER SPRING;SGH-D600,STS3 PMO-BATTERY LOCKER;SGH-D600,PC(K2261 MPR-TAPE BOHO MAIN WIN A;SCH-X850,3M MPR-BOHO VINYL IF;SCH-X699,3M 4187C, MPR-BOHO VINYL S/U (R);SGH-D500,STA MPR-MAIN CON INSULATION;SGH-D600,SP6 MPR-MAIN PBA DOWN L IN;SGH-D600,SP65 MPR-MAIN PBA DOWN R IN;SGH-D600,SP65 MPR-MAIN PBA UP L IN;SGH-D600,SP65,8 MPR-MAIN PBA UP R IN;SGH-D600,SP65,9 MPR-TAPE B TO B CON IN;SGH-D600,SP65 MPR-TAPE B TO B CON EMI;SGH-D600,DTF MPR-SUB CON INSLATION;SGH-D600,SP65, MPR-TAPE SUB CON EMI;SGH-D600,DTF-10 MPR-TAPE BASE BTB LA;SGH-D600,TAST49 MPR-BOHO VINYL MAIN WIN;SGH-D600,ST5 MPR-BOHO VINYL R/W LENS;SGH-D600,ST5 MPR-B TO B CON SIDE EMI;SGH-D600,DTF MPR-TAPE IF HOLDER;SCH-V740,FABRIC T MPR-TAPE BASE BTB;SGH-D600,TASA 4962 AS-INTENNA FRONT GASKET;SGH-D600,-,G AS-INTENNA REAR GASKET;SGH-D600,-,GA GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A GH A

12 3-3. Test Jig (GH A) RF Test Cable (GH A) Test Cable (GH C) Serial Cable Power Supply Cable DATA CABLE (GH A] TA (GH A) TV-OUT Cable (GH A)

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17 5-1. RF Solution Block Diagram HD155165BPEB (U100) GSM850 Rx GSM900 Rx UAA3536HN/C3 (U100) I DCS Rx QUAD RF Connector (CN100) PCS Rx Q VREG DIV FEM (F100) GSM/DCS/PCS ~ CP FracN DIV PFD VREG ~ VCTCXO (U102) PCF5212-3I 1:1/2 VC1 VC2 VC3 Rx(G/D) Rx(PCS) Tx(GSM) Tx(D/P) DCS/PCS Tx VC1 VC2 VC3 L L L L L H H L L L H L GSM Tx PAM (U103) GSM Tx CP PFD DIV QUAD IF Freq. 60/114 MHz fmod. DATA CLK EN RXON TXON SYNON FESWON APC Block DCS/PCS Tx

18 5-2. Base Band Solution Block Diagram

19 6-1. PCB Top Diagram

20 6-2. PCB Bottom Diagram

21 7-1. Power On

22 MICBIAS _RSTHC _IRQ SIMIOHC SIMCKHC _SIMRSHC PWREN1 PWREN2 CLK32K SDA SCL _REC1 OSCO OSCI _ONKEY REFC VINT VSAVE VBAT VCHG CHGDRV CHGCUR/BATMAX CPVDD CPVBAT ONKEYN C406 C407 C409 R404 OSC400 C408 Typical 3.7V VBAT POS C410 BU_RST BAT400 V400 C411 C412 NEG 2.8V +VDD_RX_TX R405 0 C V R406 +VCC_SYN C415 SCP V +VDD_IMAGE 2.6V +AVDD 2.6V +AVDD_HFA C416 C417 C RF2VDD 23 RF12VBAT 22 RF1VDD 21 D1VDD 20 LPD1VBAT 19 LPVDD 18 HCVBAT 17 HCVDD 16 D2VDD 15 IOD2VBAT 14 IOVDD 13 _REC2 U400 SCN 38 D3VDD 39 SIMD3VBAT 40 SIMVCC 41 SIMIOCD 42 SIMCKCD _SIMRSCD SIMEN GPO3 GPO2 47 GPO1 48 GND 49 GND 50 GND 51 GND 52 NC 53 NC 54 RESET_BT 2.9V VDD_IO_HIGH C V +VDD_IO_LOW C V MIC_BIAS R408 C426 RSTON IT_PMU SIMIO

23 Typical 3.7V VBAT L401 U402 1 IN LX 5 L402 +VDD_GSM_CORE 1.8V +VDD_IO_HIGH 2 GND 3 _SHDN FB 4 R401 C401 C402 C403 R403 R102 U100 H6 J3 B6 A8 A6 J2 B3 G8 A3 E9 A9 A7 VCCTXVCOG VCCTXVCO VCCRFVCO VCCRFSYN VCCRFLO VCCOPLL VCCMIX VCCMASH VCCLNA VCCCLK VCCBUF VCCBB DIVON DCSLNAIB DCSLNAI DCSGSM1GND CLKOUT2 CLKOUT1 CLK2CONT CLK CAPQB CAPQ CAPIB D8 D1 C1 D2 D9 G9 C8 F8 B5 A5 B4 R103 TP100 C120 R105 R106 C116 DCS_RX_P DCS_RX_N D_REF_CLK RF_CLK

24 7-2. Initial

25 U15 P15 V17 N17 L12 P18 J14 R14 R15 HDP0 HDP1 HDP2 HDP3 HDP4 HDP5 HDP6 HDP7 RSTON IT_PMU SIMIO +VDD_IO_HIGH R211 R212 I2C Communication SCL SDA HA(23) WEN OEN CS3n_IMAGE CS1n_RAM CS0n_FLASH BE1n WAITn ADVn TP207 TP208 TP209 TP210 TP211 TP212 TP213 TP214 ADD21 F5 ADD23 G4 WE_E E2 OE_R_W K4 CS3 H5 CS1 G2 CS0 J5 BE1 H4 GPIOA8 H7 ADV RXD1 AUDIO_SEL USB_CHG_ON JACK_IN EAR_SWITCH L7 GPIOA18 J11 GPIOA12 R1 GPIOB5 P1 GPIOA16 P5 GPIOA19 SD_CMD SD_CLK SD_DATA P7 GPIOB8 R4 GPIOB9 V1 GPIOB10 CS4n_NAND FLASH_LED_EN USB_IN FLIP SD_DETECT M5 GPIOA0 U1 GPIOA13 K7 GPIOA14 L8 GPIOA15 K11 GPIOA20 HA(24) CS2n_FLASH IMAGE_RST KEY_ROW(0:4) +VDD_IO_LOW R F2 GPIOB2 J4 GPIOA7 U4 GPIOA6 KEY_ROW(0) A16 KEY_ROW(1) A18 KROW0 KEY_ROW(2) KROW1 C17 KEY_ROW(3) KROW2 B17 KEY_ROW(4) KROW3 A17 KEY_COL(0) KROW4 D18 KEY_COL(1) KCOL0 C18 KEY_COL(2) KCOL1 D17 KCOL2 KEY_COL(3) E17 KEY_COL(4) KCOL3 B18 KCOL4 KEY_COL(0:4)

26 7-3. Charging Part

27 +VDD_IO_HIGH Typical 3.7V VBAT R513 R512 Typical 1.4V 5.0V V_EXT_CHARGE C505 C506 ZD501 +VBUS AUX_ON 1 CRDL 2 USB 3 _PPR U501 BAT 10 9 ICDL GND 8 R514 C504 MES_BATT END_OF_CHG CHG_ON 4 _CHG 5 _EN GND 11 USBON 7 6 IMIN USB_CHG_ON R517 R518 C507 BATTERY CHARGING

28 7-4. Sim Part

29 SIM_VCC SIM SIM_IO SIM_CLK SIM_RST G G G G C418 C419 C422

30 7-5. Microphone Part

31 MIC_BIAS MIC_IN_P U601 MIC600 C603 MIC_IN_P AUXM_P 1 VCC 2 NO1 10 NO2 COM2 9 AUXM_N MIC_SEL_N C607 C606 MIC_SEL_P 3 COM1 4 IN1 8 IN2 NC2 7 MIC_IN_N MIC_IN_N MIC_IN_P 5 NC1 GND 11 GND 6 C608 MIC_SEL ZD600 MIC_BIAS C601 R601 L601 C602 MIC_SEL_P MIC_P C604 R604 C605 MIC_SEL_N MIC_N L602 R605

32 7-6. Speaker Part(MP3/Spk)

33 Typical 3.7V VBAT AMP_EN L801 H L AMP ON AMP OFF C804 C805 U804 TP503 TP504 L810 L813 L809 L812 AMP_EN SPK_L C811 R810 C827 C812 R811 R803 J_SPK+ J_SPK- C813 1 EN_L 24 VIPL 22 VIML 23 VREFL 18 VOPL 16 VOML 3 VDD 7 VDD 9 VDD 15 VDD 19 VDD 21 VDD 13 EN_R 12 VIPR 10 VIMR 11 VREFR 6 VOPR 4 VOMR 2 VSS 5 VSS 8 VSS 14 VSS 17 VSS 20 VSS GND NC NC 27 C814 R804 R812 C828 C815 R813 AMP_EN SPK_R L803 L806 C816 L804 L807 TP505 TP506 R805 R806 C821 C822 STEREO SPEAKER Same Routing to SPK_L / SPK_R

34 7-7. Key Data Input

35 7-8. Receiver Part

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37 7-9. LCD Part

38

39 7-10. Camera part

40 7-11. Trans Flash Card part

41 7-12. TV OUT

42 3.3V +VDD_IO_HIGH TP303 R305 +VDD_IO_LOW C308 3 SAG V+ 6 HOT U IN 5 ENABLE GND 2 OUU 4 OSC300 GND1 2 GND2 4 HOT 1 3 C313 C314 C318 +VDD_CAM C310 C309 C311 +VDD_IMAGE +VDD_TV R313 R314 P5 L_DA0 P6 GPIO1_D0 P7 GPIO1_D1 P8 GPIO1_D4 P9 GPIO1_D7 P10 VDDG1 P11 GPIO2_D9 P12 TESTMODE P13 VDDAC P14 D_SDATAIN P2 L_DA2 P3 L_WR_N P4 LS_CS_N N3 L_DA5 N4 L_DA1 N5 L_RD_N N6 L_PCLK N7 GPIO1_D2 N8 GPIO1_D3 N9 GPIO1_D5 P1 L_DA3 M2 L_DA7 N1 L_DA6 N10 GPIO1_D6 N11 GPIO2_D8 N12 D_BCK N13 D_MSCK N14 D_SDATAOUT N2 L_DA4 L6 VDDI L7 D_SDA L8 S_SCK L9 D_LRCK M1 L_DA8 M13 S_SSN M14 S_MISO K9 TRST L1 L_DA11 L10 VDDSPI L11 S_MOSI L13 VSS L14 GPIO2_D10 L2 L_DA10 L4 L_DA9 L5 VSS K13 RTCK K14 TCK K2 L_DA17 K4 L_DA14 K5 L_DA13 K6 VDDC K7 D_SCK K8 TMS J13 T_OUT J14 TDO J2 L_ADS J4 L_DA16 J5 L_DA15 K1 L_DA12 K10 GPIO2_D11 K11 TDI H13 T_VRO H14 T_VREF H2 USB_DM H4 VDDUSB H5 VDDLCD J1 L_CS_N J10 AVSSTV J11 AVDDTV G13 M_SD3 G14 M_SD2 G2 GPIO2_D14 G4 VDDC G5 VSS H1 USB_DP H10 M_SD0 H11 M_SD1 F13 M_SD6 F14 M_SD4 F2 C_PWDN F4 C_D7 F5 VDDI G1 GPIO2_D15 G10 M_SD5 G11 M_SD7 E5 C_D4 E6 SD_D5_SD_3 E7 M_INTR E8 M_SD13 E9 M_SA1 F1 VSS F10 M_SD8 F11 M_SD9 D9 XRTS0 E1 C_D6 E10 M_SD12 E11 M_SD14 E13 M_SD10 E14 M_SD11 E2 C_D5 E4 C_D1 D13 M_SD15 D14 M_SA0 D2 C_D2 D4 C_PCLK D5 VDDS D6 SD_D2_SD_0 D7 M_ADS D8 VDDC B9 VSS C1 C_D0 C13 XOUT C14 XIN C2 C_MCLK D1 C_D3 D10 M_HOLD D11 MS_CS_N B14 VSSPLL B2 C_SDA B3 VSS B4 STROBE B5 SD_D3_SD_1 B6 VDDSD B7 SD_D0_SCLK B8 GPIO2_D12 A7 SD_D1_SCMD A8 GPIO2_D13 A9 VDDI B1 C_SCK B10 M_SA2 B11 SOUT0 M_RESET_N B12 B13 VDDPLL A12 SIN0 A13 M_WR_N A14 M_RD_N A2 C_HS A3 C_RST A4 VDDC A5 SD_D4_SD_2 A6 VSSQ U301 1 NC 2 NC A1 C_VS A10 M_CS_N A11 XCTS0 TP315 R311 C320 R310 +VDD_TV +VDD_IO_HIGH R307 +VDD_IO_LOW +VDD_IO_LOW C312 +VDD_IO_LOW +VDD_CAM R306 +VDD_IMAGE TP312 R309 WEN L_WRB TP305 LD(8) LD(7) LD(6) LD(5) LD(4) LD(3) LD(2) LD(15) LD(14) LD(13) LD(12) LD(11) LD(10) LD(1) LD(0) IMAGE_RST HD(7) HD(6) HD(5) HD(4) HD(3) HD(2) HD(15) HD(14) HD(13) HD(12) HD(11) HD(10) HD(1) HD(0) HD(0:15) LD(0:15) LD(9) I2S_SDATAIN I2S_MCKI I2S_SDATAOUT I2S_LRCK I2S_BCK RS Y(0) Y(1) Y(2) Y(3) Y(4) Y(5) Y(6) Y(7) Y(0:7) HD(9) HD(8) TDI_H TRST_H TMS_H LCD_MAIN_CS HA(20) HA(1) HA(2) M_HOLD CS3n_IMAGE OEN IMAGE_INT VSYNC M_SDA M_SCL CAM_RESET PCLK M_CLK HSYNC EARSPK_COM VDD_TV_EN C_PWDN T_OUT TV_OUT TDO_H TCK_H RTCK_H T_OUT

43 7-13. Bluetooth part

44 PCM_BCLK VDD_USB USB_DN USB_DP UART_RXD REQ_CTRL EEPROM_CLK COEX_3 VDD_IO GND GND GND PCM_SYNC GND TX_PU_TDD_N RESET_N VDD_RF TM3_LOW TM1 2_HIGH VDD_IO_LOW ANT C315 F300 2 OUT IN 4 GND GND 3 1 TP313 RESET_BT R308 C316 TP311 FSC L302 L301 BT_1V8 U302 BT_1V8 RTS2 DU CTS2 DD RXD2 TP314 TP316 TP307 TP308 TP317 C ANT GND UART_CTS_N PCM_OUT UART_RTS_N PCM_IN UART_TXD VDD_CORE GND GND GND GND TM0_HIGH BT_WAKE HOST_WAKE EEPROM_DATA GPIO_6 LPO_IN USB_DETACH GPIO_7 XTAL_PD COEX_ BT_EN BT_HOST_WAKE 32KHz_DIGIT +VDD_IO_LOW R315 TXD2 TP310 DCL

45 7-14. Main Key LED part

46