Very fast rate 2-input fuzzy processor for high energy physics

Transcription

1 Fuzzy Sets and Systems 132 (2002) Very fast rate 2-input fuzzy processor for high energy physics Davide Falchieri, Alessandro Gabrielli, Enzo Gandol Physics Department, Bologna University, Viale Berti Pichat 6=2, Bologna, Italy Received 27 October 2000; received in revised form 10 January 2002; accepted 20 March 2002 Abstract The paper explains the design and the realization of a small size high-speed fuzzy processor. The processor goal is to give more exibility to the front-end electronics for high-energy physics experiments. The chip can be applied as a general purpose data analyzer; particularly for analyzing and reducing on-line the data coming from detectors. The application of a fuzzy processor to this eld allows rejecting redundant data in a very short time. The design of the fuzzy processor has been done using VHDL language; it is cell-based and has been implemented with Alcatel 0:35 m CMOS VLSI technology. The chip architecture is pipelined with a clock frequency of 133 MHz; consequently the processing rate is 30 ns since only four active rules are processed. The chip size is 3 mm 2 and the total power consumption is 200 mw with 3, 3 Vof voltage supply. c 2002 Elsevier Science B.V. All rights reserved. Keywords: Fuzzy system; Fuzzy processor; Pattern recognition; Physics experiments; VLSI; Fuzzy rule generators 1. Introduction In high-energy physics experiments (HEPE) the detectors generate big amount of data at a quite high rate. For example at European Laboratory for Particle Physics (CERN) one of the main future experiments is the so-called Large Hadron Collider (LHC). In LHC a bunch crossing frequency of 40 MHz generates a burst every 25 ns. These data cannot be saved on-line since it would require a too huge and fast memory. On the other hand, most of these data are considered as background and, consequently, must be somehow rejected. This is why a fast and dedicated electronics is required. The main job of the device, here in after called trigger device, is to select on-line the possible Corresponding author. Tel.: ; fax: address: alessandro.gabrielli@bo.infn.it (A. Gabrielli). URL: gabrielli data from the background noise. It should be noted that the trigger device absolutely must not reject any signicant event and, in case of doubt, must save it. This task is generally divided into several stages and the electronics is named trigger device of I, II, III level and so on. At LHC the I level trigger job requires approximately 3 s to carry out a rst on-line selection of incoming data. For this reason the data are temporarily stored inside a FIFO while, at the same time, are analyzed with a pipelined architecture that, in case of data validation, after 3 s, transfers the stored data to the II level trigger device. This is shown in Fig. 1 where there is a First In First Out (FIFO) architecture that takes the function of a queue for the incoming data. While data are stored into the FIFO the I level trigger analyzes the data with a pipeline architecture that, for example, is composed by an application specic integrated circuits (ASICs) chip. At the end of the pipeline stages a control signal forces a multiplexer into transferring the previously stored data to /02/$ - see front matter c 2002 Elsevier Science B.V. All rights reserved. PII: S (02)

2 262 D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) Input Rate 40 Mhz 3 µ s FIFO Queue Data Rejection Detector ADC ASIC Fuzzy I Level Trigger Pipeline Stages Selected Data Out II L evel Trigger III Level Trigger Data To be Saved Fig. 1. Trigger sketch. Data Bus Control Signals Pipeline Stages the II level trigger or to the waste. Thus the II level trigger, that receives data at an average rate of some tens of KHz, has a longer time for making a second level selection. In the same way works the III level trigger that receives data at about 100 Hz rate. Of course the longer is the time available by the trigger level the more rened can be the data selection. For example the selection can take care of some trajectories that have to be identied, or some signal levels that have to overcome a given threshold Technological choice The I level trigger can be designed by means of ASICs depending on several tradeos. For example, the electronics for the I level trigger generally is very close to the detector and, consequently, its performances may be aected by radiation. Obviously the components should be as much radiation tolerant as possible but no component is granted to be radiation hard for every radiation ux and exposure time. Radiation can induce latch-up eects on CMOS gates, can induce single event upset (SEU) or even can permanently damage the silicon. Nevertheless, apart from the permanent damages, the programmable devices, such as memories or ip-ops, can work in a completely dierent way they were designed for. In fact, if a SEU occurs on the internal conguration memory, the programmable device can completely change its performance. Conversely, combinatorial logic, at most may be forced into changing some internal levels that hopefully should not aect seriously the global performance. For this reason ASICs are more radiation tolerant in case they have inside a few programmable devices in comparison to the case they have not. This is the reason why we have been induced into choosing ASICs. On the other hand fuzzy logic is a general robust approach that ts HEPE constraints. So we decided to combine fuzzy logic and ASICs by designing ourselves a fuzzy processor. Moreover we have been investigating architectural solutions for minimizing both power and time consumption. Anyway the choice among the available electronic devices is also based on the cost, since several thousands of components must often work in parallel on dierent sets of data. From this point of view ASICs, especially for many thousands of pieces, become much cheaper than other programmable devices such as eld programmable gate arrays (FPGAs). Thus, nally, we decided to have our chip realized using Alcatel Mietec 0:35 m CMOS VLSI digital technology, one of the most interesting among the deep sub-micron ones available through Europractice Fuzzy implementation In some particular application elds such as HEPE, where high computation performances are required, fuzzy processors can t the requirements. In addition they can be applied and implemented on electronic boards and systems [15,3,2,10,5]. In other words, for some dedicated application elds where traditional processors require a well-dened input output algorithm, fuzzy processors may be trained just with input training patterns. Nowadays, for this aim there are many methods for training a fuzzy system: by means of neural network based systems, by means of genetic algorithm based systems, by means of hybrid systems among the latter ones and so on. Nevertheless, the fuzzy system can solve a problem independently of knowledge of the input-output relationship. For this reason it has been investigated the

3 possibility to implement high-speed fuzzy processors for HEPE applications. From another point of view fuzzy logic, once implemented into dedicated hardware for particular applications, can solve much more quickly the same problems that traditional logic does slower. This leads to possible applications to HEPE trigger problems. In this application eld in fact, the electronic devices used for detecting, recognizing and saving physics events must be as fast as possible, and have to be designed with a high noise immunity, low power consumption and high performances in terms of reliability, robustness and exibility. These features have been met both by applying parallel-pipeline architecture and by implementing no-time consumption rule identication within the fuzzy processors. In other words, as will be explained in detail in Section 2.1, only some selected fuzzy rules, called active rules, are executed. The selection of these rules is one of the dedicated architectures that have been implemented for reducing the processing time. Thus, since we decided to face the trigger problem using a fuzzy-logic based system we have designed and realized a dedicated chip. We could not apply commercial components since most of the fuzzy logic based controllers available on the market [16,17,11] are not oriented to high processing rates as required in HEPE. In order to get such performance we have divided the design into several points: D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) the fuzzy chip needs a parallel-pipeline architecture working at the highest possible frequency (the technology adopted allows a frequency even higher than 100 MHz); the design must implement in HW a simple algorithm like the Sugeno order zero inference and defuzzication method [18,19]; the chip must process only the active rules without time consuming [4]; the processing rate must be independent of the implemented fuzzy system. This has been done using always a 64-fuzzy-rule-based system. Sixty-four are in fact all the possible combinations of the two input variables X0 and X1 with eight fuzzy sets each; just two adjacent membership functions (MFs) at a time can overlap each other; the rule antecedent allows determining the rule memory address (Fig. 2); Fig. 2. Schematic block representation. some dedicated circuits have been designed. The active interval selector connected to the membership function interval memory and to the address generator (Fig. 2) is able to identify and process only the active rules (see Section 2.1) related to each input data set, without time consuming; The active rule selections must be done without time consuming.

4 264 D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) Fuzzy processor architecture The main processor features are here summarized: two 7-bit input digital fuzzy variables; one 7-bit output digital fuzzy variable; 4 bits both for the antecedent and the premise degree of truth, from now on called respectively and value (see Section 2.2); eight fuzzy sets for each of the two input variables and bit crisp fuzzy sets (FSs) for the output variable; two adjacent MFs at a time can overlap; sixty-four 9-bit fuzzy rules; minimum and product disjunction and operator for the fuzzy rules; Sugeno order zero inference and defuzzication method; sixteen pipeline stages; Clock frequency (133 MHz) since this is the maximum clock speed allowed by the RAM memories in the Alcatel Mietec 0:35 m digital technology; 3-mm 2-layout area, 0:35 m CMOS digital technology. With these above features the chip has the following performance: each rule is processed in one clock period; the processing rate is given by the four active rules (see Section 2.1) and by the clock period: 4 7:5ns=30ns; the total processing time is the processing rate (30 ns) plus the input synchronization time (7:5 ns) plus the number of the pipeline stages times the clock period (16 7:5 ns = 120 ns). This makes 157:5 ns. The main chip architecture is shown in Fig. 2. The address generator selects the active rules related to the actual values of the input variables. Then the fuzzi- cation process starts. Here follows an explanation regarding the way the rules are stored and how the active ones are selected without time consuming, then each block will be described in more details The active fuzzy rule coding For example, let us deal with a fuzzy system with two input variables, three FSs for each input with two α X0 0 α X0 1 (a) (b) (c) Low Medium High X0 Low Medium High 2 data for interval identification 7 data for interval identification Fig. 3. (a) (c) Fuzzy sets. X1 X1 1 X1 2 as maximum allowed overlapping. A typical fuzzy rule for the above fuzzy system appears like: if (X0 is low) and (X1 is medium) then (Z isz j ): It is shown in Fig. 3(a) and (b) that only the four rules where X0 is related to low or medium FSs and X1 to medium or high FSs give a nonnull contribution for to the nal result. The output FS Z j is one among the 128 allowed (j [0; 127]). These rules are called active rules. Fig. 3(a) and (b) shows the values X0 0 and X0 1 as the degrees of truth related to the predicate X0 is low and X0 is medium. Moreover the gure shows the values X1 1 and X1 2 as the degrees of truth related to the predicate X1 is high and X1 is medium. Nevertheless, apart from the example, if we have N input variables, K FSs for each input variable, only t-norm operator for the rules and at most an overlap of 2, the active rules are 2 N while all the possible fuzzy rules are K N. Therefore, for the example shown in Fig. 3(a) and (b), we can process only four rules instead of 9 for a fuzzy system made of all the rules.

5 D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) Thus, this two input fuzzy processor carries out only the active rules, which are four, among all the possible ones, which are 64. This is done for making the time consuming as low as possible. Let us go into more details for describing the rulememory addressing method. In the case of Fig. 3(a) and (b) the number of all possible rules is 2 3 =8. In the fuzzy processor the fuzzy rules are stored into the rule memory starting from the 6-bit address which contains the code for: if (X0 is low) and (X1 is low) then (Z isz i ); then the memory location contains the code for the rule: if (X0 is Low) and (X1 is Medium) then (Z isz j ) and so on (i; j [0; 127]). The 9-bit rule code consists of two parts. The rst 2-bit one is the rule premise code and it is related to the premise, where 0 means that the related variable is not present in the rule while 1 means that there is. The second 7-bit part is the rule consequent code and it is related to the rule consequent and contains the whole crisp output FS value Z j. According to this addressing method, the rule memory address denes directly the FSs of the rule premise while the rule premise code conrms or not which input variables and output FS are involved. For example the premise code 10 means that the rule involves X0 but not X1. If we had 00 as a premise code it would mean that its contribution must be zero since it does not involve neither X0 nor X1. In addition, the rule consequent code is the crisp value of the output FS The active interval selector andthe MF interval buer This block has two ram memories, which contain the ending points of the eight MFs related to each input variable X0 and X1. For each input variable are sucient only six data because eight FSs dene seven intervals as shown in Fig. 3(c). Thus, for M input FSs overlapping two at a time, only M-1 datapairs can identify which interval, and, consequently, which FS, the input variable belongs to. In Fig. 3(a) and (b), where only three FSs are present, it would need just two data. These data are stored into the MF interval buer shown in Fig. 2. The active interval selector selects the two active MFs related to each input variable actual value. In Fig. 3(a) and (b) the active MFs are related to the shaded FSs that are the rst and second for X0 and the second and third for X1. As soon as these MFs are identied the address generator is able to compute the address code of the related active rules. Thus, if the input variable actual value is smaller than the rst ending point, the active MFs will be the rst and the second. In case the input variable actual value is between the rst and second ending points the active MFs will be the second and the third and so on The fuzzier The fuzzication process, in other words the computation of the antecedent degrees of truth s, from the hardware point of view, may be carried out in two main ways: with an arithmetic operation or reading a lookup-up-table. Since the arithmetic operation can be quite time and area consuming it has been decided to implement a fast look-up-table. A second advantage of this method is its high exibility in dening membership function shapes; in fact any arbitrary function compatible with the digital quantization is possible as shown in Fig. 3(c). Besides that, the restrictions on the overlapping of fuzzy sets leads to a very small memory block. In Fig. 2 the fuzzication process is implemented by means of the fuzzier circuit. It is composed of two ram memories each of which is a bit words. The 8 bits stand for the couple of 4-bit values related to each input variable value as shown in Fig. 3(a) and (b). Conversely, the 128 words stand for the 128 input values related to each input 7-bit variable The operator In this processor two dierent t-norm operations have been implemented: i (i [0; 3]) can be derived from the minimum value or the product one among the two 4-bit values related to the two input variables. In fact, both the minimum and product operation is selected o-line by means of an input pin selection. In this way the extraction of the i (i [0; 3]) value from the 2 s, leads to dierent results depending on

6 266 D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) the selected mode. For implementing this feature it has been designed a dedicated circuit named operator. It receives, as inputs, the 4 values as shown in Fig. 3(a) and (b) (X0 0 ;X0 1 ;X1 1 ;X1 2 ) and the rule premise code of the rule under process. The 4 s are grouped two at a time, rst X0 0 with X1 1, then X0 0 with X1 2, and so on till X0 1 with X1 2 to get four dierent combinations. These combinations correspond to the four active rules. At the same time, the rule address circuits, identies by means of the active interval selector, the related fuzzy rules stored into the rule memory. Thus, the operator is able to extract the right premise degree of truth taking into account if the two inputs are present in the rule or not. In fact, if a given rule has just one input variable in the premise, i (i [0; 3]) coincides with one of the s and a no-operation is done. For example if only X1 is present the rule premise code is 01 is stored into the rule memory The address generator This circuit, as shown in Fig. 2, generates the four right addresses once the involved intervals have been identied. This depends on the input variables values X0 and X1 as shown in Fig. 3(a) and (b). To identify an interval among the eight available, related to the eight input FSs, a 3-bit word is used as shown in Fig. 2 (X0 and X1 intervals). The address generator just concatenates this pair of interval 3-bit codes for creating a 6-bit address. Since each involved interval is adjacent to the successive one, starting with any interval code the following one is easily found out. For example, if the interval 3-bit code pair is , the four generated addresses that correspond to the four fuzzy rules within which these intervals are present, are generated as follows: Address 0 = ; Address 1 = ; Address 2 = ; Address 3 = : These are the four rule memory addresses shown in Fig The rule memory This ram memory is composed of 64 9-bit words. The 9 bits stand for the 7-bit word rule consequent code and for the 2-bit rule premise code. The rule consequent code is the output crisp FS value Z j (j [0; 127]). Conversely the 64 words stand for the 64 possible combinations of the two input variables and eight FSs each The defuzzier The defuzzier receives, clock period by clock period from the operator circuit, the i (i [0; 3]) value and from the rule memory the rule consequent code Z j (j [0; 127]) and computes the i i and i Z i; k i operations (k [0; 127]; i [0; 3] since only four additions are executed). These operations are carried out by means, respectively, of the pipeline numerator adder and pipeline denominator adder. Before executing the addition for the denominator a fast multiplication between i and Z i; k is done by means of the fast wallace pipeline multiplier [20] circuit. After processing the last rule the division process of formula 1 starts to compute the fuzzy output value (see Fig. 2). Fuzzy output = i Z i;k i = i 2.8. Implementedfeatures for I/O control i : (1) As already explained above, for HEPE applications the speed, in terms of computation time, is a very important constraint and is absolutely to be met [8]. Thus, for having a exible fuzzy chip, it has also be provided with input output handshake signals. Firstly the input data set, X0 and X1, has to be loaded into the chip according to input synchronization handshake signals. The input data set can be ready at any time depending on the external device that generates it but it has to be loaded just when the fuzzy processor is ready itself. Indeed, it has also to be synchronized with the fuzzy chip internal clock signal. For this reason the fuzzy processor has been provided with an input-ready and an output-ready handshake signals. The fuzzy processor, in fact, does not delegate the input output handshake synchronization signals to external devices such as controllers or dedicated processors, but a simple handshake signal conguration has been studied. An input-ready signal is used for enabling an external asynchronous device write cycle. In other words

7 D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) the external device can write its data into the fuzzy processor by means of an external driven load-enable signal, just when this input-ready signal is active. In addition, the external device must hold the input data set, X0 and X1, and a load-enable signal valid for at least two clock periods. In this way the fuzzy processor can both recognize the external device write cycle and synchronize the data X0 and X1, coming from external device, with the clock signal. Moreover an output-ready signal has been implemented to enable the external device for accepting the fuzzy output data of the fuzzy processor. Since the fuzzy processor may be clocked with a up to 133 MHz (period = 7:5 ns) frequency, and since the division process takes four pipeline stages, that is 30 ns, these output handshake signal is delayed four clock periods after the division process starts. Four clock periods are required by the fuzzier to extract the values. The X0 MF memory and X1 MF memory are read and the values are synchronized. Two of the four periods are parallel to the previously described pipeline stages. Consequently, at this point 9 pipeline stages have been used. The operator requires another period to compute the value: this is pipeline stage 10. The defuzzier requires one period to compute the i i and the multiplication Z i; k i operations and another period to carry out the addition i Z i; k i: these are pipeline stages 11 and 12 (k [0; 127]; i [0; 3]). the division process takes place when the last rule has been processed and takes four periods: these are pipeline stages from 13 to VLSI implementation 3. Pipeline subdivision It is here described and shown in Fig. 4, step-bystep, what each pipeline stage exactly does. At the rst pipeline stage a new input data set is loaded into an input register and the two X0 and X1 values are synchronized with the internal clock. In the second and third pipeline stages are generated the codes of the involved FSs by means of the active interval selector and MF interval buer. Four clock periods are required by the address generator to generate right four rule memory addresses. These stages start from the fourth and nish to the seventh. From the VLSI implementation point of view the fuzzy chip has been divided into dierent macroblocks independently of the pipeline and architecture subdivision. For example the rule memory is one of the most important because of its size. Figs. 5 and 6 show the clock and the power-ground supply wire distribution design. Conversely, Fig. 7 is a microphotograph of the actual silicon area. The inside-chip blocks have been designed in order to reach both high clock frequency and low power consumption. Of course a tradeo solution has been adopted but, anyway, the proposed goals have been met. In 1997 we designed and constructed a rst version of the two input fuzzy processor [9] with ES Pipeline Stage Rule Memory Address Fuzzy Output Fig. 4. Pipeline stages.

8 268 D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) Fuzzy Rule Ram Memory Clock Buffer Pad Rule Memory Membership Function Ram Memory X0 MF Memory X1 MF Memory Standard Cells Clock Net Fig. 5. Clock wire distribution. Core Power Supply 50 µm-wide wire Pad Power Supply Rings Rule Memory Core Power Supply Rings X0 M F Memory X1 MF Memory Core Ground 50 µm-wide wire Fig. 6. Ground and power supply distribution. 0:7 m digital CMOS technology and the clock frequency was 50MHz. The chip total area is 14mm 2 and the total power consumption is 1 W. Moving from 50 to 133 MHz has required some architectural changes in the previous architecture. In fact, it is not sucient to re-synthesize the previous VHDL code and map

9 D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) Fig. 7. Chip layout. it onto the new 0:35 m technology. First of all the pipeline stages have been optimized for a clock period of 7:5ns. For this some of the blocks have been subdivided into smaller and faster ones until they have been able to work at the target speed. For example the fast wallace pipeline multiplier that carries out the operation Z i; k i (7 4 bits) has been subdivided into two smaller pipeline blocks working at the frequency of 133 MHz. Thus the latency has increased of one period but every 7:5 ns a valid data Z i; k i is produced (k [0; 127]; i [0; 3]). In more detail, even if the total number of pipeline stages has been increased the nal latency has not. Moreover, over the frequency of 100 MHz is recommended avoiding gated clocks. Clock gating proves to be useful when some blocks of a circuit have to be enabled while others not. For example we made use of this technique in the previous version of the fuzzy chip for selecting only one of three memory blocks at a time (while the others two were in a stand-by state) in order to save power. While this technique is widely used for low-medium frequencies it is quite risky at high frequencies. In fact, using combinatorial control logic on the clock net, it may give rise to spikes whose eect may randomly aect the behavior of the entire logic. In this new version of the fuzzy chip the clock wire directly drives Fig. 8. Chip microphotograph. nearly 300 ip-ops and 3 ram memories without any control logic on it. One has only to provide a clock buer able to drive this net with an acceptable skew. In other words the clock signal has to reach every ip- op in the chip nearly at the same time. The skew of the clock net generated is 12 ps that is completely negligible at out target frequency. The - nal chip area is about 3 mm 2 versus the 14 mm 2 of the older one in 0:7 m ES2 technology. In Figs. 5 7 pictures of the chip layout are shown. The three memory blocks are easily visible on the left-hand side of the die area. The upper block is the rule memory, while the others are the look-up-tables containing information of the input MFs. For the global design 1700 standard cells have been put in a rectangular region on the right of the chip. A double ring for power and ground nets surrounds these cells (see particularly Figs. 6 and 7). The clock net has been automatically traced with a tree-shape structure in order to minimize the skew (see particularly Figs. 5 and 7). Fig. 8 shows the chip microphotograph. It is visible the layout design of Fig Applications As already been mentioned the electronic research for HEPE requires that several points have to be met at

10 270 D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) Fig. 9. (a),(b) Rotated area recognition. the same time. This is why many ASICs are designed and applied into the experiments [13,1]. Thus, for this application eld the fuzzy processor that is here presented has been designed. Particularly for application in HEPE for LHC experiments. Nevertheless, thanks to its fast processing rate, it can also been applied to more general pattern recognition problems [14,12]. The pattern recognition eld has been already investigated by us with a previous version of the fuzzy processor. The design of this previous version has been done using VHDL language, is cell-based and has been implemented with 0:7 m CMOS VLSI technology. It has been particularly investigated the problem of rotated area recognition [7]. The are recognition problem above presented leads to several LHC application elds within HEPE. In eect, area recognition applications may be split into several sub-applications very crucial in high energy physics. For example an area recognition, in the sense of shape recognition, is one of the main data analysis tasks that are usually carried out o-line. This is why data analysis is a time consuming process that has not been implemented on hardware devices in HEPE yet, apart from very simple applications such as under-threshold data rejection. Below are described in detail two dierent applications where the processor implementation has been investigated. Application 1: In Fig. 9(a) it is shown a given shape B that is included into an external background A. A and B can give rise to a typical area recognition problem in the sense that depending upon the input coordinates X and Y, the x y pair can belong to one of the two areas. If the task would be only this, the recognition could be easily done for example by digital comparators on the x y coordinates. When some given combinations of the input variables (x y coordinates) satisfy a given recognition rule, at the same time the task to recognize if the input pair belongs to A or B is also done. For example in Fig. 9(a) if X is 6.9 and Y is 11.2 the pair belongs to A. The same task becomes much more complicated if the same areas are rotated as shown in Fig. 9(b). The boundaries are xed but the same pair (6.9;11.2) belongs to B. In this way, while the areas rotate, also the thresholds used for dening the boundaries are to be modied. In other words the thresholds cannot be xed but must be quite exible: it is what fuzzy sets can do. We have investigated the problem of dening dierent input fuzzy sets for X and Y depending on the area boundaries. The simulations showed that for rotations both clockwise and anti-clockwise of angles lower than 10 a given area such that shown in Fig. 9 can be recognized. Application 2: Here is presented another area recognition problem applied to physics experiments. Also in this case the processor is intended as a time-consuming improver device. In eect, fuzzy logic can adapt easily for solving problems which require a hard computational work. In the example the task is to recognize and measure a given ellipsoidal area which is related to the charge of incident nuclei. When relativistic nuclei interact with some target nuclei, they produce heavy fragments whose charge diers from that of the incident nucleus. The primary motivation for these studies was to determine the nuclear parameters needed for calculations of the propagation of cosmic rays (CR) through interstellar matter. In the described application, the fragment charge is identied using the CR39 solid state nuclear track detectors [6]. This detector is composed of many target foils, displaced after the target on which accelerated charged particles collide. When an ion crosses the detector foil, it produces damages at the level of molecular bonds, forming a latent track. The latent track can be developed, during a successive chemical etching: due to the damaged molecular bonds, the etching velocity along the latent track is larger than that of the bulk material, and etch-pit cones are formed on both sides of the foil. Fig. 10 shows the base area and height of each cone. These quantities are functions of the energy loss

11 D. Falchieri et al. / Fuzzy Sets andsystems 132 (2002) Y y-axe Y y-axe x-axe x-axe X X Fig. 10. Rotated ellipsoidal area calculation. of the incident ion and, consequently, functions of the ion charge. The data analysis is made o-line after the collisions and etching, and is a time-consuming task. Some hundreds of foils can be collected for each incident nucleus type and each foil can contain thousands of cones. The cones are often damaged by the etching step and the boundaries are not very shape-dened. In addition, depending on the ion impacting direction, the cones can have a given ellipsoidal-base orientation. Each CR39 top view face is scanned with an optical microscope with a motorized stage, coupled with a charge coupled device (CCD). A PC computer records the coordinates and the base diameters of each track. A long scanning analysis must be performed to measure the ellipsoidal bases of the etch-pit cones in dierent CR39 faces. The averaged area of many face measurements, give the charge of the fragment particle. Starting from this point, the idea is to carry out the same task by means of a exible, robust and adaptable data acquisition system such as a fuzzy system. Besides that, taking into account that a fuzzy processor may take the function of a hardware accelerator, all the analysis stage can be much less time-consuming. It is expected an analysis-time improvement of a factor of about 10. To be highly condent on the results the diameters are measured twice on two dierent sets of perpendicular directions. Fig. 10 shows two possible orientations of the measurements that give rise to two couples of x y diameters. This way, the processor is able to extract a suciently approximated area of the ellipsoidal base. Thus the system deals with the experimental results related to the fragmentation charge-changing ion cross section. Indeed, fuzzy logic helps into extracting robust and condential area calculations even though the ellipsoidal axes values are slightly rotated in comparison with the expected ones. 6. Conclusion This design and realization of the fuzzy processor is an innovative possible solution for high energy applications. Particularly the proposal to apply fuzzy logic for data reduction in physics experiments is quite a original feature that we are going to further investigate and test. On the other hand we have tested the fuzzy chip with a clock frequency of 133 MHz. This upper limit is due to the ram mega cells available at the moment in Alcatel. So, the two input fuzzy chip realized with the 0:7 and 0:35 m technology have, respectively, an area of 14 and 3 mm 2. Moreover we have increased the throughput from 80 to 30 ns. This new chip is going to be assembled on a printed board and connected to a PC to develop and test a fuzzy system for a specic application. Then it will work o-line linked to external devices. We are also going to apply it to physics experiments where high computation speed is required for detecting, selecting and recognizing particle trajectories. Nevertheless, due to the implemented features for making it congurable in dierent ways it may be applied as a general-purpose fuzzy processor. In more details the fuzzy processor has an architecture congurable in dierent ways in

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