A High-Speed CMOS Image Sensor with Column-Parallel Single Capacitor CDSs and Single-slope ADCs
|
|
- Junior Casey
- 5 years ago
- Views:
Transcription
1 A High-Speed CMOS Image Sensor with Column-Parallel Single Capacitor CDSs and Single-slope ADCs LI Quanliang, SHI Cong, and WU Nanjian (The State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing , P.R. China) ABSTRACT This paper presents a high speed CMOS image sensor (CIS) with column-parallel single capacitor correlated double samplings (CDSs), programmable gain amplifiers (PGAs) and single-slope analog-to-digital converters (ADCs). The single capacitor CDS circuit has only one capacitor so that the area CDS circuit is small. In order to attain appropriate image contrast under different light conditions, the signal range can be adjusted by PGA. Single-slope ADC has smaller chip area than others ADCs and is suitable for column-parallel CIS architectures. A prototype sensor of pixels was realized in a 0.13μm 1P3M CIS process. Its pixel circuit is 4T active pixel sensor (APS) and pixel size is 10 10μm 2. Total chip area is 4 4mm 2. The prototype achieves the full frame rate in excess of 250 frames per second, the sensitivity of 10.7V/lx s, the conversion gain of 55.6μV/e and the column-to- column fixed-pattern noise (FPN) 0.41%. CMOS image sensor, Correlated double sampling, Programmable gain amplifier, Single-slope ADC, 4T, FPN 1 INTRODUCTION Due to benefit of lower power consumption, lower voltage operation, on-chip functionality and compatibility with standard CMOS technology, random access of image data, and lower cost [1],recent advances in CMOS image sensors have made them viable alternatives to charge-coupled devices (CCD), particularly in high-speed camera. A high-speed camera is a useful tool for the observation of high-speed phenomena, analysis of high-speed machinery and sports and so on. There are three general approaches to implementing ADC with active pixel sensors: chip level ADC, column level ADC, and pixel level ADC [2]. The chip level ADC uses only single ADC for an entire pixel array. Hence, extremely high-speed ADC should be required to achieve a high frame rate. The pixel-level ADC implements an ADC in every pixel, providing extremely high frame rate at the price of silicon area and power consumption. The column- parallel ADC which has an ADC in one or more columns of pixel array can achieve a good trade-off among frame-rate, the number of ADC, the data conversion rate of single ADC, noise performance, and power consumption. To achieve very high data conversion rate, many CISs employ column-parallel ADC architecture [4-6].There are many kinds of ADCs for column-parallel CISs. Successive approximation ADC (SAR) [4], cyclic ADC [5] and single slope ADC [6] have been utilized for column-parallel CISs. A single slope ADC is much simpler than other ADCs,which mainly consists of a International Symposium on Photoelectronic Detection and Imaging 2011: Advances in Imaging Detectors and Applications, edited by Makoto Ikeda, Nanjian Wu, Guangjun Zhang, Kecong Ai, Proc. of SPIE Vol. 8194, SPIE CCC code: X/11/$18 doi: / Proc. of SPIE Vol
2 single comparator and requires much less chip area and power consumption than a SAR or cyclic ADC. Moreover, this simple circuit also makes it relatively easy to ensure uniformity between columns and thus minimizes the column-to-column fixed-pattern noise. As a result, single-slope is very suitable for the column parallel architecture. In this paper, single-slope ADC acts as column parallel ADC. Correlated double sampling (CDS) circuit is also a key building block in a CMOS imager. The CDS circuit can reduce pixel reset noise, pixel fixed pattern noise (FPN), and flicker noise [3]. FPN is the primary noises of the CMOS imager, which is caused by random variations in the threshold voltage of the reset and source-follow transistors, variations in the photodetector geometry and variations in the dark current. In conventional designs, CDS circuit consists of two sets of sampling and hold (S/H) circuits and a differential amplifier [2]. The basic S/H circuit consists of a switch and a capacitor. This paper presents a high speed CMOS image sensor (CIS) with column-parallel single capacitor correlated double samplings (CDSs), programmable gain amplifiers (PGAs) and single-slope analog-to-digital converters (ADCs). The CDS circuit uses only one capacitor. Compared to conventional CDS circuit, single capacitor CDS requires less chip area. In order to attain appropriate image contrast under different light conditions, the signal range can be adjusted by PGA. Single-slope ADC has smaller chip area than others ADCs and is suitable for column-parallel CIS architectures. The rest of the paper is organized as follows. In section 2, the architecture of high speed CIS, the single capacitor CDS, the programmable gain amplifier and the single slope ADC are presented. In section 3, the experimental results will be presented. Finally, conclusions are drawn in section 4. 2 ARCHITECTURE OF HIGH SPEED CIS 2.1 Overall Block Diagram Figure1. The Overall Block Diagram of this CIS The overall block diagram of this high speed CIS is shown in Figure 1. In addition to the pixel array, the sensor consists of CDS array, PGA array, single-slope ADC array, data storage and output, and controlling modules. The Proc. of SPIE Vol
3 controlling module controls pixel array to operate and to output the image data row by row. First CDS array samples pixel signals after pixel reset operation and signal charge and outputs a difference signal between the reset and signal values. Then the signal is amplified by the PGA, and next the signal is quantified by single-slope ADC. The output data of ADC is stored in data storage unit and outputted by I/O interface T Pixel and CDS The pixel consists of a pinned photodiode (PPD), four transistors M1~M4 for pixel reset and readout. The CDS schematic consists of a capacitor C1, one reset transistor M6 and buffer M7. M5 and M8 are bias transistors. The schematic of 4T APS and single capacitor CDS, the timing diagram of the CDS circuit are shown in figure 2.CDS works as following: V CDS V pix RST CDS Vb Vb AbTX MT (a) (b) Figure2. The Schematic of 4T APS and the Single Capacitor CDS (a), and the Timing Diagram of the CDS Circuit (b) First, RST and SEL are high, RST CDS is low, and M2, M4, and M6 are on. The nodes A and B are charged to V RST +Vpix_offset and V CDS, respectively. As a result, the sampling capacitor C1 stores the charge of C1*(V CDS -V RST -Vpix_offset). Second, RST becomes low, TX and RST CDS become high, and M1 is on, while M2 and M6 are off. The node A is charged to Vsig+Vpix_offset and node B is floating, the voltage of node B is V B. So, C1 stores the charge of C1*(V B -Vsig-Vpix_offset). Considering the charge on the capacitor yields: C1 V CDS V RST V _ C1 V B V V _ (1) Then, V B V CDS V RST V (2) As shown in equation (2), the pixel offset voltage V pix_offset is eliminated. Where V RST is the pixel reset voltage, Vsig is the pixel signal voltage, and Vpix_offset is the pixel offset voltage including reset noise and fixed pattern noise. 2.3 PGA Proc. of SPIE Vol
4 The operation of PGA is divided into two models: (a) initialization and sampling and (b) amplifying, as illustrates in figure 3.In initialization and sampling model, switch S1, S3 are on, S2 is off, and the charge of C3 is discharged to zero, Vin is sampled on C2. Then PGA enters into amplifying model, switch S1, S3 become off, S2 turns on, the charge of C2 transfers into C3.Considering the charge on the node C yields: So C2 V C3 V (3) C C V (4) Where V in is the output of CDS, and V out is the output of PGA. The gain of PGA is determined by ratio of C2 and C3. C3 is a programmable capacitance, and its value can be changed by adjusting the control word. Thereby, the gain of PGA can be programmed by adjusting the value of C3. AOfTI (a) (b) Figure3. The Operation of PGA: (a) Initialization and Sampling and (b) Amplifying 2.4 Single Slope ADC ALJ1JJb jçrnjb ç ALWb COflUL ACOUJb COflUL (a) (b) Figure4. The architecture (a) and the timing diagram (b) of single slope ADC The single-slope ADC consists of ramp generator, comparator, counter and latch. Figure 4 shows the architecture of 8-bit single-slope ADC and the timing diagram to operate single-slope ADC. V in is compared with ramp voltage V ramp, which is generated by the ramp generator. V ramp value is determined by the counter. When Vin and Vramp crisscross, the Proc. of SPIE Vol
5 output of comparator becomes from high to low, and the output data of counter are latched. The latched data are the outputs of single-slope ADC. For column-parallel CIS, the ramp generator and counter of the single-slopee ADC can be shared by every column, and data-latch s area is small. So, most of the ADC s area is occupied by comparator and the single-slope requires smalll chip area. 3 EXPERIMENTAL RREULTS The chip is fabricated in 0.13μm CMOS process. The microphotograph of the chip is shown in Figure 5. Pixel array is , and pixel pitch is 10μm.There is 256 column-parallel readout paths (a unit with a CDS, a PGA, and a single-slope ADC) at the bottom of the pixel array. There is a controlling module at the left of chip, which controls pixel array, CDS, PGA, ADC, and data storage and outputt to operate according to the timing diagram of chip. Under FPGA controlling, image data transfer from CIS chip to computer. Figure 6 shows a sample image taken by the prototype chip at 250fps. The summary of this chip is shown in table 1. Figure5. Microphotograph of the fabricated CIS Figure6. A sample image taken by the prototype chip Table1. Information of CIS Process 0.13μm CIS process Power Supply 3.3 V (Analog)/1.5 V (Digital) Pixel Array Pixel Size μm 2 Pixel Type 4T FF 77% ADC Single-slope ADC ADC resolution 8 bit Sensitivity 10.7V/lx s Conversion Gain 55.6μV/ /e Col.-to-Col. FPN(dark) 0.41% Proc. of SPIE Vol
6 4 CONCLUSION A CMOS image sensor was fabricated and tested. It has 3.3 V analog power supply, and 1.5 V digital power supply. The column readout circuit consists of single capacitor CDS, PGA and single-slope ADC. Its pixel size is μm 2. Total chip area is 4 4 mm 2 which includes bond pads. The prototype chip achieves the full frame rate in excess of 250 frames per second, the sensitivity of 10.7V/lx s, the conversion gain of 55.6μV/e and the column-to-column FPN 0.41%. REFERENCES [1] Bigas, M., Cabruja, E., Forest, J. and Salvi, J., Review of CMOS image sensors, Microelectronics Journal,Papers 37, (2006). [2] Ohta, J.,[Smart CMOS Image Sensors and Applications], CRC Publishers, Boca Raton, London & New York, 46-47(2007). [3] Kawai, N. and Kawahito, S., Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensor, IEEE Trans. Electron Devices, Papers 51, (2004). [4] Matsuo, S.; Bales, T.J.; Shoda, M.; Osawa, S.; Kawamura, K.; Andersson, A.; Munirul Haque; Honda, H.; Almond, B.; Yaowu Mo; Gleason, J.; Chow, T.; Takayanagi, I., 8.9-Megapixel Video Image Sensor With 14-b Column-Parallel SA-ADC, IEEE Trans. Electron Devices, Papers56( 11), , (2009). [5]. Jong, H. P., Aoyama, S., Watanabe, T., Isobe, K.; Kawahito, S., A high-speed low-noise CMOS image sensor with 13-b column-parallel single-ended cyclic ADCs, IEEE Trans. Electron Devices, Papers56( 11), (2009). [6] Lee, D., Cho, K., Kim, D., and Han, G., Low-noise in-pixel comparing active pixel sensor using column-level single-slope ADC, IEEE Trans. Electron Devices, Papers 55(12), ,(2008). Proc. of SPIE Vol
PERFORMANCE ANALYSIS OF AN EFFICIENT TIME-TO-THRESHOLD PWM ARCHIECTURE USING CMOS TECHNOLOGY
PERFORMANCE ANALYSIS OF AN EFFICIENT TIME-TO-THRESHOLD PWM ARCHIECTURE USING CMOS TECHNOLOGY T. Jaya Bharathi and N. Mathan VLSI Design, Department of Electronics and Communication Engineering, Sathyabama
More information8K 240-HZ FULL-RESOLUTION HIGH-SPEED CAMERA AND SLOW-MOTION REPLAY SERVER SYSTEMS
8K 240-HZ FULL-RESOLUTION HIGH-SPEED CAMERA AND SLOW-MOTION REPLAY SERVER SYSTEMS R. Funatsu, T. Kajiyama, T. Yasue, K. Kikuchi, K. Tomioka, T. Nakamura, H. Okamoto, E. Miyashita and H. Shimamoto Japan
More informationOV µm Pixel Size Back Side Illuminated (BSI) 5 Megapixel CMOS Image Sensor
OmniVision OV5642 1.4 µm Pixel Size Back Side Illuminated (BSI) 5 Megapixel CMOS Image Sensor Circuit Analysis of the Pixel Array, Row Control, Column Readout, Analog Front End, and Pipelined A/D Converter
More informationReading an Image using CMOS Linear Image Sensor. S.R.Shinthu 1, P.Maheswari 2, C.S.Manikandababu 3. 1 Introduction. A.
International Journal of Inventions in Computer Science and Engineering, Volume 2 Issue 4 April 2015 Reading an Image using CMOS Linear Image Sensor S.R.Shinthu 1, P.Maheswari 2, C.S.Manikandababu 3 1,2
More informationPICOSECOND TIMING USING FAST ANALOG SAMPLING
PICOSECOND TIMING USING FAST ANALOG SAMPLING H. Frisch, J-F Genat, F. Tang, EFI Chicago, Tuesday 6 th Nov 2007 INTRODUCTION In the context of picosecond timing, analog detector pulse sampling in the 10
More informationA pixel chip for tracking in ALICE and particle identification in LHCb
A pixel chip for tracking in ALICE and particle identification in LHCb K.Wyllie 1), M.Burns 1), M.Campbell 1), E.Cantatore 1), V.Cencelli 2) R.Dinapoli 3), F.Formenti 1), T.Grassi 1), E.Heijne 1), P.Jarron
More informationOverview of All Pixel Circuits for Active Matrix Organic Light Emitting Diode (AMOLED)
Chapter 2 Overview of All Pixel Circuits for Active Matrix Organic Light Emitting Diode (AMOLED) ---------------------------------------------------------------------------------------------------------------
More informationAdding Analog and Mixed Signal Concerns to a Digital VLSI Course
Session Number 1532 Adding Analog and Mixed Signal Concerns to a Digital VLSI Course John A. Nestor and David A. Rich Department of Electrical and Computer Engineering Lafayette College Abstract This paper
More informationPARALLEL PROCESSOR ARRAY FOR HIGH SPEED PATH PLANNING
PARALLEL PROCESSOR ARRAY FOR HIGH SPEED PATH PLANNING S.E. Kemeny, T.J. Shaw, R.H. Nixon, E.R. Fossum Jet Propulsion LaboratoryKalifornia Institute of Technology 4800 Oak Grove Dr., Pasadena, CA 91 109
More informationMANY computer vision applications can benefit from the
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 52, NO. 1, JANUARY 2005 13 A General-Purpose Processor-per-Pixel Analog SIMD Vision Chip Piotr Dudek, Member, IEEE, and Peter J. Hicks,
More informationDual Slope ADC Design from Power, Speed and Area Perspectives
Dual Slope ADC Design from Power, Speed and Area Perspectives Isaac Macwan, Xingguo Xiong, Lawrence Hmurcik Department of Electrical & Computer Engineering, University of Bridgeport, Bridgeport, CT 06604
More informationA FOUR GAIN READOUT INTEGRATED CIRCUIT : FRIC 96_1
A FOUR GAIN READOUT INTEGRATED CIRCUIT : FRIC 96_1 J. M. Bussat 1, G. Bohner 1, O. Rossetto 2, D. Dzahini 2, J. Lecoq 1, J. Pouxe 2, J. Colas 1, (1) L. A. P. P. Annecy-le-vieux, France (2) I. S. N. Grenoble,
More information(12) United States Patent (10) Patent No.: US 6,727,486 B2. Choi (45) Date of Patent: Apr. 27, 2004
USOO6727486B2 (12) United States Patent (10) Patent No.: US 6,727,486 B2 Choi (45) Date of Patent: Apr. 27, 2004 (54) CMOS IMAGE SENSOR HAVING A 6,040,570 A 3/2000 Levine et al.... 250/208.1 CHOPPER-TYPE
More informationTechnology Scaling Issues of an I DDQ Built-In Current Sensor
Technology Scaling Issues of an I DDQ Built-In Current Sensor Bin Xue, D. M. H. Walker Dept. of Computer Science Texas A&M University College Station TX 77843-3112 Tel: (979) 862-4387 Email: {binxue, walker}@cs.tamu.edu
More informationdata and is used in digital networks and storage devices. CRC s are easy to implement in binary
Introduction Cyclic redundancy check (CRC) is an error detecting code designed to detect changes in transmitted data and is used in digital networks and storage devices. CRC s are easy to implement in
More informationCCD Element Linear Image Sensor CCD Element Line Scan Image Sensor
1024-Element Linear Image Sensor CCD 134 1024-Element Line Scan Image Sensor FEATURES 1024 x 1 photosite array 13µm x 13µm photosites on 13µm pitch Anti-blooming and integration control Enhanced spectral
More information1ms Column Parallel Vision System and It's Application of High Speed Target Tracking
Proceedings of the 2(X)0 IEEE International Conference on Robotics & Automation San Francisco, CA April 2000 1ms Column Parallel Vision System and It's Application of High Speed Target Tracking Y. Nakabo,
More informationEFFICIENT DESIGN OF SHIFT REGISTER FOR AREA AND POWER REDUCTION USING PULSED LATCH
EFFICIENT DESIGN OF SHIFT REGISTER FOR AREA AND POWER REDUCTION USING PULSED LATCH 1 Kalaivani.S, 2 Sathyabama.R 1 PG Scholar, 2 Professor/HOD Department of ECE, Government College of Technology Coimbatore,
More information25.5 A Zero-Crossing Based 8b, 200MS/s Pipelined ADC
25.5 A Zero-Crossing Based 8b, 200MS/s Pipelined ADC Lane Brooks and Hae-Seung Lee Massachusetts Institute of Technology 1 Outline Motivation Review of Op-amp & Comparator-Based Circuits Introduction of
More informationReport on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533
Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop Course project for ECE533 I. Objective: REPORT-I The objective of this project is to design a 4-bit counter and implement it into a chip
More informationCCD 143A 2048-Element High Speed Linear Image Sensor
A CCD 143A 2048-Element High Speed Linear Image Sensor FEATURES 2048 x 1 photosite array 13µm x 13µm photosites on 13µm pitch High speed = up to 20MHz data rates Enhanced spectral response Low dark signal
More informationMimosa32: Tower CIS October 2011 submission: 4 Metal, MiM Capacitor, Quadruple Well (deep-n and deep-p wells), HR epi
3.3 Discri-per-pix 80x25 array 16x80 µm JTAG structure SPAD Mimosa32: Tower CIS October 2011 submission: 4 Metal, MiM Capacitor, Quadruple Well (deep-n and deep-p wells), HR epi - Overall chip dimension:
More informationADVANCE INFORMATION TC PIXEL CCD IMAGE SENSOR. description
Very High-Resolution, 1/3-in Solid-State Image Sensor for NTSC Color Applications 340,000 Pixels per Field Frame Memory 658 (H) 496 (V) Active Elements in Image-Sensing Area Compatible With Electronic
More informationA MISSILE INSTRUMENTATION ENCODER
A MISSILE INSTRUMENTATION ENCODER Item Type text; Proceedings Authors CONN, RAYMOND; BREEDLOVE, PHILLIP Publisher International Foundation for Telemetering Journal International Telemetering Conference
More informationHigh Speed Reconfigurable FPGA Architecture for Multi-Technology Applications
High Speed Reconfigurable Architecture for Multi-Technology Applications 1 Arulpriya. K., 2 Vaisakhi.V.S., and 3 Jeba Paulin. M Assistant Professors, Department of ECE, Nehru Institute of Engineering and
More informationVHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress
VHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress Nor Zaidi Haron Ayer Keroh +606-5552086 zaidi@utem.edu.my Masrullizam Mat Ibrahim Ayer Keroh +606-5552081 masrullizam@utem.edu.my
More informationConverters: Analogue to Digital
Converters: Analogue to Digital Presented by: Dr. Walid Ghoneim References: Process Control Instrumentation Technology, Curtis Johnson Op Amps Design, Operation and Troubleshooting. David Terrell 1 - ADC
More informationHigh Performance TFT LCD Driver ICs for Large-Size Displays
Name: Eugenie Ip Title: Technical Marketing Engineer Company: Solomon Systech Limited www.solomon-systech.com The TFT LCD market has rapidly evolved in the last decade, enabling the occurrence of large
More informationV6118 EM MICROELECTRONIC - MARIN SA. 2, 4 and 8 Mutiplex LCD Driver
EM MICROELECTRONIC - MARIN SA 2, 4 and 8 Mutiplex LCD Driver Description The is a universal low multiplex LCD driver. The version 2 drives two ways multiplex (two blackplanes) LCD, the version 4, four
More informationLow Power D Flip Flop Using Static Pass Transistor Logic
Low Power D Flip Flop Using Static Pass Transistor Logic 1 T.SURIYA PRABA, 2 R.MURUGASAMI PG SCHOLAR, NANDHA ENGINEERING COLLEGE, ERODE, INDIA Abstract: Minimizing power consumption is vitally important
More informationA 3-Pin 1.5 V 550 µw 176 x 144 Self-Clocked CMOS Active Pixel Image Sensor
A 3Pin 1.5 V 55 µw 176 x 144 SelfClocked CMOS Active Pixel Image Sensor KwangBo Cho Photobit Corporation 135 N. Los Robles Avenue Pasadena, CA 9111, USA 162668322 cho@photobit.com Alexander Krymski Photobit
More informationLOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES. Masum Hossain University of Alberta
LOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES Masum Hossain University of Alberta 0 Outline Why ADC-Based receiver? Challenges in ADC-based receiver ADC-DSP based Receiver Reducing impact of Quantization
More informationAM-OLED pixel circuits suitable for TFT array testing. Research Division Almaden - Austin - Beijing - Haifa - India - T. J. Watson - Tokyo - Zurich
RT0565 Engineering Technology 4 pages Research Report February 3, 2004 AM-OLED pixel circuits suitable for TFT array testing Y. Sakaguchi, D. Nakano IBM Research, Tokyo Research Laboratory IBM Japan, Ltd.
More informationLarge Area, High Speed Photo-detectors Readout
Large Area, High Speed Photo-detectors Readout Jean-Francois Genat + On behalf and with the help of Herve Grabas +, Samuel Meehan +, Eric Oberla +, Fukun Tang +, Gary Varner ++, and Henry Frisch + + University
More informationLow-Voltage 96 db Snapshot CMOS Image Sensor with 4.5 nw Power Dissipation per Pixel
Sensors 2012, 12, 10067-10085; doi:10.3390/s120810067 Article OPEN ACCESS sensors ISSN 1424-8220 www.mdpi.com/journal/sensors Low-Voltage 96 db Snapshot CMOS Image Sensor with 4.5 nw Power Dissipation
More informationChapter 3 Evaluated Results of Conventional Pixel Circuit, Other Compensation Circuits and Proposed Pixel Circuits for Active Matrix Organic Light Emitting Diodes (AMOLEDs) -------------------------------------------------------------------------------------------------------
More informationReconfigurable Neural Net Chip with 32K Connections
Reconfigurable Neural Net Chip with 32K Connections H.P. Graf, R. Janow, D. Henderson, and R. Lee AT&T Bell Laboratories, Room 4G320, Holmdel, NJ 07733 Abstract We describe a CMOS neural net chip with
More informationIC Design of a New Decision Device for Analog Viterbi Decoder
IC Design of a New Decision Device for Analog Viterbi Decoder Wen-Ta Lee, Ming-Jlun Liu, Yuh-Shyan Hwang and Jiann-Jong Chen Institute of Computer and Communication, National Taipei University of Technology
More informationT sors, such that when the bias of a flip-flop circuit is
EEE TRANSACTONS ON NSTRUMENTATON AND MEASUREMENT, VOL. 39, NO. 4, AUGUST 1990 653 Array of Sensors with A/D Conversion Based on Flip-Flops WEJAN LAN AND SETSE E. WOUTERS Abstruct-A silicon array of light
More informationR Fig. 5 photograph of the image reorganization circuitry. Circuit diagram of output sampling stage.
IMPROVED SCAN OF FIGURES 01/2009 into the 12-stage SP 3 register and the nine pixel neighborhood is transferred in parallel to a conventional parallel-to-serial 9-stage CCD register for serial output.
More information3D-CHIP TECHNOLOGY AND APPLICATIONS OF MINIATURIZATION
3D-CHIP TECHNOLOGY AND APPLICATIONS OF MINIATURIZATION 23.08.2018 I DAVID ARUTINOV CONTENT INTRODUCTION TRENDS AND ISSUES OF MODERN IC s 3D INTEGRATION TECHNOLOGY CURRENT STATE OF 3D INTEGRATION SUMMARY
More informationAn FPGA Implementation of Shift Register Using Pulsed Latches
An FPGA Implementation of Shift Register Using Pulsed Latches Shiny Panimalar.S, T.Nisha Priscilla, Associate Professor, Department of ECE, MAMCET, Tiruchirappalli, India PG Scholar, Department of ECE,
More informationMonolithic Thin Pixel Upgrade Testing Update. Gary S. Varner, Marlon Barbero and Fang Fang UH Belle Meeting, April 16 th 2004
Monolithic Thin Pixel Upgrade Testing Update Gary S. Varner, Marlon Barbero and Fang Fang UH Belle Meeting, April 16 th 2004 Basic Technology: Standard CMOS CMOS Camera Because of large Capacitance, need
More informationA Real Time Infrared Imaging System Based on DSP & FPGA
A Real Time Infrared Imaging ystem Based on DP & FPGA Babak Zamanlooy, Vahid Hamiati Vaghef, attar Mirzakuchaki, Ali hojaee Bakhtiari, and Reza Ebrahimi Atani Department of Electrical Engineering Iran
More informationADOSE DELIVERABLE D6.9; PUBLIC SUMMARY SRS Testing of components and subsystems
RELIABLE APPLICATION SPECIFIC DETECTION OF ROAD USERS WITH VEHICLE ON-BOARD SENSORS ADOSE DELIVERABLE D6.9; PUBLIC SUMMARY SRS Testing of components and subsystems Issued by: AIT Austrian Institute of
More informationA low jitter clock and data recovery with a single edge sensing Bang-Bang PD
LETTER IEICE Electronics Express, Vol.11, No.7, 1 6 A low jitter clock and data recovery with a single edge sensing Bang-Bang PD Taek-Joon Ahn, Sang-Soon Im, Yong-Sung Ahn, and Jin-Ku Kang a) Department
More informationEfficient 500 MHz Digital Phase Locked Loop Implementation sin 180nm CMOS Technology
Efficient 500 MHz Digital Phase Locked Loop Implementation sin 180nm CMOS Technology Akash Singh Rawat 1, Kirti Gupta 2 Electronics and Communication Department, Bharati Vidyapeeth s College of Engineering,
More informationA 5-Gb/s Half-rate Clock Recovery Circuit in 0.25-μm CMOS Technology
A 5-Gb/s Half-rate Clock Recovery Circuit in 0.25-μm CMOS Technology Pyung-Su Han Dept. of Electrical and Electronic Engineering Yonsei University Seoul, Korea ps@tera.yonsei.ac.kr Woo-Young Choi Dept.
More informationThe design of a 16*16 pixels CMOS image sensor with 0.5 e - RMS noise
The design of a 16*16 pixels CMOS image sensor with 0.5 e - RMS noise (4186176) June 2013 Faculty of Electrical Engineering, Mathematics and Computer Science Delft University of Technology The project
More information(12) United States Patent (10) Patent No.: US 8,026,969 B2
USOO8026969B2 (12) United States Patent (10) Patent No.: US 8,026,969 B2 Mauritzson et al. (45) Date of Patent: *Sep. 27, 2011 (54) PIXEL FOR BOOSTING PIXEL RESET VOLTAGE (56) References Cited U.S. PATENT
More informationReadout techniques for drift and low frequency noise rejection in infrared arrays
Readout techniques for drift and low frequency noise rejection in infrared arrays European Southern Observatory Finger, G., Dorn, R.J, Hoffman, A.W., Mehrgan, H., Meyer, M., Moorwood, A.F.M., Stegmeier,
More informationAbstract 1. INTRODUCTION. Cheekati Sirisha, IJECS Volume 05 Issue 10 Oct., 2016 Page No Page 18532
www.ijecs.in International Journal Of Engineering And Computer Science ISSN: 2319-7242 Volume 5 Issue 10 Oct. 2016, Page No. 18532-18540 Pulsed Latches Methodology to Attain Reduced Power and Area Based
More informationDigital Correction for Multibit D/A Converters
Digital Correction for Multibit D/A Converters José L. Ceballos 1, Jesper Steensgaard 2 and Gabor C. Temes 1 1 Dept. of Electrical Engineering and Computer Science, Oregon State University, Corvallis,
More informationINTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY
INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY A PATH FOR HORIZING YOUR INNOVATIVE WORK LOW POWER SAR USING CMOS TECHNOLOGY; VLSI IMPLEMENTATION MS. KRISHNA PRAKASHCHAND
More informationFuture of Analog Design and Upcoming Challenges in Nanometer CMOS
Future of Analog Design and Upcoming Challenges in Nanometer CMOS Greg Taylor VLSI Design 2010 Outline Introduction Logic processing trends Analog design trends Analog design challenge Approaches Conclusion
More informationReducing tilt errors in moiré linear encoders using phase-modulated grating
REVIEW OF SCIENTIFIC INSTRUMENTS VOLUME 71, NUMBER 6 JUNE 2000 Reducing tilt errors in moiré linear encoders using phase-modulated grating Ju-Ho Song Multimedia Division, LG Electronics, #379, Kasoo-dong,
More informationSemiconductors Displays Semiconductor Manufacturing and Inspection Equipment Scientific Instruments
Semiconductors Displays Semiconductor Manufacturing and Inspection Equipment Scientific Instruments Electronics 110-nm CMOS ASIC HDL4P Series with High-speed I/O Interfaces Hitachi has released the high-performance
More informationAnalog, Mixed-Signal, and Radio-Frequency (RF) Electronic Design Laboratory. Electrical and Computer Engineering Department UNC Charlotte
Analog, Mixed-Signal, and Radio-Frequency (RF) Electronic Design Laboratory Electrical and Computer Engineering Department UNC Charlotte Teaching and Research Faculty (Please see faculty web pages for
More informationWINTER 15 EXAMINATION Model Answer
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationISC0904: 1k x 1k 18µm N-on-P ROIC. Specification January 13, 2012
ISC0904 1k x 1k 18µm N-on-P ROIC Specification January 13, 2012 This presentation contains content that is proprietary to FLIR Systems. Information is subject to change without notice. 1 Version 1.00 January
More informationDesign Low-Power and Area-Efficient Shift Register using SSASPL Pulsed Latch
Design Low-Power and Area-Efficient Shift Register using SSASPL Pulsed Latch 1 D. Sandhya Rani, 2 Maddana, 1 PG Scholar, Dept of VLSI System Design, Geetanjali college of engineering & technology, 2 Hod
More informationEL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043
EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP Due 16.05. İLKER KALYONCU, 10043 1. INTRODUCTION: In this project we are going to design a CMOS positive edge triggered master-slave
More informationUncooled amorphous silicon ¼ VGA IRFPA with 25 µm pixel-pitch for High End applications
Uncooled amorphous silicon ¼ VGA IRFPA with 25 µm pixel-pitch for High End applications A. Crastes, J.L. Tissot, M. Vilain, O. Legras, S. Tinnes, C. Minassian, P. Robert, B. Fieque ULIS - BP27-38113 Veurey
More informationBias, Auto-Bias And getting the most from Your Trifid Camera.
Bias, Auto-Bias And getting the most from Your Trifid Camera. The imaging chip of the Trifid Camera is read out, one well at a time, by a 16-bit Analog to Digital Converter (ADC). Because it has 16-bits
More informationFully Static and Compressed Topology Using Power Saving in Digital circuits for Reduced Transistor Flip flop
Fully Static and Compressed Topology Using Power Saving in Digital circuits for Reduced Transistor Flip flop 1 S.Mounika & 2 P.Dhaneef Kumar 1 M.Tech, VLSIES, GVIC college, Madanapalli, mounikarani3333@gmail.com
More informationVLSI Design: 3) Explain the various MOSFET Capacitances & their significance. 4) Draw a CMOS Inverter. Explain its transfer characteristics
1) Explain why & how a MOSFET works VLSI Design: 2) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel
More informationLow-Power and Area-Efficient Shift Register Using Pulsed Latches
Low-Power and Area-Efficient Shift Register Using Pulsed Latches G.Sunitha M.Tech, TKR CET. P.Venkatlavanya, M.Tech Associate Professor, TKR CET. Abstract: This paper proposes a low-power and area-efficient
More informationCCD220 Back Illuminated L3Vision Sensor Electron Multiplying Adaptive Optics CCD
CCD220 Back Illuminated L3Vision Sensor Electron Multiplying Adaptive Optics CCD FEATURES 240 x 240 pixel image area 24 µm square pixels Split frame transfer 100% fill factor Back-illuminated for high
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) WINTER 2018 EXAMINATION MODEL ANSWER
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in themodel answer scheme. 2) The model answer and the answer written by candidate may
More informationRedEye Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision
Analog ConvNet Image Sensor Architecture for Continuous Mobile Vision Robert LiKamWa Yunhui Hou Yuan Gao Mia Polansky Lin Zhong roblkw@rice.edu houyh@rice.edu yg18@rice.edu mia.polansky@rice.edu lzhong@rice.edu
More informationA Symmetric Differential Clock Generator for Bit-Serial Hardware
A Symmetric Differential Clock Generator for Bit-Serial Hardware Mitchell J. Myjak and José G. Delgado-Frias School of Electrical Engineering and Computer Science Washington State University Pullman, WA,
More informationEECS150 - Digital Design Lecture 2 - CMOS
EECS150 - Digital Design Lecture 2 - CMOS January 23, 2003 John Wawrzynek Spring 2003 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor
More informationA VLSI Implementation of an Analog Neural Network suited for Genetic Algorithms
A VLSI Implementation of an Analog Neural Network suited for Genetic Algorithms Johannes Schemmel 1, Karlheinz Meier 1, and Felix Schürmann 1 Universität Heidelberg, Kirchhoff Institut für Physik, Schröderstr.
More informationThe hybrid photon detectors for the LHCb-RICH counters
7 th International Conference on Advanced Technology and Particle Physics The hybrid photon detectors for the LHCb-RICH counters Maria Girone, CERN and Imperial College on behalf of the LHCb-RICH group
More informationRX40_V1_0 Measurement Report F.Faccio
RX40_V1_0 Measurement Report F.Faccio This document follows the previous report An 80Mbit/s Optical Receiver for the CMS digital optical link, dating back to January 2000 and concerning the first prototype
More informationDesign of a Low Power and Area Efficient Flip Flop With Embedded Logic Module
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 6, Ver. II (Nov - Dec.2015), PP 40-50 www.iosrjournals.org Design of a Low Power
More informationPAPER A 4K 2 K-Pixel Color Image Pickup System
IEICE TRANS. INF. & SYST., VOL.E82 D, NO.8 AUGUST 1999 1219 PAPER A 4K 2 K-Pixel Color Image Pickup System Kohji MITANI, Hiroshi SHIMAMOTO, Nonmembers, and Yoshihiro FUJITA, Member SUMMARY We have developed
More informationNoise Margin in Low Power SRAM Cells
Noise Margin in Low Power SRAM Cells S. Cserveny, J. -M. Masgonty, C. Piguet CSEM SA, Neuchâtel, CH stefan.cserveny@csem.ch Abstract. Noise margin at read, at write and in stand-by is analyzed for the
More informationROM MEMORY AND DECODERS
ROM MEMORY AND DECODERS INEL427 - Spring 22 RANDOM ACCESS MEMORY Random Access Memory (RAM) read and write memory volatile Static RAM (SRAM) store information as long as power is applied will not lose
More information(12) Patent Application Publication (10) Pub. No.: US 2003/ A1
(19) United States US 2003O146369A1 (12) Patent Application Publication (10) Pub. No.: US 2003/0146369 A1 Kokubun (43) Pub. Date: Aug. 7, 2003 (54) CORRELATED DOUBLE SAMPLING CIRCUIT AND CMOS IMAGE SENSOR
More informationAND9191/D. KAI-2093 Image Sensor and the SMPTE Standard APPLICATION NOTE.
KAI-09 Image Sensor and the SMPTE Standard APPLICATION NOTE Introduction The KAI 09 image sensor is designed to provide HDTV resolution video at 0 fps in a progressive scan mode. In this mode, the sensor
More informationComparative Analysis of Organic Thin Film Transistor Structures for Flexible E-Paper and AMOLED Displays
Comparative Analysis of Organic Thin Film Transistor Structures for Flexible E-Paper and AMOLED Displays Linrun Feng, Xiaoli Xu and Xiaojun Guo ECS Trans. 2011, Volume 37, Issue 1, Pages 105-112. doi:
More informationResults on 0.7% X0 thick Pixel Modules for the ATLAS Detector.
Results on 0.7% X0 thick Pixel Modules for the ATLAS Detector. INFN Genova: R.Beccherle, G.Darbo, G.Gagliardi, C.Gemme, P.Netchaeva, P.Oppizzi, L.Rossi, E.Ruscino, F.Vernocchi Lawrence Berkeley National
More information... A COMPUTER SYSTEM FOR MULTIPARAMETER PULSE HEIGHT ANALYSIS AND CONTROL*
I... A COMPUTER SYSTEM FOR MULTIPARAMETER PULSE HEIGHT ANALYSIS AND CONTROL* R. G. Friday and K. D. Mauro Stanford Linear Accelerator Center Stanford University, Stanford, California 94305 SLAC-PUB-995
More informationINTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET)
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) Proceedings of the 2 nd International Conference on Current Trends in Engineering and Management ICCTEM -2014 ISSN
More informationStatus of readout electronic design in MOST1
Status of readout electronic design in MOST1 Na WANG, Ke WANG, Zhenan LIU, Jia TAO On behalf of the Trigger Group (IHEP) Mini-workshop for CEPC MOST silicon project,23 November,2017,Beijing Outline Introduction
More information12) United States Patent 10) Patent No.: US B2
USOO87240O2B2 12) United States Patent 10) Patent No.: US 8.724.002 B2 9 9 Rajasekaran (45) Date of Patent: May 13, 2014 (54) IMAGING PIXELS WITH DUMMY 6,535,247 B1 3/2003 Kozlowski et al. TRANSISTORS
More informationTopics. Microelectronics Revolution. Digital Circuits Part 1 Logic Gates. Introductory Medical Device Prototyping
Introductory Medical Device Prototyping Digital Circuits Part 1 Logic Gates, http://saliterman.umn.edu/ Department of Biomedical Engineering, University of Minnesota Topics Digital Electronics CMOS Logic
More informationChapter 7 Memory and Programmable Logic
EEA091 - Digital Logic 數位邏輯 Chapter 7 Memory and Programmable Logic 吳俊興國立高雄大學資訊工程學系 2006 Chapter 7 Memory and Programmable Logic 7-1 Introduction 7-2 Random-Access Memory 7-3 Memory Decoding 7-4 Error
More informationHello and welcome to this training module for the STM32L4 Liquid Crystal Display (LCD) controller. This controller can be used in a wide range of
Hello and welcome to this training module for the STM32L4 Liquid Crystal Display (LCD) controller. This controller can be used in a wide range of applications such as home appliances, medical, automotive,
More informationDEPFET Active Pixel Sensors for the ILC
DEPFET Active Pixel Sensors for the ILC Laci Andricek for the DEPFET Collaboration (www.depfet.org) The DEPFET ILC VTX Project steering chips Switcher thinning technology Simulation sensor development
More informationDigital Circuits. Innovation Fellows Program
Innovation Fellows Program Digital Circuits, http://saliterman.umn.edu/ Department of Biomedical Engineering, University of Minnesota Topics Digital Electronics TTL and CMOS Logic National Instrument s
More informationPhotodiode Detector with Signal Amplification
107 Bonaventura Dr., San Jose, CA 95134 Tel: +1 408 432 9888 Fax: +1 408 432 9889 www.x-scanimaging.com Linear X-Ray Photodiode Detector Array with Signal Amplification XB8801R Series An X-Scan Imaging
More informationECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011
ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 9: TX Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Next
More informationMarch Test Compression Technique on Low Power Programmable Pseudo Random Test Pattern Generator
International Journal of Computational Intelligence Research ISSN 0973-1873 Volume 13, Number 6 (2017), pp. 1493-1498 Research India Publications http://www.ripublication.com March Test Compression Technique
More informationDIFFERENTIAL CONDITIONAL CAPTURING FLIP-FLOP TECHNIQUE USED FOR LOW POWER CONSUMPTION IN CLOCKING SCHEME
DIFFERENTIAL CONDITIONAL CAPTURING FLIP-FLOP TECHNIQUE USED FOR LOW POWER CONSUMPTION IN CLOCKING SCHEME Mr.N.Vetriselvan, Assistant Professor, Dhirajlal Gandhi College of Technology Mr.P.N.Palanisamy,
More informationThe ATLAS Pixel Chip FEI in 0.25µm Technology
The ATLAS Pixel Chip FEI in 0.25µm Technology Peter Fischer, Universität Bonn (for Ivan Peric) for the ATLAS pixel collaboration The ATLAS Pixel Chip FEI Short Introduction to ATLAS Pixel mechanics, modules
More informationProduction and Development status of MPPC
Production and Development status of MPPC Kazuhisa Yamamura 1 Solid State Division, Hamamatsu Photonics K.K. Hamamatsu-City, 435-8558 Japan iliation E-mail: yamamura@ssd.hpk.co.jp Kenichi Sato, Shogo Kamakura
More informationMass production testing of the front-end ASICs for the ALICE SDD system
Mass production testing of the front-end ASICs for the ALICE SDD system L. Toscano a, R.Arteche Diaz b,e, S.Di Liberto b, M.I.Martínez a,d, S.Martoiu a, M.Masera c, G.Mazza a, M.A.Mazzoni b, F.Meddi b,
More informationThe Alice Silicon Pixel Detector (SPD) Peter Chochula for the Alice Pixel Collaboration
The Alice Silicon Pixel Detector (SPD) Peter Chochula for the Alice Pixel Collaboration The Alice Pixel Detector R 1 =3.9 cm R 2 =7.6 cm Main Physics Goal Heavy Flavour Physics D 0 K π+ 15 days Pb-Pb data
More information