Stanford Linear Accelerator Center Accelerator Controls Electronics & Instrumentation Engineering PRELIMINARY SLAC IP-QINT-ADC

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1 SLAC IP-QINT-ADC 8-Channel Industry Pack Charge-Integrating ADC Programming Guide Version 4.0 For Use With Board Part Number: R1 For BLM Assembly: D Gateware Rev 0x4002 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 1 of 100 J. Dusatko /

2 0. MEMORY MAPS: IP-QINT-ADC I/O Space Memory Map: 16-bits 0x007E 0x0054 0x0052 0x0050 Acq Cnt High Reg Acq Cnt Low Reg 0x004E 0x004C 0x004A 0x0048 0x0046 0x0044 0x0042 0x0040 0x003E EGate ADC Delay Reg EGate Width Reg High EGate Width Reg Low EGate Delay Reg Latched Summary Faults Reg_1 Latched Summary Faults Reg_0 Summary Faults Reg_1 Summary Faults Reg_0 Latched Chan 7 Fault Status 0x0030 0x002E Latched Chan 0 Fault Status Chan 7 Fault Status 0x0020 0x001E 0x001C 0x001A 0x0018 0x0016 0x0014 0x0012 0x0010 0x000E 0x000C 0x000A 0x0008 0x0006 0x0004 0x0002 Chan 0 Fault Status Gate PED ADC Delay Reg Test-to-Base Delay Reg Beam-to-Test Delay Reg Gate ADC Delay Reg GPIO Ctrl Reg Sync Out Width Reg Sync Out Delay Reg Gate Width Reg Gate Delay Reg Test Pulse Width Reg Test Pulse Delay Reg Trigger Error Cnt Trigger Delay Reg CSR2 / Control & Status Register 3 CSR2 / Control & Status Register 2 Base + 0x0000 CSR1 / Control & Status Register 1 Note that the IP I/O space only uses address lines A6:A1. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 4 of 100 J. Dusatko /

3 IP-QINT-ADC MEM Space Memory Map: 16-bits 0xFFFFFF 0x0059BE 0x Beam / Test / Baseline Accumulator Raw Data <reserved> 0x00583E 0x x x x00578E 0x x x BLM Baseline Data Beam/Test Chans 0..7 <reserved> Raw ADC Data Chan <reserved> ADC Diagnostic Memory <reserved> Channel 7 Dose Data / Fault Thresh 0x x x004FFF 0x Channel 0 Dose Data / Fault Thresh <reserved> 0x00437E Beam / Test / Baseline Shift Register Raw Data Base + 0x Note that the IP MEM space uses address lines A22:A1 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 5 of 100 J. Dusatko /

4 3.0 IP-QINT-ADC Module I/O Space Register Descriptions: 3.1 Module Control & Status Register 1 Name: CSR1 Offset: 0x0000 Mode: R/W This is the control and status register for the IP-QINT-ADC module. In contains bits that control the basic board functions and provides status as well. SRST Bit(s): [0] SW Reset (R/W resets to 0) 0x0 = board not reset 0x1 = board is reset Software reset. When asserted, the board is reset: internal registers and counters are cleared and all state machines are brought to their idle states. Note that the programmable registers are NOT reset. This bit does not need to be cleared (it is self-clearing). Reads return 0. GEN GPL GTS GES DRDY SWT TMIS TES TR_S[1:0] DM_S[1:0] ENA ARM DME SRST DME Bit(s): [1] Diagnostic Mode Enable (read/write read returns set state of bit / resets to 0) 0x0 = Diagnostic mode is DISabled 0x1 = Diagnostic mode is ENAbled When enabled, the board is put into diagnostic mode, which allows control over the sequencing of the three data acquisition steps. This bit is set in conjunction with DM_SEL[1:0] to select the specific diagnostic mode the board should be put in. The board trigger is then used to sequence the diagnostic modes. Note that the board must still be ENAbled and ARMed before triggers can be received. ARM Bit(s): [2] ARM (R/W resets to 0) 0x0 = board is DISarmed and will not receive triggers 0x1 = board is ARMed and will receive and process triggers ARMs the board to begin receiving triggers. When set to 0 during an acq cycle, the action is the same as above. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 18 of 100 J. Dusatko /

5 ENA Bit(s): [3] ENAble (R/W resets to 0) 0x0 = data acquisition is disabled 0x1 = data acquisition is enabled Enables the board to begin acquiring data, boarm must be armed before receiving triggers. Note that if this bit is set to DISable during an acquisition cycle, the board will complete its current acq cycle and go into the DISable state. DM_S[1:0] Bit(s): [5:4] Diagnostic Mode Select (read/write read returns set state of bit / resets to 00) 0x0: Single-shot beam mode 0x1: Single-shot test mode 0x2: Single-shot baseline mode 0x3: Single-Step mode TR_S[1:0] Bit(s): [7:6] Trigger source select (r/w read returns set state of bits / resets to 0x0) 0x0: External Trigger 1 0x1: External Trigger 2 0x2: Software Trigger 0x3: <reserved> (currently selects SW Trigger) TES Bit(s): [8] Trigger Edge Select: source trigger activating edge select (R/W resets to 1) 0x1 = The positive (rising) edge of the source trigger will activate the module 0x0 = The negative (falling) edge of the source trigger will active the module Selects which edge of the input source trigger (selected by TR_S[1:0]) the module will trigger and perform its acquisition cycle on. Note that for the SW trigger this selection is somewhat nebulous, however the rising edge should be selected so that a trigger will occur when a one is written to the SW trigger bit. If the falling edge is selected, the trigger will occur when the SW trigger pulse falls. The timing of this depends upon the timing between the IP master and the module and can vary from cycle to cycle. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 19 of 100 J. Dusatko /

6 TMIS Bit(s): [9] Missed trigger status (R/W resets to 0 / reads back the set value / writing 1 clears this bit) Read: 0x0 = Trigger OK 0x1 = Trigger Missed Write: 0x0 = no effect 0x1 = clears bit This bit indicated whether a cycle of the 360Hz continuous trigger has been missed. It is a latching bit, and a one indicates if a trigger has been missed on the last 1/360 sec cycle. Writing a one clears this bit. Note that the updating of this bit is enabled by the ARM bit. SWT Bit(s): [10] Software trigger (R/W; inits to 0) 0x0 = No trigger 0x1 = Trigger Writing a 0x1 to this bit will cause the board to trigger if selected as the trigger source. This bit is self-clearing and does not need to be reset. Note that the trigger edge select affects how this bit is processed. Positive should be selected. Reads return 0. DRDY Bit(s): [11] Data ReaDY (R/W) 0x0 = Board data is NOT ready for readout 0x1 = Board data is READY for readout (write 0x1 clears) This bit indicates when the board has finished acquiring and processing its data (following a trigger) and is ready for readout. This bit is latched and must be cleared by writing a one to it. Note that the written one must be cleared back to zero. GES Bit: [12] Gate Generator Select (R/W) / resets to 0 0x0 = Standard Gate generator is selected 0x1 = Extended-width Gate generator is selected This is the extended-width gate generator select bit. When enabled, the extended width (32-bit) gate generator block is muxed in, while the standard-width (16-bit) gate generator is muxed out (see Fig 1). GTS Bit(s): [13] Gate Trigger Select R/W / resets to 0 0x0 = External trigger used 0x1 = SW trigger used The bit selects which trigger source the gate generator will use. Note that when the external trigger is selected, it will select whichever source the TR_S[1:0] bits are set to. Separate control is provided here for diagnostic purposes. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 20 of 100 J. Dusatko /

7 GPL Bit(s): [14] Gate Polarity R/W / resets to 1 0x0 = Gate signal polarity is Negative-True (low-going pulse) 0x1 = Gate signal polarity is Positive-True (high-going pulse) Controls the polarity of the charge integrator gate pulse. For most purposes, the polarity will always be positive. GEN Bit(s): [15] Gate Enable R/W / resets to 0 0x0 = Gate output is DISabled 0x1 = Gate output is Enabled Enables the generation of the gate signal. Bits [15:13], along with registers 0x000E & 0x0010 control the ADC integrator Gate signal. This signal opens and closes the charge integrating capacitor shorting switch. Open causes charge to collect on the integrating capacitor, closing causes the charge to be drained off, resetting the capacitor for the next measurement. These control bits control the enabling, polarity and trigger source. Note that in the voltage-sensitive version of the IP- QINT-ADC, the gate signal is not generated; and writing to these bits has no effect. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 21 of 100 J. Dusatko /

8 3.2 Module Control & Status Register 2 Name: CSR2 Offset: 0x0002 Mode: R/W This is the control and status register for the IP-QINT-ADC module. In contains bits that control the basic board functions and provides status as well. TDEL[7:0] PTS PPL PEN HRST D4L D2L D2L Bit(s): [0] 20MHz DCM Lock Status Read Only / Writes have no effect 0x0 = 20MHz DCM is NOT Locked 0x1 = 20MHz DCM IS Locked This bit gives the lock status of the 20MHz FPGA Digital Clock Manager, which uses the 80MHz board clock to generate its 20Mhz clock. This bit is essentially the lock bit from the internal PLL. D4L Bit(s): [1] 40MHz DCM Lock Status Read Only / Writes have no effect 0x0 = 40MHz DCM is NOT Locked 0x1 = 40MHz DCM IS Locked This bit gives the lock status of the 40MHz FPGA Digital Clock Manager, which uses the 80MHz board clock to generate its 40Mhz clock. This bit is essentially the lock bit from the internal PLL. HRST Bit(s): [3] HW Reset (R/W inits to 0) 0x0 = board not reset 0x1 = board is reset Hardware reset. When asserted, the board is reset: internal registers and counters are cleared and all state machines are brought to their idle states. The CSR1, CSR2 and CSR3 registers are NOT cleared and retain their original settings. Note that this operation is INVASIVE and the programmable registers ARE reset and must be re-initialized following the issuance of a HW reset. This bit does not need to be cleared (it is self-clearing). Reads return 0. PEN Bit(s): [4] Test Pulse Enable R/W / resets to 0 0x0 = Test Pulse output is DISabled IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 22 of 100 J. Dusatko /

9 0x1 = Test Pulse output is Enabled This bit enables the generation of the output test pulse (or heartbeat ) signal. PPL Bit(s): [5] Test Pulse Polarity R/W / resets to 1 0x0 = Test Pulse signal polarity is Negative-True (low-going pulse) 0x1 = Test Pulse signal polarity is Positive-True (high-going pulse) This bit controls the polarity of the output test pulse signal. PTS Bit(s): [6] Test Pulse Trigger Select R/W / resets to 0 0x0 = External trigger used 0x1 = SW trigger used The bit selects which trigger source the test pulse generator will use. Note that when the external trigger is selected, it will select whichever source the TR_S[1:0] bits are set to. Separate control is provided here for diagnostic purposes. <unused/reserved> Bit(s): [7, 3:2] Unused/Reserved Bit (Returns 0) These bits are unused and return 0 when read. Writing to it has no effect. TDEL[7:0] Bit(s): [15:8] Test Acquistion Delay Control (read/write read returns set state of bits / resets to 0x2E) This register controls the delay time between the assertion of the LED test pulse and the acquisition of the resultant detector output charge. The delay unit step size is 25ns. The minimum intrinsic delay, when the register is set to 0x00 is 2 counts due to internal logic delays. Therefore, qty = 2 counts must be added to the set value to reflect the actual delay quantity being generated. This register resets to a default value of 0x2E, which is equal to a delay of 1.2uS (46 counts + 2 for intrinsic delay = 48 counts at 25ns). This delay is set for the BLM system and accounts for the round-trip delays of the cables and the intrinsic delays of the detector and electronics. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 23 of 100 J. Dusatko /

10 3.3 Module Control & Status Register 3 Name: CSR3 Offset: 0x0004 Mode: R/W This is the control and status register for the IP-QINT-ADC module. In contains bits that control the basic board functions and provides status as well. PIC FBC RNG SYPL SYEN SYEN Bit(s): [0] Sync Output Enable (R/W resets to 0) 0x0 = Sync output is DISabled 0x1 = Sync output is ENAbled Sync output enable control. This bit controls whether the sync output will be asserted or not. SM_SEL[3:0] SMDE SYPL Bit(s): [1] Sync Pulse Polarity R/W / resets to 1 0x0 = Test Pulse signal polarity is Negative-True (low-going pulse or level) 0x1 = Test Pulse signal polarity is Positive-True (high-going pulse or level) This bit controls the polarity of the sync output pulse signal. SMDE Bit(s): [2] Sync Output Mode R/W / resets to 0 0x0 = Sync output is timed pulse mode 0x1 = Sync output is level (output = selected input = raw source signal) This bit controls the output mode of the syc signal. SM_SEL[3:0] Bit(s): [7:4] Sync output pulse source selection mux R/W / resets to 0x0 This bit field selects the source of the sync output signals. The selected signal, when asserted, will cause the sync pulse to be output (after the programmed delay). 0x0 = Trigger Signal 0x1 = Gate Signal 0x2 = ADC_Acq_Go signal 0x3 = Get_Beam_Data signal 0x4 = Get_Test_Data signal 0x5 = Get_Base_Data signal 0x6 = Get_Beam_Data Done signal 0x7 = Get_Test_Data Done signal IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 24 of 100 J. Dusatko /

11 0x8 = Get_Base_Data Done signal 0x9 = Sum_Fault_Beam Monitor Signal 0xA = Sum_Fault_Test Monitor Signal 0xB = Sum_Fault_Base Monitor Signal 0xC = SW Trigger 0xD = data_rdy (CAR1 DRDY bit) 0xE = data_rdr_clr 0xF = <reserved> RNG Bit(s): [11] ADC Range Control R/W / resets to 1 0x0 = ADC has +/-10V dynamic range 0x1 = ADC has +/-5V dynamic range (default setting) This bit controls ADC input voltage dynamic range. This bit should only be set during initialization, before the ADC receives at SW reset. Note that when in +/-5V range, the ADC has a resolution of 153uV/count; when in +/-10V range, the resolution changes to 305uV/count. Note the range should be set BEFORE SW_RST is issued. <unused/reserved> Bit(s): [13:12], [10:8] & [3] Unused/Reserved Bit (Returns 0) These bits are unused and return 0 when read. Writing to it has no effect. FBC Bit(s): [14] Force Baseline Clear Control R/W / resets to state set in gateware 0x0 = Baseline Correction is applied to incoming data 0x1 = Baseline Correction is NOT applied to incoming data This bit controls whether the Baseline Correction function is applied. When cleared, the baseline corrector functions normally, applying the baseline correction value calculated on the previous acq cycle to the incoming ADC samples. When this bit is set, the baseline correction holding register is kept is constant clear, essentially subtracting a value of 0x0000 from the incoming ADC samples. PIC Bit(s): [15] PIC mode bit Read Only / resets to state set in gateware 0x0 = Module is in BLM mode 0x1 = Module is in PIC mode This bit indicates the mode that the board is in. This bit is set in firmware and is read only. It is provided as status information for the developer. When is BLM mode, the module performs the acquisition sequenced as described in section 2.0 of this document. When in PIC mode, the module only performs a beam acquisition; this mode is described in Appendix A, PIC mode operation, of this document. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 25 of 100 J. Dusatko /

12 3.4 Trigger Delay Register Name: TRDEL Offset: 0x0006 Mode: R/W This register sets the delay time from the trigger input to actual beginning of the data acquisition cycle. The timing resolution is 25.0 ns per count. Note that there is an intrinsic delay latency of (3) clock cycles; this must be taken into account when setting the delay value. Trigger Assertion Delay Value TRIG_DLY Bit(s): [15:0] Trigger delay setting (R/W resets to 0 / read returns set value) 0x0000: minimum delay value = (3) 25ns clk40 cycles 75ns 0xFFFF: maximum setting ( = cycles ms) 1 count = 25ns This register controls the delay between the reception of the acquisition trigger and the actual beginning of the acquisition cycle. There is an intrinsic three cycle latency due to logic, thus 3 must be added to the decimal set value to reflect that actual delay setting. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 26 of 100 J. Dusatko /

13 3.5 Trigger Error Counter Name: TR_ERR Offset: 0x0008 Mode: R/W This register provides a count of the number of 360Hz triggers that have been missed per trigger cycle. That is, the counter will increment by one if the trigger is missed for each 1/360 cycle. A write to this register clears it to zero and re-arms the counter. Note that this counter is enabled by the ARM bit. TRIG_ERR_CNT[15:0] TRIG_ERR_CNT Bit(s): [15:0] Missing trigger error counter (R/W resets to 0 / read returns set value / write clears) Read: <The number of 360Hz triggers that have been missed per trigger cycle> Write: 0xXXXX = clears counter to 0x0000 and re-arms IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 27 of 100 J. Dusatko /

14 3.6 Test Pulse Generator Delay Register Name: TPDEL Offset: 0x000A Mode: R/W This register sets the delay time from trigger to actual assertion of the gate pulse signal. The timing resolution is 25ns per count. Note that there is an intrinsic delay latency of (2) clock cycles; this must be taken into account when setting the delay value. Test Pulse Assertion Delay Value TPDEL Bit(s): [15:0] ([MSB:LSB]) Test Pulse Delay Setting R/W / resets to 0x0000 0x0000: Minimum Delay Setting = (2) clock cycles due to latency 0x0001 0xFFFF: delay in cycles + 2 counts 3.7 Test Pulse Generator Width Register Name: TPWID Offset: 0x000C Mode: R/W This register sets the width of the gate pulse. The timing resolution is 25ns per count. The value set reflects the number of clock cycles the pulse will be asserted for. Note that a setting of 0x0000 will produce no output (zero width pulse). Note that this register initializes to its preset value of 0x0050, which corresponds to a width of 2.0uS. Test Pulse Width Value TPWID Bit(s): [15:0] ([MSB:LSB]) Test Pulse Width Setting R/W / resets to 0x0050 (2us default pulse width) 0x0000: no output 0x0001 0xFFFF: test pulse width in counts IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 28 of 100 J. Dusatko /

15 3.8 Gate Generator Delay Register Name: GDEL Offset: 0x000E Mode: R/W This register sets the delay time from trigger to actual assertion of the gate pulse signal. The timing resolution is 25ns per count. Note that there is an intrinsic delay latency of (2) clock cycles; this must be taken into account when setting the delay value. GATE Assertion Delay Value GDEL Bit(s): [15:0] ([MSB:LSB]) Gate Delay Setting R/W / resets to 0x0000 0x0000: Minimum Delay Setting = (2) clock cycles due to latency 0x0001 0xFFFF: delay in counts + 2 counts 3.9 Gate Generator Width Register Name: GWID Offset: 0x0010 Mode: R/W This register sets the width of the gate pulse. The timing resolution is 25ns per count. The value set reflects the number of clock cycles the pulse will be asserted for. Note that a setting of 0x0000 will produce no output (zero width pulse). The default setting for this register is 20uS (800 counts). GATE Pulse Width Value GWID Bit(s): [15:0] ([MSB:LSB]) Gate Width Setting R/W / resets to 0x0320 (20uS) 0x0000: no output 0x0001 0xFFFF: gate pulse width in counts IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 29 of 100 J. Dusatko /

16 3.10 Sync Generator Delay Register Name: SDEL Offset: 0x0012 Mode: R/W This register sets the delay time from trigger to actual assertion of the Sync pulse signal. The timing resolution is 25nS per count. Note that there is an intrinsic delay latency of (2) clock cycles; this must be taken into account when setting the delay value. GATE Assertion Delay Value SDEL Bit(s): [15:0] ([MSB:LSB]) Sync Delay Setting R/W / resets to 0x0000 0x0000: Minimum Delay Setting = (2) clock cycles due to latency 0x0001 0xFFFF: delay in counts + 2 counts 3.11 Sync Generator Width Register Name: SWID Offset: 0x0014 Mode: R/W This register sets the width of the sync pulse. The timing resolution is 25nS per count. The value set reflects the number of clock cycles the pulse will be asserted for. Note that a setting of 0x0000 will produce no output (zero width pulse). GATE Pulse Width Value SWID Bit(s): [15:0] ([MSB:LSB]) Sync Width Setting R/W / resets to 0x0000 0x0000: no output 0x0001 0xFFFF: gate pulse width in counts IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 30 of 100 J. Dusatko /

17 3.12 General-Purpose I/O Control Register Name: GIPO Offset: 0x0016 Mode: R/W This register controls the four General-Purpose Input/Output lines on the board. The are two generalpurpose inputs and two general-purpose outputs. The inputs are read-only bits and the outputs are read/write. Out_1 Out_0 In_1 In_0 In_0 Bit(s): [0] GPIO Input 0 (read only writes have no effect) 0x0 = input signal is logic 0 0x1 = input signal is logic 1 Note: Inputs are non-latching and reflect the current state of the external input signal. In_1 Bit(s): [1] GPIO Input 1 (read only writes have no effect) 0x0 = input signal is logic 0 0x1 = input signal is logic 1 Note: Inputs are non-latching and reflect the current state of the external input signal. Out_0 Bit(s): [4] GPIO Output 0 (read/write read returns set state of bit) 0x0 = output signal is logic 0 0x1 = output signal is logic 1 Note: Outputs are latched and held upon a write operation Out_1 Bit(s): [5] GPIO Output 1 (read/write read returns set state of bit) 0x0 = output signal is logic 0 0x1 = output signal is logic 1 Note: Outputs are latched and held upon a write operation IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 31 of 100 J. Dusatko /

18 3.13 Gate ADC Delay Register Name: GADEL Offset: 0x0018 Mode: R/W This register sets the delay time from the closing of the gate to the ADC sample go operation before the gate closes. Note that the delay is computed relative to the closing (rising edge) of the gate (see Fig. 5). The timing resolution is 25ns per count. Note that there is an intrinsic delay latency of (2) clock cycles; this must be taken into account when setting the delay value. When in charge-integrating mode, this register is used to time when to trigger the ADC to perform a convert sequence *before* the gate closes. Note that time is counted here from the CLOSING side of the gate and must be considered when setting the GDEL register. This delay should never be longer than the GDEL delay value. The default setting is 1uS before gate closing to trigger the ADC convert (for a 10uS default gate width setting). When the board is in voltage-sensitive mode and the gate signal is disabled, this register setting is still applicable. Rev 2 Change: In the Rev 2 version of the BLM QADC FPGA design, this register now controls the delay from the closing of the gate to the ADC sample go operation for the BEAM or TEST signal (see Fig. xy). It is the second ADC of two sampling operations performed during one gate interval. GATE ADC Delay Assertion Delay Value GADEL Bit(s): [15:0] ([MSB:LSB]) Gate ADC Delay Setting R/W / resets to 0x0028 (default delay value of 1uS) 0x0000: Minimum Delay Setting = (2) clock cycles due to latency 0x0001 0xFFFF: delay in counts + 2 counts IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 32 of 100 J. Dusatko /

19 3.14 Beam-to-Test Acq Delay Register Name: BTTDEL Offset: 0x001A Mode: R/W This register sets the delay time from the end of the Beam data acquisition to the start of the Test pulse generation / Test signal acquisition cycle. The timing resolution is 25nS per count. Note that there is an intrinsic delay latency of (1) clock cycle; this must be taken into account when setting the delay value. The absolute minimum delay setting must be 0x0001 (1 count). Beam-to-Test Cycle Delay Value BTTDEL Bit(s): [15:0] ([MSB:LSB]) Beam-to-Test Cycle Delay Setting R/W / resets to 0x8CA0 (900uS standard delay setting) 0x0001: Minimum Delay Setting = clock cycle due to latency 0x0001 0xFFFF: delay in counts + 1 count 3.15 Test-to-Base Acq Delay Register Name: TBLDEL Offset: 0x001C Mode: R/W This register sets the delay time from the end of the Test data acquisition to the start of the Baseline pulse acquisition cycle. The timing resolution is 25nS per count. Note that there is an intrinsic delay latency of (1) clock cycle; this must be taken into account when setting the delay value. The absolute minimum delay setting must be 0x0001 (1 count). Test-to-Base Cycle Delay Value TBLDEL Bit(s): [15:0] ([MSB:LSB]) Sync Width Setting R/W / resets to 0x8CA0 (900uS standard delay setting) 0x0000: Minimum Delay Setting = clock cycle due to latency 0x0001 0xFFFF: delay in counts + 1 count IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 33 of 100 J. Dusatko /

20 3.16 Channel Fault Status Registers There is one fault status register for each ADC channel on the board, for a total of eight fault status registers. Note that although there are actually 12 physical ADC channels, only eight are used for the charge integration operation. The remaining four channels are used to monitor the board s power supply and ground rails (see ADC registers section). The address mapping of the fault registers is provided below in tabular format. Following this, a generic bit mapping description is provided. Note that the bit mapping and descriptions are the same for all channels. Address Channel Description 0x Channel 0 Accum d Dose Fault Status 0x Channel 1 Accum d Dose Fault Status 0x Channel 2 Accum d Dose Fault Status 0x Channel 3 Accum d Dose Fault Status 0x Channel 4 Accum d Dose Fault Status 0x002A 5 Channel 5 Accum d Dose Fault Status 0x002C 6 Channel 6 Accum d Dose Fault Status 0x002E 7 Channel 7 Accum d Dose Fault Status Chan_n FAULT Register Name: Fault_Chan_n Offset: 0x002i (i = 0,2,4,6,8,A,C,E) Mode: Read Only This register contains the raw (unlatched) fault status bits for each ADC channel. The bits are set when the particular data tap value strays beyond the high/low window that is set by the respective high/low threshold registers. QBLH QBLL T1H T1L QTH QTL B60H B60L B30H B30L B10H B10L B1H B1L QBH QBL QBL Bit(s): [0] Beam Raw Charge Low Fault (raw: non-accumulated Beam charge measurement) QBH Bit(s): [1] Beam Raw Charge High Fault (raw: non-accumulated Beam charge measurement) IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 34 of 100 J. Dusatko /

21 B1L Bit(s): [2] Beam 1 Sec Accum Low Fault B1H Bit(s): [3] Beam 1 Sec Accum High Fault B10L Bit(s): [4] Beam 1/10 Sec Accum Low Fault B10H Bit(s): [5] Beam 1/10 Sec Accum High Fault B30L Bit(s): [6] Beam 1/30 Sec Accum Low Fault B30H Bit(s): [7] Beam 1/30 Sec Accum High Fault B60L Bit(s): [8] Beam 1/60 Sec Accum Low Fault B60H Bit(s): [9] Beam 1/60 Sec Accum High Fault QTL Bit(s): [10] Test Raw Charge Low Fault (raw: non-accumulated Test charge measurement) IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 35 of 100 J. Dusatko /

22 QTH Bit(s): [11] Test Raw Charge High Fault (raw: non-accumulated Test charge measurement) T1L Bit(s): [12] Test 1 Sec Accum Low Fault T1H Bit(s): [13] Test 1 Sec Accum High Fault QBLL Bit(s): [14] Baseline Raw Charge Low Fault (raw: most-recently measured pedestal value) QBLH Bit(s): [15] Baseline Raw Charge High Fault (raw: most-recently measured pedestal value) IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 36 of 100 J. Dusatko /

23 3.17 Channel Latched Fault Status Registers These registers have the same function as the Fault Status registers described in section 3.12, except that they are latched. Thus when a fault is generated, the respective fault bit is set and held until cleared. The fault bit is cleared by writing a logic one to the respective bit slot. The address mapping of the latched fault registers is provided below in tabular format. Following this, a generic bit mapping description is provided. Note that the bit mapping and descriptions are the same for all channels. Address Channel Description 0x Channel 0 Accum d Dose Latched Fault Status 0x Channel 1 Accum d Dose Latched Fault Status 0x Channel 2 Accum d Dose Latched Fault Status 0x Channel 3 Accum d Dose Latched Fault Status 0x Channel 4 Accum d Dose Latched Fault Status 0x003A 5 Channel 5 Accum d Dose Latched Fault Status 0x003C 6 Channel 6 Accum d Dose Latched Fault Status 0x003E 7 Channel 7 Accum d Dose Latched Fault Status Chan_n LATCHED FAULT Register Name: Fault_Chan_n Offset: 0x003i (i = 0,2,4,6,8,A,C,E) Mode: Read/Write This register contains the latched fault status bits for each ADC channel. The bits are set when the particular data tap value strays beyond the high/low window that is set by the respective high/low threshold registers. Writing a logic one to a respective bit position clears that fault bit. LQBLH LQBLL LT1H LT1L LQTH LQTL LB60H LB60L LB30H LB30L LB10H LB10L LB1H LB1L LQBH LQBL LQBL Bit(s): [0] Beam Raw Charge Low Fault (raw: non-accumulated Beam charge measurement) LQBH Bit(s): [1] Beam Raw Charge High Fault (raw: non-accumulated Beam charge measurement) IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 37 of 100 J. Dusatko /

24 LB1L Bit(s): [2] Beam 1 Sec Accum Low Fault LB1H Bit(s): [3] Beam 1 Sec Accum High Fault LB10L Bit(s): [4] Beam 1/10 Sec Accum Low Fault LB10H Bit(s): [5] Beam 1/10 Sec Accum High Fault LB30L Bit(s): [6] Beam 1/30 Sec Accum Low Fault LB30H Bit(s): [7] Beam 1/30 Sec Accum High Fault LB60L Bit(s): [8] Beam 1/60 Sec Accum Low Fault LB60H Bit(s): [9] Beam 1/60 Sec Accum High Fault IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 38 of 100 J. Dusatko /

25 LQTL Bit(s): [10] Test Raw Charge Low Fault (raw: non-accumulated Test charge measurement) LQTH Bit(s): [11] Test Raw Charge High Fault (raw: non-accumulated Test charge measurement) LT1L Bit(s): [12] Test 1 Sec Accum Low Fault LT1H Bit(s): [13] Test 1 Sec Accum High Fault LQBLL Bit(s): [14] Baseline Raw Charge Low Fault (raw: most-recently measured pedestal value) LQBLH Bit(s): [15] Baseline Raw Charge High Fault (raw: most-recently measured pedestal value) IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 39 of 100 J. Dusatko /

26 3.18 Summary Faults Register 0 Name: Sum_Faults_0 Offset: 0x0040 Mode: Read Only This register contains the raw (unlatched) fault status bits for each ADC channel s Beam and Test data faults. The bits are set when the particular data tap value strays beyond the high/low window that is set by the respective high/low threshold registers. TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 SB0 Bit(s): [0] Summary Beam Faults Channel 0 SB1 Bit(s): [1] Summary Beam Faults Channel 1 SB2 Bit(s): [2] Summary Beam Faults Channel 2 SB3 Bit(s): [3] Summary Beam Faults Channel 3 SB4 Bit(s): [4] Summary Beam Faults Channel 4 SB5 Bit(s): [5] Summary Beam Faults Channel 5 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 40 of 100 J. Dusatko /

27 SB6 Bit(s): [6] Summary Beam Faults Channel 6 SB7 Bit(s): [7] Summary Beam Faults Channel 7 TB0 Bit(s): [8] Summary Test Faults Channel 0 TB1 Bit(s): [9] Summary Test Faults Channel 1 TB2 Bit(s): [10] Summary Test Faults Channel 2 TB3 Bit(s): [11] Summary Test Faults Channel 3 TB4 Bit(s): [12] Summary Test Faults Channel 4 TB5 Bit(s): [13] Summary Test Faults Channel 5 TB6 Bit(s): [14] Summary Test Faults Channel 6 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 41 of 100 J. Dusatko /

28 TB7 Bit(s): [15] Summary Test Faults Channel 7 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 42 of 100 J. Dusatko /

29 3.19 Summary Faults Register 1 Name: Sum_Faults_1 Offset: 0x0042 Mode: Read Only This register contains the raw (unlatched) fault status bits for each ADC channel s baseline data and three grand fault bits that sum the individual faults for each of the three (beam/test/base) data types. The bits are set when the particular data tap value strays beyond the high/low window that is set by the respective high/low threshold registers. GBFS GTFS GBLS SBL7 SBL6 SBL5 SBL4 SBL3 SBL2 SBL1 SBL0 SBL0 Bit(s): [0] Summary BaseLine Faults Channel 0 SBL1 Bit(s): [1] Summary BaseLine Faults Channel 1 SBL2 Bit(s): [2] Summary BaseLine Faults Channel 2 SBL3 Bit(s): [3] Summary BaseLine Faults Channel 3 SBL4 Bit(s): [4] Summary BaseLine Faults Channel 4 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 43 of 100 J. Dusatko /

30 SBL5 Bit(s): [5] Summary BaseLine Faults Channel 5 SBL6 Bit(s): [6] Summary BaseLine Faults Channel 6 SBL7 Bit(s): [7] Summary BaseLine Faults Channel 7 <unused> Bit(s): [8:12] Unused bits, returns 0x0 GBLS Bit(s): [13] Grand BaseLine Fault Summary (all channels) GTFS Bit(s): [14] Grand Test Fault Summary (all channels) GBFS Bit(s): [15] Grand Beam Fault Summary (all channels) IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 44 of 100 J. Dusatko /

31 3.20 Summary Latched Faults Register 0 Name: Lat_Sum_Faults_0 Offset: 0x0044 Mode: Read Only This register contains the summary latched fault status bits for each ADC channel s Beam and Test data faults. The bits are set when the particular data tap value strays beyond the high/low window that is set by the respective high/low threshold registers. Note that the latch is cleared when the respective bits are written to in the Latched Faults registers. All fault bits must be cleared before the respective latched summary faults can be cleared. Writing a logic one to a respective bit position clears that fault bit. TB7 TB6 TB5 TB4 TB3 TB2 TB1 TB0 SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0 LSB0 Bit(s): [0] Latched Summary Beam Faults Channel 0 LSB1 Bit(s): [1] Latched Summary Beam Faults Channel 1 LSB2 Bit(s): [2] Latched Summary Beam Faults Channel 2 LSB3 Bit(s): [3] Latched Summary Beam Faults Channel 3 LSB4 Bit(s): [4] Latched Summary Beam Faults Channel 4 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 45 of 100 J. Dusatko /

32 LSB5 Bit(s): [5] Latched Summary Beam Faults Channel 5 LSB6 Bit(s): [6] Latched Summary Beam Faults Channel 6 LSB7 Bit(s): [7] Latched Summary Beam Faults Channel 7 LTB0 Bit(s): [8] Latched Summary Test Faults Channel 0 LTB1 Bit(s): [9] Latched Summary Test Faults Channel 1 LTB2 Bit(s): [10] Latched Summary Test Faults Channel 2 LTB3 Bit(s): [11] Latched Summary Test Faults Channel 3 LTB4 Bit(s): [12] Latched Summary Test Faults Channel 4 LTB5 Bit(s): [13] Latched Summary Test Faults Channel 5 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 46 of 100 J. Dusatko /

33 LTB6 Bit(s): [14] Latched Summary Test Faults Channel 6 LTB7 Bit(s): [15] Latched Summary Test Faults Channel 7 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 47 of 100 J. Dusatko /

34 3.21 Summary Latched Faults Register 1 Name: Lat_Sum_Faults_1 Offset: 0x0046 Mode: Read Only This register contains the summary latched fault status bits for each ADC channel s baseline data and three grand fault bits that sum the individual faults for each of the three (beam/test/base) data types. The bits are set when the particular data tap value strays beyond the high/low window that is set by the respective high/low threshold registers. Writing a logic one to a respective bit position clears that fault bit. GBFS GTFS GBLS SBL7 SBL6 SBL5 SBL4 SBL3 SBL2 SBL1 SBL0 LSBL0 Bit(s): [0] Latched Summary BaseLine Faults Channel 0 LSBL1 Bit(s): [1] Latched Summary BaseLine Faults Channel 1 LSBL2 Bit(s): [2] Latched Summary BaseLine Faults Channel 2 LSBL3 Bit(s): [3] Latched Summary BaseLine Faults Channel 3 LSBL4 Bit(s): [4] Latched Summary BaseLine Faults Channel 4 IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 48 of 100 J. Dusatko /

35 LSBL5 Bit(s): [5] Latched Summary BaseLine Faults Channel 5 LSBL6 Bit(s): [6] Latched Summary BaseLine Faults Channel 6 LSBL7 Bit(s): [7] Latched Summary BaseLine Faults Channel 7 <unused> Bit(s): [8:12] Unused bits, returns 0x0 LGBLS Bit(s): [13] Latched Grand BaseLine Fault Summary (all channels) LGTFS Bit(s): [14] Latched Grand Test Fault Summary (all channels) LGBFS Bit(s): [15] Latched Grand Beam Fault Summary (all channels) IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 49 of 100 J. Dusatko /

36 3.22 Extended Gate Generator Delay Register Name: EGDEL Offset: 0x0048 Mode: R/W This register sets the delay time from trigger to actual assertion of the extended gate pulse signal. The timing resolution is 25ns per count. Note that there is an intrinsic delay latency of (2) clock cycles; this must be taken into account when setting the delay value. EGATE Assertion Delay Value EGDEL Bit(s): [15:0] ([MSB:LSB]) Gate Delay Setting R/W / resets to 0x0000 0x0000: Minimum Delay Setting = (2) clock cycles due to latency 0x0001 0xFFFF: delay in counts + 2 counts 3.23 Extended Gate Generator Width Register Low Name: EGWID_L Offset: 0x004A Mode: R/W This register sets the lower 16-bit width of the 32-bit gate pulse width value. The timing resolution is 25ns per count. The value set reflects the number of clock cycles the pulse will be asserted for. Note that a setting of 0x0000 will produce no output (zero width pulse). The default setting for this register is 0x86A0 (34464 counts), which when combined with EGWID_H gives a gate width of 2.5mS. EGATE Pulse Width Value Low EGWID_L Bit(s): [15:0] ([MSB:LSB]) Extended Gate Width Setting / Lower 16-bits (bits[15:0] of [31:0]) Mapping is EGWID_H[15:0] Ext GATE Width[15:0] R/W / resets to 0x86A0 (lower portion of 2.5mS delay) 0x0000: no output 0x0001 0xFFFF: gate pulse width in counts IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 50 of 100 J. Dusatko /

37 3.24 Extended Gate Generator Width Register High Name: EGWID_H Offset: 0x004C Mode: R/W This register sets the upper 16-bit width of the 32-bit gate pulse width value. The timing resolution is 25ns per count. The value set reflects the number of clock cycles the pulse will be asserted for. Note that a setting of 0x0000 will produce no output (zero width pulse). The default setting for this register is 0x0001, which when combined with the default setting of EGWID_L amounts to 2.5ms EGATE Pulse Width Value High EGWID_H Bit(s): [15:0] ([MSB:LSB]) Extended Gate Width Setting / Upper 16-bits (bits[31:16] of [31:0]) Mapping is EGWID_H[15:0] Ext GATE Width[31:16] R/W / resets to 0x0001 0x0000: no output 0x0001 0xFFFF: gate pulse width in counts 3.25 Extended Gate ADC Delay Register Name: EGADEL Offset: 0x004E Mode: R/W This register sets the delay time from trigger to actual assertion of the Sync pulse signal. The timing resolution is 25ns per count. Note that there is an intrinsic delay latency of (2) clock cycles; this must be taken into account when setting the delay value. When in charge-integrating mode, this register is used to time when to trigger the ADC to perform a convert sequence *before* the gate closes. Note that time is counted here from the CLOSING side of the gate and must be considered when setting the EGDEL_H & EGDEL_H registers. This delay should never be longer than the EGDEL delay value. The default setting is 2uS before gate closing to trigger the ADC convert (for a 20uS default gate width setting). When the board is in voltage-sensitive mode and the gate signal is disabled, this register setting is not applicable. EGATE Assertion Delay Value IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 51 of 100 J. Dusatko /

38 EGADEL Bit(s): [15:0] ([MSB:LSB]) Extended Gate ADC Delay Setting R/W / resets to 0x0050 (default delay value of 2uS) 0x0000: Minimum Delay Setting = (2) clock cycles due to latency 0x0001 0xFFFF: delay in counts + 2 counts IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 52 of 100 J. Dusatko /

39 3.26 Gate Ped ADC Delay Register Name: GPADEL Offset: 0x001E Mode: R/W This register sets the delay time from the opening of the gate to the ADC sample go operation. This ADC sample is typically the pedestal/baseline. Note that the delay is computed relative to the opening (falling edge) of the gate (see Fig. xy). The timing resolution is 25ns per count. Note that there is an intrinsic delay latency of (3) clock cycles; this must be taken into account when setting the delay value. When in charge-integrating mode, this register is used to time when to trigger the ADC to perform a convert sequence relative to time after the opening of the gate. Note that time is counted here from the OPENING side of the gate and must be considered when setting the GWID register. This delay should never be longer than the GWID delay value and one must also consider the placement in time of the GADEL setting as well as the 3us intrinsic ADC convert time. The default setting is 1uS after gate opening to trigger the ADC convert (for a 10uS default gate width setting). When the board is in voltage-sensitive mode and the gate signal is disabled; however, this register setting is still applicable. GATE PED ADC Sample Assertion Delay Value GPADEL Bit(s): [15:0] ([MSB:LSB]) Gate ADC Delay Setting R/W / resets to 0x0028 (default delay value of 1uS) 0x0000: Minimum Delay Setting = (3) clock cycles due to latency 0x0001 0xFFFF: delay in counts + 3 counts IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 53 of 100 J. Dusatko /

40 3.27 Acquisition Counter Low Register Name: ACQ_CNT_L Offset: 0x0050 Mode: R/W This register is the lower 16-bit word of the 32-bit acquisition counter. This counter is incremented by one every time the DRDY bit (CSR1_[11]) is set. Note that DRDY still needs to be cleared before the next acquisition cycle for the counter to increment. The counter will roll-over to zero when its maximum value + 1 has been reached. The counter (all 32-bits) can be reset to zero with a write operation (data value = don t care) to this register. The full counter is the concatenation of this register (ACQ_CNT_L) and the ACQ_CNT_H register. Acquisition Counter (ACQ_CNT_L) bits D[15:0] ACQ_CNT_L Bit(s): [15:0] ([MSB:LSB]) Acquisition Counter Low (bits D[15:0]) R/W / resets to 0x0000 upon a Write operation of data 0xXXXX (don t care) 3.28 Acquisition Counter High Register Name: ACQ_CNT_H Offset: 0x0052 Mode: R/W This register is the upper 16-bit word of the 32-bit acquisition counter. This counter is incremented by one every time the DRDY bit (CSR1_[11]) is set. Note that DRDY still needs to be cleared before the next acquisition cycle for the counter to increment. The counter will roll-over to zero when its maximum value + 1 has been reached. The counter (all 32-bits) can be reset to zero with a write operation (data value = don t care) to this register. The full counter is the concatenation of this register (ACQ_CNT_H) and the ACQ_CNT_L register. Acquisition Counter (ACQ_CNT_H) bits D[31:16] ACQ_CNT_H Bit(s): [15:0] ([MSB:LSB]) Acquisition Counter High (bits D[31:16]) R/W / resets to 0x0000 upon a Write operation of data 0xXXXX (don t care) IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 54 of 100 J. Dusatko /

41 Acquisition counter concatenation operation: IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 55 of 100 J. Dusatko /

42 4.0 IP Memory Space Registers Referring to Section 0, IP-QINT-ADC IP Memory Space Memory Map, it can be seen that the module s memory space is divided into five regions: Shift Register Data, Channel Dose Data / Fault Threshold, RAW ADC data, Baseline Data and Accumulator Raw Data. The details of each region will be described in the following subsections, going from the bottom address and progressing upwards thru the memory map. 4.1 Beam/Test/Baseline Shift Register Raw Data Region: 0x x00437E Mode: Read Only The data contained in this region of the IP module s memory space is the RAM-based shift register data for each channel s data type (Beam, Test and Baseline). The locations, based on data type are listed below. Note that the shift register uses a dynamic pointer in a circular buffer arrangement, with the pointer indicating the most recently written data. The shift register data is part of the AAC subsystem and readout of the raw values is only necessary for diagnostic purposes. Beam Shift Register Data (360 words / channel) Channel Start Address End Address 0 0x x0002CE 1 0x0002D0 0x00059E 2 0x0005A0 0x00086E 3 0x x000B3E 4 0x000B40 0x000E0E 5 0x000E10 0x0010DE 6 0x0010E0 0x0013AE 7 0x0013B0 0x00167E Test Shift Register Data (360 words / channel) Channel Start Address End Address 0 0x x00194E 1 0x x001C1E 2 0x001C20 0x001EEE 3 0x001EF0 0x0021BE 4 0x0021C0 0x00248E 5 0x x00275E 6 0x x002A2E 7 0x002A30 0x002CFE Baseline Shift Register Data (360 words / channel) Channel Start Address End Address 0 0x002D00 0x002FCE 1 0x002FD0 0x00329E 2 0x0032A0 0x00356E 3 0x x00383E 4 0x x003B0E 5 0x003B10 0x003DDE 6 0x003DE0 0x00404E 7 0x0040B0 0x00437E IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 56 of 100 J. Dusatko /

43 Shift Register Data Format Mode: Read Only Width: 16-bits Format: Two s Complement This shift register data consists of 360 words of time-delayed ADC sample data. Therefore a shift register word is in ADC data format. Shift Register Data Word Word_n Bit(s): [15:0] ([MSB:LSB]) ADC Data Two s Complement ADC Step Size: 152 μv / count Maximum Positive Value: 0x7FFF = = V Maximum Positive Value: 0x8000 = = V Rev 2 changes: The Baseline region (0x002D00 0x00437E) of the shift register memory is no longer used do to the modifications in the Acquisition and Baseline Subtraction processing. This memory region will now return 0x0000 if read from. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 57 of 100 J. Dusatko /

44 4.2 Channel Dose Data / Fault Threshold Region: 0x x Mode: Read and Write This region contains both the accumulated (integrated) dose data as well as the programmable threshold registers. There is one set of (25) registers for each ADC data channel. The registers (for each data type: beam, test, baseline) consist of the baseline correction value, the current (baseline corrected) measurement value, the accumulated measurement values at specific times and the high and low threshold settings. A memory map of this arrangement is shown on the next page. Note that this register map is repeated for each channel. A table of the channel addresses is listed below: Channel Range 0 0x x0050FF 1 0x x0051FF 2 0x x0052FF 3 0x x0053FF 4 0x x0054FF 5 0x x0055FF 6 0x x0056FF 7 0x x0057FF Accumulated Dose Data / Fault Threshold Address Table Note that the channel data (current measurement, accumulated dose and baseline value) is updated each trigger cycle. Register Descriptions: Following the memory map shown on the next page, each specific register is described in detail. IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 58 of 100 J. Dusatko /

45 16-bits 0x005(n+1)XX 0x005(n+1)00 0x005nFF 0x005n32 Channel (n+1) <Reserved> 0x005n30 Chan n Base_Thresh_High_1 0x005n2E Chan n Base_Thresh_Low_1 0x005n2C 0x005n2A Chan n Test_Thresh_High_1 Chan n Test_Thresh_Low_1 Upper 16-bit Thresh Words 0x005n28 Chan n Beam_Thresh_High_1 0x005n26 0x005n24 0x005n22 Chan n Beam_Thresh_Low_1 Chan n Base_Thresh_High_0 Chan n Base_Thresh_Low_0 Fault Threshold Setting value 32-bit (two's compliment format) 0x005n20 0x005n1E Chan n Test_Thresh_High_0 Chan n Test_Thresh_Low_0 Lower 16-bit Thresh Words 0x005n1C Chan n Beam_Thresh_High_0 0x005n1A Chan n Beam_Thresh_Low_0 X8 Chan 0: Chan 1: Chan 2: Chan 3: Chan 4: Chan 5: Chan 6: Chan 7: 0x x0050FF 0x x0051FF 0x x0052FF 0x x0053FF 0x x0054FF 0x x0055FF 0x x0056FF 0x x0057FF 0x005n18 0x005n16 0x005n14 0x005n12 0x005n10 0x005n0E Chan n Q 1_Test_H Chan n Q 1_Test_L Chan n Q 0 Test Chan n Q 60_Beam_H Chan n Q 60_Beam_L Chan n Q 30_Beam_H Accumlated Test Dosage Data (two s compliment format / pedestal auto-subtracted) Current Test Dose (2's comp / ped subtr.) 0x005n0C 0x005n0A Chan n Q 30_Beam_L Chan n Q 10_Beam_H Accumlated Deam Dosage Data (two s compliment format / pedestal auto-subtracted) 0x005n08 Chan n Q 10_Beam_L 0x005n06 Chan n Q 1_Beam_H 0x005n04 Chan n Q 1_Beam_L 0x005n02 Chan n Q 0 Beam Current Beam Dose (2's comp / ped subtr.) Offset + 0x005n00 Chan n Beam Baseline Beam Baseline (pedestal) value (2's comp) Note: n = [0:7] IP-QINT-ADC Accum/Avg/Compare Module Register Map IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 59 of 100 J. Dusatko /

46 4.2.1 Channel n Baseline Register Name: Chan_n Baseline Offset: 0x005n00 (n = 0...7) Mode: Read Only Width: 16-bits Format: Two s Complement This register contains the current computed baseline correction data value. During each trigger cycle, after the Beam and Test data is collected, a baseline measurement is taken. This measurement takes a measurement of the detector when no beam or test signal is present. In this way, a measurement of the baseline (pedestal or dark) offset present in the detector electronics is measured. This measurement is also accumulated over a period of one second (for 360 samples) with the 360 th sample subtracted from current sample value. The accumulated value is then divided by 360 (to normalize it to the current ADC sample size) and then stored into the baseline correction memory (one value for each channel). This data value is then subtracted from each Beam- and Test- ADC sample. Note that each acquisition cycle uses the previous cycle s computed baseline value (because the current cycle computes a new baseline correction). Change for new pedestal measurement technique: This register contains the value of the Baseline (Pedestal) measurement made during the Beam measurement interval. This is considered more relevant and is provided in this register. Channel n Baseline Data Baseline Data Bit(s): [15:0] ([MSB:LSB]) Baseline Correction Factor Two s Complement ADC Step Size: 152 μv / count Maximum Positive Value: 0x7FFF = = V Maximum Positive Value: 0x8000 = = V IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 60 of 100 J. Dusatko /

47 4.2.2 Channel n Current Beam Charge Value Name: Chan_n Q 0 Beam Offset: 0x005n02 (n = 0...7) Mode: Read Only Width: 16-bits Format: Two s Complement This register contains the current baseline-corrected beam charge measurement. This data has been acquired from the trigger for this data cycle. Channel n Q 0 Beam Current Beam Charge Data Bit(s): [15:0] ([MSB:LSB]) Baseline Correction Factor Two s Complement ADC Step Size: 152 μv / count Maximum Positive Value: 0x7FFF = = V Maximum Positive Value: 0x8000 = = V IP_QINT_ADC_SW_Prog_Guide_V4d0.doc Page 61 of 100 J. Dusatko /