Registers and Counters

Transcription

1 Registers and Counters A register is a group of flip-flops which share a common clock An n-bit register consists of a group of n flip-flops capable of storing n bits of binary information May have combinational gates that perform certain dataprocessing tasks A counter is essentially a register that goes through a predetermined sequence of binary states Gates in the counter are connected in such a way as to produce the prescribed sequence of states 1

2 Basic Registers Various types of registers are available commercially Simplest register is one that consists of only flip-flops, without any gates Figure shows a register constructed with four D flip-flops to form a four-bit data storage register Common clock input triggers all flip-flops on the positive edge of each pulse Binary data at the 4-bit inputs (I) are transferred into the register after the clock edge and are available at the output (A) Active-low reset (Clear) sets all registers to zero asynchronously 2

3 Parallel Load Registers Useful to have a condition as to when to load a register with data Figure shows a 4-bit parallel load register with a Load or Enable Load input determines the action to be taken with each clock pulse When 1, the data at the inputs (I) are transferred into the register with the next positive edge of the clock When 0, the outputs of the flip-flops are connected to their respective inputs and loaded back into the register at the next positive clock edge Preferred method since the clock is not gated (which could cause synchronization issues) 3

4 Parallel Load Register HDL Can use if or case to infer a MUX before the flip-flop Depending on synthesizer and cells available, you may be able to exclude the else or default condition and it will use a flip-flop with enable option // Verilog-2001 module pl_reg (output reg [3:0] A, input CK, Load, input [3:0] I); CK) begin if (Load) A <= I; else A <= A; // or: case (Load) 0: A <= A; 1: A <= I; endcase end endmodule 4

5 Shift Register A shift register is capable of shifting the binary information held in each cell to its neighboring cell, in a selected direction Consists of a chain of flip-flops in cascade, with the output of one flip-flop connected to the input of the next flip-flop All flip-flops receive the same clock Figure shows a simple shift register which can only shift right (unidirectional) 5

6 Shift Register When enabled (Enable=1), the shift register moves data from D0 to serial out (SO), D1 to D0, D2 to D1, D3 to D2, and serial in (SI) to D3 When disabled (Enable=0), output from each flip-flop cycles back to input We always assume flip-flop setup and hold times are not violated (Warning: The text book shows unfavorable designs, ie. gated clocks, and elects later to correct them) 6

7 Parallel Load Shift Register HDL Use concatenation and bit ranges to implement shift registers: {SI,D[3:1]} is the same as {SI,D[3],D[2],D[1]} // Verilog-2001 module pl_sreg (output reg SO, input CK, Enable, SI); reg [3:0] D; CK) begin SO <= D[0]; if (Enable) D <= {SI,D[3:1]}; else D <= D; end endmodule 7

8 Generic Parallel Load Shift Register HDL Can use parameters to make code generic to any configuration Should use before defining I/O bit widths Instantiate module later with different parameters (example): pl_sreg #(4) U0 (SO,CK,Enable,SI); pl_sreg #(8) U1 (SO2,CK,Enable,SO); // Verilog-95 module pl_sreg (SO, CK, Enable, SI); parameter n = 4; output SO; input CK, Enable, SI; reg SO; reg [n-1:0] D; CK) begin SO <= D[0]; if (Enable) D <= {SI,D[n-1:1]}; else D <= D; end endmodule 8

9 Serial Transfer The datapath of a digital system is said to operate in serial mode when information is transferred and manipulated one bit at a time In contrast to parallel transfer, whereby all the bits of the register are transferred at the same time Most operations are performed in parallel because it is a faster whereas serial operations are slower because a datapath operation takes several clock cycles Serial operations have the advantage of requiring fewer hardware components and in some cases can operate at higher clocks speed than parallel operations 9

10 Serial Transfer Serial transfer of information from register A to register B is done with shift registers To avoid reloading of register A, its output is fed back to its input for this example As the clock pulses, the initial contents of register B are shifted out through its serial output (may be transferred to a third shift register) The Enable and Clock determine when the shift happens After 4 enabled pulses, register A is back to it s initial value and register B has the contents of register A 10

11 Serial Adder Parallel adder shown adds number by using cascading full adders For a serial implementation, one bit of each inputs A, B, and C are shifted in, starting at the LSB, processed by the full adder, and the results S and C are stored One possibility is to save the sum (S) back into A to accumulate future results over time Only the previous carry (C) needs to be remembered 11

12 Serial Adder Example: Add Serial adder stores result in augend; it is accumulated C 0 is initially 0 (cycle 0) Sum is stored in Augend MSB every cycle Addend MSB gets new Addend every cycle Carry register stores only the current carry Add more numbers by shifting in via Serial Input (SI) on addend Additional control required to coordinate resets 12

13 Serial Adder: Alternate Design Uses separate shift registers for input and output Still requires only one FA 13

14 Universal Shift Register (USR) Use larger MUX to allow for more options Depending on Mode, USR can: 00: Preserve previous A 01: Shift right (MSB serial in, A[0] serial out) 10: Shift left (LSB serial in, A[3] serial out) 11: Load in a parallel value from I 14

15 Generic Universal Shift Register HDL For Verilog 2001+, parameters must be declared before ports Clear is active high // Verilog-2001 module univ_sreg #(parameter n=4) (output reg [n-1:0] A, input CK, Clear, MSB, LSB, input [1:0] Mode, input [n-1:0] I); CK, posedge Clear) begin if (Clear) A <= 0; else begin case (Mode) 0: A <= A; 1: A <= {MSB,A[n-1:1]}; 2: A <= {A[n-2:0],LSB}; default: A <= I; endcase end end endmodule 15

16 Synchronous Counters Skipping Ripple Counters (Section 6.3) Uses gated clocks Domino triggers Creates bad habits; avoid them Focus on Synchronous counters All flip-flops use the same clock Similar to creating state machine circuits from state tables (chapter 5) Only present state influences next state 16

17 Binary Up Counter Simple design Can do by inspection or by using state tables Use T flip-flops Can use others, but T is often easier for counters XOR preceding D flip-flop Present State Next State Flip-Flop Inputs A 3 A 2 A 1 A 0 A 3 A 2 A 1 A 0 T A 3 T A 2 T A 1 T A

18 Binary Up Counter Flip-Flop inputs: T A0 = 1 T A1 = A 0 T A2 = A 1 A 0 T A3 = A 2 A 1 A 0 = A 2 T A2 Scales up easily T A0 can be the enable signal 18

19 Binary Down Counter Simple design Can do by inspection or by using state tables Will use T flipflops again Present State Next State Flip-Flop Inputs A 3 A 2 A 1 A 0 A 3 A 2 A 1 A 0 T A 3 T A 2 T A 1 T A

20 Binary Down Counter Flip-Flop inputs: T A0 = 1 T A1 = A 0 ' T A2 = A 1 'A 0 ' T A3 = A 2 'A 1 'A 0 ' = A 2 'T A2 Scales up easily T A0 can be the enable signal 20

21 Binary Up/Down Counter Combine both designs together Place a MUX before AND gates to select A n or A n ' with signal UpDown 21

22 BCD Counter Present State Next State Output Flip-Flop Inputs A 3 A 2 A 1 A 0 A 3 A 2 A 1 A 0 y T A 3 T A 2 T A 1 T A Output y used to trigger next digit 22

23 BCD Counter Use state table with T flip-flops T A0 = 1 T A1 = A 3 'A 0 T A2 = A 1 A 0 T A3 = A 3 A 0 + A 2 A 1 A 0 y = A 3 A 0 23

24 Binary Up/Down Counter with Load 24

25 Generic Binary Up/Down Counter (with Load) HDL Use if to avoid considering all cases since there are multiple inputs (UpDown, Enable, Load) instead of one (ie. Mode from previous example) Only need begin/end with more than a single statement If/elses are chained // Verilog-2001 module binupdownload #(parameter n=4)(output reg [n-1:0] A, input CK, Clear, UpDown, Enable, Load, input [n-1:0] I); CK, posedge Clear) begin if (Clear) A <= 0; else if (Enable) if (Load) A <= I; else if (UpDown) A <= A - 1; else A <= A + 1; end endmodule 25

26 BCD Up/Down Counter from Binary Up/Down Counter with Load Use binary counter with load to reset BCD to 0 or 9 based on up/down respectively Load value is set based on up/down 26

27 Counter with Unused States Counter with n flip-flops has at most 2 n states Unused states handled with X s may not move onto valid states if entered; determined after implementation Example: State table implements a gateless design with unused states 011 and 111, but they recover to known states J A = B K A = B J B = C K B = 1 J C = B' K C = 1 27

28 Ring Counter Uses circular shift register with only one flip-flop set at a time (one flip-flop per state) The 1 is shifted from one flip-flop to the next on each clock Reset signal asserts Set/Resets of flip-flops to create initial state Could also use a 2-bit counter which drives a 2-to-4 decoder to achieve a similar result Uses less flip-flops, but decoder size can dominate for large number of states 28

29 Ring Counter HDL Use concatenation and bit ranges to implement shift registers // Verilog-2001 module ringcounter #(parameter n=4) (output reg [n-1:0] T, input CK, Reset); CK, posedge Reset) begin if (Reset) begin T[n-1:1] <= 0; T[0] <= 1; end else begin T <= {T[n-2:0],T[n-1]}; end end endmodule 29

30 Johnson Counter Modified ring counter with complement of last flip-flop fed-back instead Generates 2n states from n flip-flops 2n AND 2-input gates required to decode state (Sx) Examine adjacent patterns only If in unpredictable state, it will not reset on its own Fix: D C = (A + C)B 30

31 Johnson Counter HDL Use generic model where n is the number of flip-flops; 2n outputs Calculate S with for loop Infers parallelism Use integer type for control variable Loop limit must be known at compile time Can t use i++ ; use i=i+1 // Verilog-2001 module johnsoncounter #(parameter n=4) (output [n*2-1:0] S, input CK, Reset); reg [n-1:0] T; integer i; CK, posedge Reset) if (Reset) T <= 0; else T <= {T[n-2:0],~T[n-1]}; begin S[0] = ~T[0] & ~T[n-1]; S[n] = T[0] & T[n-1]; for (i=0;i<n-1;i=i+1) begin S[i+1] = T[i] & ~T[i+1]; S[n+i+1] = ~T[i] & T[i+1]; end end endmodule 31