Clock Branch Shearing Flip Flop Based on Signal Feed Through Technique

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1 Clock Branch Shearing Flip Flop Based on Signal Feed Through Technique Pragati Gupta 1, Dr. Rajesh Mehra 2 M.E. Scholar 1, Associate Professor Department of Electronic and Communication Engineering NITTTR, Chandigarh ABSTRACT: Flip-flops are used to store state information in all types of controlling units of integrated circuits. The efficiency of synchronous circuits depends on the performance of flip-flop. To calculate the performance of flip-flop power and delay is the two most important factors. To reduce the power consumption and delay of flip -flop, signal feed through scheme is used in this paper. As in this scheme signal is directly driven the internal node of the latch, so the speed of the circuit is improved. In this paper the designing of explicit type pulse trigger flip-flop on CMOS 90nm technology is proposed. Double edge triggering is also used in this paper to improve power and delay. When compared to the existing design this paper gives improved delay, so the speed of the circuit is also improved. KEY WORDS: Flip-flop, Low power electronics, power dissipation and VLSI I. INTRODUCTION Flip-flop used as the basic storage element and a store State information. Flip-flop is digital electronic circuit to store a logical state of one input signal and more data input signals in comeback to a clock pulse. Periodic signals are used generally in the design which is used to produce sustained data and for a specified time period and also used to receive the data. Also used for the other circuits which process the data in another form. As technology is moving towards in reduction of the size of the device, the most important need is the need for low power, most of the part of circuit power is consumed by the clock distribution network. Another important thing is the speed of the circuit, if the supply voltage is reduced, then the speed of the circuit to produce the output is reduced because input voltage is decreased. The optimum value of supply voltage depends upon the threshold voltage of the network, and that threshold level is decided by the transistor either of NMOS or PMOS, that decide the optimum energy delay product. According to the Moore s law the number Of transistors that are to be integrated on a single die just doubled approximately for every 18 months and that proven that space of the design or can say the area is also an important concern. Due to the advancement in technology integration and low power for CMOS is the most important factor for advancement. The developments in the arena of CMOS expertise, have encouraged an unceasing growth in the concreteness of combination in the frequency of the VLSI ICs. As advancement occurs, leading towards lower power small scale area and high speed ICs. These challenging concerns are mainly due to the excessive switching activity. In VLSI system, clock system is the most power consuming element which consists a distribution network called clock and an element of timing are called flip-flop or latches [1-2]. It consist 35% to 65% of the system. As the power consumed by the timing element is reduced, then the total system power is also affected and reduced the overall power consumed by the system. In order to do the reduction in power most important factor is voltage scaling. It is helpful to reduce the consumed power. As power is proportional to the square of the voltage of the network. However, Threshold voltage is related to the voltage scaling, cause to change or increase in the leakage power. In addition supply voltage scaling, double edge triggering is used in comparison to the single edge to reduce half power of the network. The Power of the clocking system is equal to power of the clock distribution network plus the power of flipflop. Cutting the frequency of the clock by one half will halve the power consumption on the clock distribution network [2]. Different techniques are available to implement double edge triggering in flip-flop. In general terms, it is divided mainly in two categories. The first category is to connect or add extra circuitry to produce an internal pulse signal on each clock cycle. The second way is to identify the path to trigger the flip-flop to sample data on every clock pulse [3]. Double edge trigger flip-flop is able to generate the same output, at half of the frequency. The double edge trigger flip-flop gives lesser delay in comparison to single edge trigger flip-flop, so gives a benefit in terms of speed. So it is used in high speed applications. As this type of flip-flops numbers of ISSN: Page 123

2 transistors are reduced and help in reducing the power consumption of the network as well as delay. This design has also reduced the area as number of clocks transistors is reduced. The two CMOS transmission gates are realizing the multiplexer circuit, so this MUX structure is used in the design of CMOS double edge trigger flip-flop. Two inverters sections are used in feedback path that restore the output level of the latch. In this paper design of double edge trigger flip-flop is proposed that reduces the power consumed by the circuit as well as the delay in the circuit exists. Fig.2. General Scheme of ExplicitDEFF [1] Fig.1. General Scheme of dual edge flip flop[1] In vision that many of double-edge flip-flops (DEFF) are established from the single-edge designs (SE), A brief survey of single edge trigger topology are considered now. There is an extensive collection of flip-flops in the literature [4]. Many microprocessors are used master slave flip-flop or pulse triggered flipflop [5]. Conventional single edge trigger flip-flop use or can say made by master slave flip-flop used two stages one for master another one for slaves. Another type of single edge trigger flip-flop named sense amplifier based flip-flop called SAFF [6]. All these types of flip-flops are the hard edge type flipflops are generally characterized as or having large delays at the output and having positive set-up time. Instead, using this master -slave flip-flop pulse triggered flip-flops are used that reduce two stages into one and are characterized by the soft edge property. Pulse triggered flip-flops are classified into two categories: one is implicit pulse-triggered flipflops [7] and the explicit pulse-triggered flip-flops [8, 9]. Explicit type pulse trigger flip-flops (ep-ff) and implicit type pulse trigger flip-flops (IP-FF) both are having different features and properties. First type ep-ff in which the pulse-generator shared among neighboring flip-flops The sharing of pulse generator will help in power reduction as helps in distributing the power among many of the explicit type flip-flops. Pulse generators are being shared in the Itanium type processor. Secondly, explicit type flip-flop has better performance as in this case the height of NMOS transistor stack is less than the implicit type flip-flop. However, one limitation with explicit type flip-flop that these FF can not be used with dynamic logic. This paper is organized in the format as Section II D- flip-flop design with explicit scheme. Section III presents DEFF simulations, and Section IV presents result analysis and Section V concludes the paper. According to the survey the DEFF categorize into three groups: conventional type DEFF, explicit type pulse DEFF, and implicit type DEFF. For these three categories, analysis is done for data latching scheme and a clock pulse generating scheme.the requirement of the number of transistors is reduced in single edge trigger flip-flop in comparison to double edge trigger flip-flop, but the double edge trigger flip-flop design is better in terms of power required to clock load is less.. The DEFF Design should aim at saving energy both on the clock distribution networksand flipflops. It is desirable to diminishcircuit'sclock loads by decreasing the quantity of clocks transistors [1]. Besides, circuits with compact switching action would be desirable. As the voltage and power are related to each other, so to reduce in the power circuit operated at low swing means at low voltage.this specifies that flip-flops with smoothalteringcapability could be used in such conditions. So, The design, integration of level shifter is easy to design with flipflops [10]. ISSN: Page 124

3 II. EXPLICIT FLIP-FLOP In this brief a novel low-power Pulse trigger D flipflop design basedon a signal feed-through scheme is presented. All design used to previously have delay to latch the data in obtaining output. This delay discrepancy can overcome by using a signal feed through a scheme in which data feed directly to the internal node of the structure of the latch can helpful to reduce the delay [11]. To enable this mechanism pass transistors are used in the design. For signal driving Pulse generation circuit is combined with the pass transistor logic.this will helpful to enhanced speed and power-delay-product(pdp) performances.the working of latch and flip flops are similar,only difference is that clock pulses are used in case of flip-flop, as here in double edge trigger flipflop the output of the flip-flop is change on rising and falling edge of clockpin and delays it by oneclock cycle. So it is referred to as a Delay flip-flop. The Delay Flip-Flop can be interpreted as a delay line orzero order hold. One of the major advantages of D flip-flop from the d-type transparent latch is that when clock pulses are applied than the input pin is captured and changes in the output occur after next pulse, till that no change occur.d flip-flop is of two types edge triggered and level triggered,in edge triggered output changes on rising or falling edge of clock, But in the case of level-clocked, the output can change when the clock is high or low. In edge triggering the change in output occur on instant during the clock cycle. In case of level triggering output can change onan entire half cycle ofthe clock pulse. This operation is explained in figure 3. The basic structure or description of DFF and itstiming diagram responses are explained below [12]. Fig. 3 Timing diagram of D flip-flop The conventional type of Flip flop can say are the very basic design of Delay Flip-Flop. Latches which is used conventionally are called level-sensitive or level triggered because in thisoutput follows their inputs as long as they are enabled. Whenever enable signal is there, then latches are transparent. Another one already explained above is edge triggered in which output change on rising edge or falling edge of clock pulses. For enabling the signal clock pulses are used that is the controlling signal for the output. Thus, all changesare occurringin a synchronized way to the rising edge or falling edge of the clock pulses [13, 14]. A serious pair of latches is used in edge triggering. In master and slave laches when clk = 1 the slave latch is enabled, then output from the master latch is transferred to slave latch and in case when clk = 0 then the master latch is enabled and output follow the input.the slave latch is enabled, all the while that Clk =1, but its contentedalterations only at the beginning of the cycle, that is, only at the rising edge of the signal because onceclk is 1, the master latch is disabled and so the input to the slave latch will not change, As in explicit type P-FF pulse generator are separate from the design,but this design better in terms of delay But is talk about, implicit type P-FFs, they gives more power advantage. Nevertheless, the Longer discharging pathoccurs in these circuits, so that characteristics of them are low-grade [15, 16]. This type of logic separation provides better speed that occur from latch design FF. If the shearing of the pulse generator is used that is the input source, then the power consumption and complexity of the circuit can be exceptionally reduced. III. PROPOSED DESIGN SIMULATION In Explicit pulse triggered flip-flop, the external pulse is generated. In these types of flip-flops pulse generator logic is shared among its nearest flipflops.several of the methods like explicit pulse data close- to- output called EP-DCO, static conditional flip-flop called S-CDFF are deliberated in this brief. This division can aid in allocating the power of the pulse generator across several Explicit pulses triggered flip-flop. In terms of energy efficiency explicit pulse trigger flip-flop are better in comparison to implicit pulse trigger flip-flop.double- Edge Triggering (DET) has been realized in the explicit pulse triggered flip-flops, but it is hard to organize in implicit pulse triggered flip-flop.the datais latched or sampling is issued at both raising and falling edges of Double edge triggering. DET used to save energy both in clock distribution network and also in flip flops. Double edge trigger circuit reduces the frequency to half, but still gives same throughput[8]. Firstly the pulse generator circuit is implemented to generate pulse at both rising and falling edges of ISSN: Page 125

4 clock. The circuit consists 5 inverter circuits and 2 NMOS transistors, So total 12 transistors are used in this circuitry, The whole simulation is done on Cadence tool. Specifications for the input supply are Period 80 NS, delay 0s, rise time 20ps, full time 20ps and pulse width is 40 NS. By using these parametercircuits is simulated on selected W/L ratio. is used with pulse width specification of 120 ps. The sizing of transistors also considered that the pulse generators can workproperly in all process respects. When considering the latchstructures, each pulse triggered flip-flop is optimized to obtain suitable performances. Input signals are generated with the help of buffer to maintain the performance. As this design use signal fed through technique so input signal feed directly to the latch so direct output driving is employed. 20 ff capacitor is used here at the output with an extra loading capacitance of 3 ff which is placed at the output side of buffer. The simulation is done at 1.0 V and frequency of the operation is 500MHz to obtain deterministic pattern. Fig.4 Double edge trigger pulse generator The output waveform for the given double edge trigger pulse generator circuit are shown below in figure no. 2, shows that output pulse are obtained at both rising and falling edges of the clock pulse and frequency are taking from this is 500MHz at 1 V supply. This double edge trigger pulse generator circuit is used as input to the flip-flop circuitry and share among many of flip-flop. In fact, the dual-edge triggered flip-flop involves lower clock frequency than the single-edge triggered flip-flop and to accomplish analogous performance. At the half of clock frequency the dual edge triggered flip flop gives the same data output of single edge-trigger flipflop gives, So the proposed design gives power economical circuit. Fig.6 Schematic of proposed flip-flop Fig.7 Layout of proposed flip-flop Fig. 5 Double Edge Pulse Generator Transient Response The technology used in this paper is the 90-NM CMOS process. Main cruible factor in the designing is the width of pulses which are responsible for capturing the data controlling the power consumed by the network [10,13], as here separate pulse generator The proposed design have not low count in terms of transistors, but the layout occupies the small area which shown in the layout design. As a signal feed through technique used here that reduces the transistor sizing and helps in reducing the discharging path. ISSN: Page 126

5 IV. RESULT ANALYSIS Table 1 displays the parameters that decide the performance of double edge trigger explicit type flipflop. This table determines how much power and delay is required for the circuit. Table 1: Parameters Table Parameters Design [6] Proposed Design Power 13.0 µw 4.72 µw Technology 180nm 90nm No. of Transistors Delay 179 ps 68.7ps Optimal PDP 2.33fJ 0.325fJ Fig.8 Transfer curve of proposed flip-flop Transfer characteristics are plotted by setting input pulses. Firstly is rising and falling edges are decided at 20ps and delay at 0. Pulse width selected according to the input voltage and sources of input, it also depends on circuit specification. So the pulse width is 80 ns and period is 40 ns. DC characteristics are shown on the design which is necessary for the power calculation Power (uw) Delay (ps) Fig. 9 DC Characteristics of Proposed flip-flop Meanwhile the proposed design which adopts signal feed-through technique requires driving the input signal or data at the internal node to feed directly at the output node of the structure. Fig. 10 Comparison Chart of power The table shows the comparison of proposed design result with the design [6]. Both the design are double edge triggered flip-flop. Power and delay factor are examined by setting pulse width factors like rise time, fall time and period of the pulse. In this brief, the set-up time is measured as the optimal timing (with respect to the clock edge) of applying input data to minimize the production of power and D-to-Q delay. Power calculated of the proposed design is µw and delay occur in the Pico second range. As the value of delay in the Pico second range, so the Dto Q delay is reduced in this proposed design from the existing design. In other words, its choice is based on the optimization of PDP from D to Q instead of the D-to-Q delay alone. The proposed design gives ISSN: Page 127

6 63.69 % reduction in power and 61.6% reduction in delay. V. CONCLUSION In this paper, double edge trigger flip-flop is designed, which is classified into three categories first is conventional flip flop design in which latching component is duplicated, second implicit type and last is explicit type double edge trigger flipflop design. The proposed design of this paper is explicit type pulse trigger flip-flop,which is used to save power and delay of the circuit. In proposing explicit type flip-flop design requires more transistors from implicit type pulse trigger flip flop, but it gives power of µw and delay of 68.77ps. As in this design D-Q delay is reduced to 61.6% of the existing design,so the speed of the circuit is improved. Hence this design is suitable in high performance,high speed environment. REFERENCES [1] B. Kong, S. Kim, and Y. Jun, Conditional-capture flip-flop for statistical power reduction, IEEE J. Solid-state Circuits, vol. 36, no. 8, pp , Aug [2] N. Weste and D. Harris, CMOS VLSI Design. Reading, MA: Addison Wesley, [3] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, 2nd Ed. Englewood Cliffs, NJ: Prentice- Hall, [4] Vandana Choudhary, Rajesh Mehra, 2- Bit Comparator Using Different Logic Style of Full Adder, International Journal of Soft Computing and Engineering, Vol.3, pp , May [5] P. Zhao, T. Darwish, and M. Bayoumi, High-performance and low powerconditional discharge flip-flop, IEEE Trans. Very Large ScaleIntegration (VLSI) Sysemt, vol. 12, no. 5, pp , May [6] Peiyi Zhao, Jason McNeely, IEEE, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, and Weidong Kuang, Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 15, No. 3, pp , March [7] B. Nikolic, V. G. Oklobzija, V. Stojanovic, W. Jia, J. K. Chiu, and M. M. Leung, Improved sense-amplifier-based flip-flop: Design and measurements, IEEE J. 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Papaef thymiou, Resonant-Clock Latch-Based Design, IEEE Journal Of Solid-State Circuits, Vol. 43, No. 4, pp , April [14] Peiyi Zhao, Tarek K. Darwish, And Magdy A. Bayoumi, High-Performance And Low-Power Conditional Discharge Flip-Flop IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Vol. 12, No. 5, pp , May [15] Akhilesh Verma, Rajesh Mehra, Design and Analysis of conventional and Ratioed CMOS Logic, IOSR Journal of VLSI and Signal Processing,Vol. 2,Issue 2, pp ,2013. [16] Upwinder Kaur, Rajesh Mehra, Low Power CMOS Counter using Clock GatedFlip-flop, International Journal of Engineering and Advanced Technology,Vol. 2, Issue 4,2013. [17] Xiaowen Wang, And William H. Robinson, A Low-Power Double Edge-Triggered Flip-Flop with Transmission Gates and Clock Gating, IEEE International Midwest symposium on circuits and systems, pp , August AUTHORS Pragati Gupta received the Bachelors of Technology degree in Electronics and Communication Engineering from Moradabad Institute of Technology, UPTU, Moradabad, India in 2010, and she is pursuing Masters of Engineering degree in Electronics and Communication Engineering from National Institute of Technical Teachers Training & Research, Panjab University, Chandigarh, India. She is an Assistant Professor with the Department of Electronics & Communication Engineering, Moradabad Institute of Technology, Moradabad, India. Her current research and teaching interests are in Digital electronics and VLSI. Dr. Rajesh Mehra: Dr. Mehra is currently associated with Electronics and Communication Engineering Department of National Institute of Technical Teachers Training & Research, Chandigarh, India since He has earned his Doctor of Philosophy in Engineering & Technology and Master of Engineering from Panjab University, Chandigarh, India. He has completed his Bachelor of Technology from NIT, Jalandhar, India. Dr. Mehra has 20 years of academic and research experience. He has more than 350 papers to his credit, which are published in refereed International Journals and Conferences. Dr. Mehra has guided 80 ME thesis and he is also guiding 02 PhD scholars. He has also authored one book on PLC & SCADA and developed 06 video films in VLSI area. His Research areas are Advanced Digital Signal Processing, VLSI Design, FPGA System Design, Embedded System Design, and Wireless & Mobile Communication. Dr. Mehra is member of IEEE and ISTE. ISSN: Page 128