Adaptive Testing Cost Reduction through Test Pattern Sampling

Transcription

1 Adaptive Testing Cost Reduction through Test Pattern Sampling Matt Grady, Bradley Pepper, Joshua Patch, Michael Degregorio, Phil Nigh IBM Microelectronics, Essex Junction, VT, USA Abstract In this paper, we will present two different applications of test pattern sampling for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test. 1. Introduction It is well known in the IC industry that most defective devices can be made to fail with many fewer tests than are typically applied [1-4]. The difficulty is how to determine the optimal pattern as early as possible during production testing. There has been a growing emphasis on increasing test coverage to improve shipped quality levels significantly driving up the number of required test patterns for logic testing for SOCs and processors (e.g., higher fault coverage targets additional fault models with as Small Delay Defect & Cell-Aware and other algorithms such as RAM Sequential. To ensure that the test time (cost does not significantly increase, new methods should be developed which provide the shipped product quality level advantages of these emerging methods while not significantly increasing test costs. IBM and other companies have found that many structural test patterns for logic circuits do not uniquely detect production failures [1-4]. For example, IBM has historically found that 70%--90% of the logic test patterns could be removed for ASICs without any impact to test escapes shipped to customers [1]. However, the data required to determine the optimal pattern set is available only after production testing is complete. The current method for performing this test optimization is through production test pattern fallout analysis after a large sample of parts have been tested. Then the ineffective patterns are permanently removed from the production pattern suite. Our analysis shows that pattern sampling can provide nearly the same test time improvements and provide better shipped product quality levels and reducethe risk since these methods can adapt to changes over time in the failure profile (e.g., due to process line variability or changes in failure modes. During product testing, patterns will be applied at multiple test conditions: multiple temperatures, voltages, timings, and socket insertions. Each of these conditions do detect unique failures but clearly applying all patterns at all conditions is overkill. One common method to reduce pattern application test time is to only apply a subset of patterns at each condition. However, there isn t an efficient method for determining the optimal subset of test patterns to apply at various conditions ahead of time. There have been other implementations of using test sampling for test time reduction (TTR [5-9]. However, the published examples of sampling are based on various types of tests (such as analog tests not based on test pattern sampling at a granular level. The techniques proposed in this paper are consistent with emerging methods described in the Adaptive Test subsection of the International Technology Roadmap for Semiconductors (ITRS [12]. Over the next few years, it is expected that methods such as these will become commonplace in the industry. In this paper, we will describe two methods for optimization of test patterns for volume production products. These two implementations have different motivations and were implemented in completely different ways but each provides a significant reduction in test times (30%-50% for the pattern portion of production testing. 2. Wafer-level Pattern Sampling for High- Volume Processor In this section, we will describe a generic functional test template that collects statistics about failing functional patterns and adaptively determines the optimal pattern set to apply at wafer probe testing. This method has resulted in 40%-50% test time reduction of individual functional test methods with low escape rates (0.01%-0.03% of failures from wafer test to final test for a high-volume processor -- and without any adverse affect to customer DPM levels.

2 2.1 Definitions We will use the following terms: Pattern: a functional test contained in some file format for some target test equipment. The functional test can be of any type (stored pattern logic test, logic built-in self test, an architectural verification pattern, etc.. Many examples of a test can be 'squeezed into' one pattern. For example, a stored pattern logic test pattern might have 10s or 100s of scan load, functional clock, scan unload sequences. Functional Template: a generic software method for running a list of patterns at some condition (voltage /timing, etc. and obtaining a pass/fail result Baselining: running all the patterns in a functional test template for a sample of parts to collect pass/fail statistics Sampling: running an 'effective' subset of patterns in a functional template based on the previous statistics collected 2.2 Basic Algorithm We begin the pattern sampling operation with the process of baselining, where we run all the patterns in the functional template and score failing patterns based on their effectiveness of uniquely identifying defective die. For example, if a pattern fails on a bad die and it is the only pattern that fails on that die, then that pattern gets a high score for that specific die. Conversely, if a pattern fails and is one of many patterns that fail on that die, then that pattern gets a lower score for that die. After baselining, we perform test pattern sampling where we run a fraction of the patterns that were selected based on scoring (naturally, the highest scoring patterns. We also keep running all the patterns on some fraction of the tested chips, so that the pattern score statistics can continue to be updated. This updating can be thought of as a continuation of baselining. All of the quantifiable terms described above are parameterized, specifically: The number of devices to be used for baselining The fraction of patterns to run on the sample die The percentage of devices to bypass sampling (run in non-sample mode after baselining The duration at which sample statistics should be reset and baseline repeated (e.g., end of a lot, or end of a time period, etc. There are other more complicated algorithms [5-6], but our proposed pattern scoring method has the following advantages. minimal data structures minimal parameter specifications negligible compute time no need to interact with other tools or databases (stands alone within the test cell Details of Scoring Patterns We define the 'score' of an individual failing pattern on a specific die as follows. Given: P = total patterns in template F = failing patterns in burst on this bad die S = score for this pattern on this die then S = (P+1 - F For example, if P=10, and a pattern fails on a die, and it is the only failing pattern, then the score for that pattern on that die is '10'. However, if a failing pattern is one of five failing patterns on a bad die, then that pattern (and the other failing patterns all score a '6'. In this way every pattern gets a score between 0 (did not fail and 10 on any given bad die. We keep a running average of the pattern score based on the following: n = failing die count A (i = running average score for this pattern through i failing die then A (n = [A (n-1 *(n-1 + S] / n We need only keep track of n for the functional template and A (n for each pattern to maintain a complete record. Figure 1 shows two examples of pattern scoring. In the example shown in Fig. 1a, we have 10 patterns each with a probability of fail of 0.5. On average, any given die will have half of the patterns failing, so each pattern will score '6' on average when it fails. The other half of the time, the pattern won't fail and will score '0'. Therefore, the average score for any pattern in this scenario is '3'. score score chip count (a chip count (b Figure 1. Two examples of Pattern Scoring. (a Probability of fail is 0.1 for all patterns (b Prob. of fail for 1 pattern increases after 130 die

3 Figure 1b shows a more interesting example where a pattern starts off with a probability of fail of 0.1, then changes (for whatever reason to be much more likely to uniquely fail (a probability of 0.9. Assume the other 9 patterns have a constant probability of failure of 0.1. Fig. 1b shows the scoring trend for this pattern given the onset of the change from 0.1->0.9 occurring after 130 failing devices. The result is that the score for the pattern of interest begins to climb (and consequently, the scores for the other nine patterns begin to decline, as there will be an increased occurrence of one more pattern failing from the newly 'rogue' pattern. Escapes Whenever a subset of patterns is run, the probability of escape will be non-zero. A key to escape rate is how many patterns tend to fail on a given bad die. many logic tests, most bad die fails many 2 shows an example from a logic test patterns on a high volume microprocessor 65nm process at IBM. Fortunately, for patterns. Figure mode with 20 manufactured in In particular, we are interested in escapes (P(x=0. If we sample 10 of 20 patterns, the probability of a test escape is (for all values of M=1 to 20: P(X=0 = h(0,10,m,20 Figure 3 shows the probability of a test escape for M<=10. Figure 3. P(escape for M<=10. If one samples 10 of 20 patterns, the probability of escape is very low until one comes across chips that fail 5 or fewer patterns. However, the number of such devices is generally very small. Also, as we are scoring patterns, we will have a higher likelihood of actually running a pattern that will fail such a chip since patterns that uniquely fail are given higher scores. Figure 2. Production Test Results Prob. of fail for 20 test patterns Fig. 2 shows that about 50% of failing chips fail 19 or 20 out of 20 patterns. This result is expected since each test pattern is actually doing many tests and most defects are relatively easily detected. Another key feature that will determinee escapes is the percentage of patterns to apply during pattern sampling. If we choose, for example, to run 10 of 20 patterns when sampling, then chips that fail 11 patterns or more are guaranteed to fail. However, all of the types of chips that fail 10 or fewer patterns will have some probability of escape as given by the hyper geometric distribution: M N M = = = x n x P ( X x h( x, n, M, N N n Where: x = number of times the patterns we are sampling intersect the patterns the chip fails n = number of patterns sampled M = number of patterns a specificc chip fails N = total number of available patterns Figure 4. Sampling Behavior during Production Test (after sampling starts, only a subset of the patterns are applied on 80% of the devices Pattern Sampling in Practice A typical parameterized setup follows these steps: 1. Fully test (no sampling enough failing chips to cover all bad die on one wafer 2. From then on, run half the patterns in the set (pattern sampling 3. Every 5 th chip, run all the pattern to continue to collect full statistics 4. Restart the algorithm at the beginning of each wafer lot

4 Figure 4 shows sampling behavior for one testmode in a typical wafer lot. The X-axis is the chip count and the Y- axis is either 0 (not sampling patterns or 1 (sampling / running a subset of patterns. For the first wafer and part of the second, pattern sampling is not used. In the early part of Wafer2 testing, pattern sampling is turned on and then the full pattern set is applied only on 20% of the die. 287ppm. Note that this escape rate is between wafer test and module Final Test only there were no test escapes to the customer. Lot#1 Initial Test (without sampling Chips 3332 Sampling 3453 Final Test Yield 98.7% 98.8% Lot#2 Initial Test (without sampling Chips 3379 Sampling 3524 Final Test Yield 98.8% 98.7% Figure 5. Pattern sampling makeup during test of a wafer lot Figure 5 displays an example of how the pattern makeup is dynamically changed by using pattern sampling data for an example wafer lot. Again, the X-axis is the tested chip count and the Y-axis is the sampling / not sampling state (1=sampling. The color legend is the pattern list state. At the start, all of the patterns (p0, p1, p2, etc. are being run. After ~300 chips, the patterns will have a sufficient number of samples and will be reordered based on the pattern scores. One can see that the order of patterns changes several times as test of the lot progresses. Experimental Results To evaluate pattern sampling in practice, two 25-wafer lots were chosen for evaluation. In each lot, half of the wafers were tested to the original process of record (no pattern sampling, and the other half of the wafer were tested with sampling. The pattern sampling consisted of running half the patterns on 80% of the chips after ~1 wafer of baseline data collection. Package test was done on all the good units from wafer test with no omission of any patterns. Module yields of the split samples were compared. In addition, all failing modules were analyzed to discover whether or not they had escaped from wafer to package test due to pattern sampling. The yields at module Final Test for this evaluation are shown in Table 1. Module yields for the lots were indistinguishable whether pattern sampling was used or not. All of the fails were then analyzed, and it was found that two of the modules were chips that failed exactly one pattern from the logic testmode sampled, and in both cases that single pattern was not run at the time the die was wafer tested. The escape rate for the sampled material was therefore Table 1. Final Test Yield for 2 wafer lots with and without pattern sampling The typical usage for this method in IBM is to reduce wafer test time (at the cost of producing a few modules that will fail the full pattern list during package test. Depending on the cost of the materials and labor for producing a failing package, the wafer test cost reduction is usually 10X-15X 15X larger than the failing package cost, so the use of test pattern sampling is easily justified. 3. Test Sampling of Scan-based Transition Patterns at Final Test for SOCs/ASICs The motivation for implementing test pattern sampling for SOCs/ASICs is to optimize the number of scan-based test patterns applied at Final Test. This method relies on a combination of on-going statistical analysis of historical data and real-time updates based on applying the full pattern suite for a sample of devices. This method has reduced pattern application duration by 28%-39% with further opportunities for test time reduction with no significant negative impact to shipped quality levels. 3.1 Pattern description and background data The initial application of this method targets test patterns that have been found to never fail for a large sample of parts. Historically, the industry practice is to statically remove these patterns after a large sample of parts have been tested. In our method, the ineffective patterns are still applied on a sample basis in production and if these patterns are later found to be effective they are added back into the regular production test suite. Before this method was applied, IBM applied the full suite of transition delay test patterns both at low VDD and high VDD. The failing pattern data can only resolve the failure to one of 32 ATPG test patterns (where each test pattern is a scan load, functional clocks, and scan unload. The patterns are grouped in this way because the output MISRs are only checked once every 32 test patterns. In spite of this grouping, the pattern sampling method is still effective (but clearly additional test time could be saved if the test buffer granularity was finer.

5 Figures 6-9 show fallout data for thesee patterns for a sample of about 1 million devices for a typical ASIC. For each failing device, the first test buffer is recorded. (A test buffer consists of 32 ATPG test patterns. Note that all buffers were applied first at Low VDD voltage, then at High VDD voltage. Figure 8.. Number of Failures / Test Buffer for example ASIC with 1M total die samples. (buffers with only a small number of failing devices is difficult to see at this resolution Figure 6. Cumulative Fallout for an example production ASIC Figure 9.. Number of Failures / Test Buffer for example ASIC with 1M total die sample (This is the same data as Fig. 8 with an expanded section showing High VDD failures. Figure 7. Cumulative Fallout (This is the same data as Fig. 6 with an expanded resolution at the Low-High VDD crossover range. Fig. 6 shows the cumulative fallout of the first failing test buffers for these 1M devices. For this example, 226 buffers were applied both at High VDD and Low VDD voltage. Note that over 90% of the failing devices fail within the first 10% of the buffers then there is a long tail where additional patterns pick up a small number of failures. Fig. 7 shows the same data as Fig. 6 with an expanded region shown between the crossover between Low VDD and High VDD pattern application. Figures 8 and 9 show the number of failures first detected by each test buffer. These figures show the same characteristic; the first set of buffers detect the vast majority of failures then later buffers detect only a small number of failures (or zero failures. Figure 9 shows an expanded view of the buffer fallout for the High VDD application of tests. Note that most buffers did not show up at all in the first failing buffer list these buffers could have been removed without any impact on shipped product quality levels (customer DPM. Note that we re only collecting the first failing buffer for each failing device. It is not be practical in high-volume production test to continue to apply all buffers after the first failure is detected and to collect all failing buffer data. Although it is possible that the pattern analysis could be made more comprehensive by collecting fail data for all buffers even after the first failure, we do not believe this this is a significant limitation in our pattern sampling process. Observe the following from this data: The vast majority of failures are in the first few buffers. (90% of fails in first 10% of patterns Many test buffers never uniquely detected a failure for the 1M devices (i.e., they could be removed with no impact to shipped product quality levels e.g., 73% of the buffers applied at High VDD do not uniquely detect any devices another 19% of the buffers was a first failure for only 1 device The vast majority of failures occur at the first voltage applied (low VDD in this example Only 0.4% of the failures passed at Low VDD and failed at High VDD

6 As previously mentioned, this data has been analyzed for many products in the past and the results have been consistent across a number of technology nodes and ASIC designs [1]. This type of data provides the motivation for pattern sampling. 3.2 Production Implementation of Pattern Sampling This method has four steps: 1. Apply 100% of test buffers in production. 2. After baseline criteria of production parts is met, turn on buffer sampling. Sample buffer list is calculated based on analysis of full production history. Sample rate is derived based on baseline sample size and DPM target. 3. During production test with pattern sampling, if a sampled pattern is the first failing buffer remove this pattern from the sample buffer list. Apply the newly failing buffer for 100% of the devices from that point on. Note that this analysis and pattern update is done in real-time within the test cell. systematic failures that are wafer/lot dependent. This is a key benefit over static optimization where the patterns are permanently removed. Due to only sampling these patterns, there is a chance defective devices could be missed this is discussed in a later section. (The exposure is minimal as long as baseline population and sample rate are properly determined. Note that this process can be changed to include buffers in the sample buffer list that have been found to be the first failure for 1 device (or a small number of devices. However, the rate of test escapes must be calculated and been determined to be acceptable. For our initial implementation, we have been conservative and only included buffers in our Sample buffer list that never occurred in our first failing buffer analysis. Calculation of Test Sample Rate & Baseline Sample To implement pattern sampling, we must determine the baseline sample size and the sample rate (the rate at which to apply the full pattern suite once pattern sampling is turned on. We have developed a model for determining the escape rate using pattern sampling for a given baseline population and sample rate. For example, Figure 10 shows the probably of exceeding 50dpm of test escapes for a range of baseline population and two different sample rates (10% & 30%. 4. On a regular basis (e.g., daily: Update the Sample buffer list and the sample rate based on full production history of fail data and propagate across all test floors and testers. Note that this method is not applied until a significant number of parts have been tested to establish a baseline. (e.g., 50, ,000 devices Then two types of patterns are identified: 1. Production Test Suite which were identified to find failures (e.g., fails in Figs Sample buffer list which have not been found to uniquely detect failures The Sample buffer list is subsequently only applied on a sample basis (e.g., 10% in production. (The Production Test Suite is applied on 100% of the production devices. Note that the test program determines on-the-fly if a device sees both pattern sets or only the Production Test Suite. If a device only fails one of the Sample buffers, then from that point on that pattern is moved from the Sample buffer list to the Production Test Suite. The sample rate is derived using an algorithm based on inputs such as baseline sample size, production sample size, recent buffer fail results and target DPM requirements (or a fixed sample rate, e.g., 10%, can be selected. Note that this method will be able to dynamically adjust the test suite if patterns which previously have never failed start to uniquely detect new failure mechanisms (e.g., Figure 10. The probability of exceeding 50dpm of escapes vs. baseline population and two example sample rates. Note that if the initial baseline population is larger, then we have more data to derive the Sample buffer list and therefore it is less likely to have test escapes. However, using a larger baseline population reduces the test time reduction opportunity also. We can also reduce the probability of test escapes by using a larger sample rate once pattern sampling is turned on. However, a larger sample rate also reduces the test time savings. For a given ASIC, we calculate the baseline population and the sample rate given a maximum test escape rate. After implementing pattern sampling, we can recalculate the optimal sample rate and adjust production testing.

7 Correlation of failing buffers at Low/High VDD We have evaluated the correlation of first failing buffers between two test conditions: Low & High VDD voltages. We evaluated if a buffer is effective at Low VDD is this same buffer also effective at High VDD? Figure 11. Buffer failure rate comparison between Low & High VDD Figure 11 shows the buffer failure rate comparison between low & high VDD for an example ASIC. Note that there is significant correlation in failing buffers between these two VDD voltages. We have taken advantage of this correlation by removing some buffers from the sample buffer list which we believe are likely to be a first failing buffer in the future even if we have not seen a failure for that buffer up to now. In this way, we are guessing that this buffer may be likely to uniquely fail in the future. 3.2 Production Test Results & Escape Rate Estimation This method has been successfully used on more than 10 65nm & 45nm SOC/ASIC devices in production. (with many more planned It has reduced the test time of the delay test portion of testing by 28%-39% for each of these products. (Note that the delay test portion of test time is the largest and growing as chips have more circuits. Table 2 shows the test time reduction (TTR for the pattern portion of testing for these 10 ASICs. Number of ASIC Logic Circuits A 11.1M B 35.6M C 34.2M D 13.8M E 23.9M F 26.0M G 13.8M H 24.7M I 45.0M J 73.6M % Pattern TTR 36% 32% 33% 35% 39% 34% 34% 39% 33% 28% Table 2. Test Time Reduction for a sample of 10 ASICs Figure 12.. Escape rate calculation vs. baseline sample size (using actual fallout results for example ASIC We found that out of the 600K parts tested with pattern sampling, only 11 of the sampled buffers were found to fail and had to be removed from the sampled list. Also, we have calculated that the DPM increase due to pattern sampling is <<5% of the normal DPM. (Note that it is difficult to translate the failures at production test to what would fail in the customer s application. We believe this estimate is very conservative. Figure 12 shows a graph of the maximum escape rate for an example ASIC. One would expect in general that escape rate would gradually be lower if the baseline sample size is larger but for a specific set of data some variation may be observed (as shown in Fig. 12. This analysis was done using fallout data from 1M devices where e we retroactively simulated various what if scenarios. Using this example fallout data, our calculations suggest that pattern sampling provides ~40% DPM improvement over static pattern analysis & removal (i.e., the historic method. Safeguards For the initial implementation of pattern sampling for ASICs, a number of safeguards were added to the process. Note that a feed-forward forward data flow is required in this implementation where production testing requires that the sample buffer list and test sampling parameters be available at the start of testing for each lot. If the pattern sampling data is missing for some reason, then sampling is turned off for that lot. There is also an option to completely turn off pattern sampling if a sampled buffer is found to fail. If the test patterns change at all, then the pattern sampling algorithm is disabled until a sufficient baseline is established again. Also, all customer returns are tested with 100% of the pattern set and if a sampled buffer unique fails, then this buffer is removed from the Sample buffer list (but we have never found this to occur up to now.

8 4. Comparison of the two Methods This paper described two different implementations of pattern sampling. In the first case, the motivation for pattern sampling was only to optimize the trade-off between wafer test cost and the cost of building defective parts that would be rejected at final test. This is a relatively low risk application if the sampling method was wrong, the only negative result would be more parts would be rejected at final test that could have been detected at wafer probe testing. In the 2 nd implementation, there is risk of shipping defective parts to the customer if pattern sampling is done incorrectly. For our initial implementation, this risk was reduced by only focusing on one of the two VDD voltages so 100% of the patterns are always applied at Low VDD. 5. Discussion of the risk of using test pattern sampling Note that it may appear to be risky to only apply test patterns to a sample of devices instead of applying all of the patterns to all of the devices. Some types of devices (such as automotive ICs have a 0 DPM requirement and may not be able to accept any risk of more test escapes. However, we believe that test pattern sampling has application for all types of devices, but the implementation would be different. For example, products requiring very low DPM levels may instead generate additional test patterns beyond what is normally applied (e.g., using alternative fault models such as N-detect, bridging, etc.. Then pattern sampling determines which of the additional test patterns are used during volume production testing. 6. Planned Extensions There are a number of improvements that are being evaluated and implemented, including: Demonstrate capability to sample test patterns for all test conditions (e.g., implement sampling for all VDDs not just High VDD Evaluate other methods for the calculation of buffer sample rate & baseline population Predictive methods for defining which patterns/buffers should be sampled More granularity in determining the passing/failing test patterns (may require new design-for-test and test pattern format options Optimization across multiple pattern types & fault models Application for other test steps such as burn-in, card/board-level testing and system test The implementations described in this paper were initially done mostly within the test program. Another approach is to use real-time analysis software (outside of the test program to reduce the programming effort for subsequent products. (note that the overhead to perform the pattern sampling methods for these two examples is virtually nil 7. Summary In this paper we presented two methods for test pattern sampling that have significantly improved test time (test cost for high-volume products. These test time reductions have enabled IBM to avoid the capital cost of buying 10s of additional testers. We have proposed algorithms and metrics for test pattern scoring, sample rate calculations and using fallout data from one condition to guess which patterns may fail at other test conditions. These test pattern sampling methods use a number of techniques that are emerging in the industry such as data feed-forward, real-time (in-situ data analysis and optimization, and data feed-back (to optimize the test suite for future devices. For future products, these types of techniques will have broader application for test time reduction, yield optimization and quality improvements [12]. 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