Analog Performance-based Self-Test Approaches for Mixed-Signal Circuits

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1 Analog Performance-based Self-Test Approaches for Mixed-Signal Circuits Tutorial, September 1, 2015 Byoungho Kim, Ph.D. Division of Electrical Engineering Hanyang University

2 Outline State of the Art for Mixed-Signal System Difficulties of Analog and Mixed-Signal Test Conventional Analog and Mixed-Signal Test Call for New Solution for Mixed-Signal Test Category for Test Methodology Typical Platforms for Self-Test Scheme 2

3 State of the Art for Mixed-Signal System Mixed-signal System-on-a-Chip SoC, SiP, SoP of multi-function chip Big-Digital and Small-Analog configuration Small-A : more essential for overall SoC performance Majority of the production test time incurred in testing and its importance Large number of tests for analog circuit specifications Test cost approaching a half of the total manufacturing cost [Akbay et al.] Future ICs employing more mixed-signal circuits Processor DSP core Base-band Interface Logic Memory Controller RAM / ROM / Flash Ethernet Mac Mixed- Signal Circuits PHY System-on-Chip RF 3

4 Difficulties of Analog and Mixed-Signal Test Needs to deal with continuity of analog signal characteristics Tolerance is acceptable for results Analog specification for fault-free within tolerance margin Noise and tolerance specifications of signal generator It is difficult to generate ideal input waveform Affect response of the DUT Low test coverage Device Under Test (DUT) Automatic Test Equipment (ATE) Signal Generator (Tolerance of Spec.) Imprecise Input Analog Digital Imprecise Output Test Limit Meas. Data Compare (Pass/Fail) Binning Imprecise Response 4

5 Conventional Analog and Mixed-Signal Test Limitations of SoC testing Issues on conventional test Limited controllability and observability Traditional systems have test nodes to individually verify operation of subsystems Modern analog circuits integrated as die of core in SoCs External ATE without direct access to all internal embedded functions of mixed-signal system Expensive and highly time-consuming Different test setups for different performance parameters Overhead for instruments for each specification test Specialized instruments for full specification test External analog ATE is very expensive 5

6 Call for New Solution for Mixed-Signal Test Need for testable SoC/SoP Conflict of interests Integration afforded by design process Testability achievable by external tester Viable solution Placing ATE functionalities in close proximity of SoC module to be tested Improvement of test-access speed Reduction of test signal degradation by cable parasitic Increase of controllability and observability of signals Analog Built-In Self-Test (BIST) and Analog Built-Off Self-Test (BOST) Tests using much less expensive ATE Test functions on load board or DUT 6

7 BIST and BOST Scheme BIST scheme Moves part of required test resources from ATE to die Test stimuli generation, response evaluation, test control circuitry More controllability and observability BOST scheme Migrates test functions to load board Additional Design-for-Test (DfT) circuitry on load board for high-speed stimulus and capturing Benefits Low area overhead Low design effort/cost Low interference to original design Easy to characterize DfT device BOST Configuration Load Board DSP sin(wt) DfT circuitry Original Design DUT 7

BIST and BOST Scheme Incorporation of additional functions within chip

diversity of problem Required by broad range of different test

different conditions of package under test Interference to original

8 BIST and BOST Scheme Incorporation of additional functions within chip by reusing components E.g., DAC, ADC, and more Careful decision between BIST and BOST to master diversity of problem Required by broad range of different test requirements of mixed-signal circuit BIST and BOST architectures for different conditions of package under test Interference to original design Large area overhead Calibration required Characterization required Conventional testing BIST Need for -Low Cost -More Testability BOST Need for -More Controllability -Test Performance Trade-Off 8

9 Category for Test Methodology Configuration category: BIST/BOST Fault-based test Higher technology of digital self-test applied to analog self-test Realistic faults from process information, defect statistics, circuit layout Reference fault model Diverse waveforms generated on-chip and DUT response compressed to signatures Test method for faulty/fault-free DUT using signature 9

Category for Test Methodology (cont ) Limitations DUT topology and reference fault models required Hard to build the reference model of complicated circuits Poorly described model leads to lower test

10 Category for Test Methodology (cont ) Limitations DUT topology and reference fault models required Hard to build the reference model of complicated circuits Poorly described model leads to lower test accuracy With precise model and high fault coverage, stimuli targeted at detecting specific faults requiring more stimuli Detecting catastrophic faults effectively Difficult to effectively detect parametric failures With various input signals and diverse responses, analyzing DUT response for parametric failure is time consuming 10

11 Category for Test Methodology (cont ) Performance-based test Overcome limitations of fault-based test Apply optimized stimuli and measure functional specifications, without need for reference model Improved by BIST and BOST using stimulus generation and response analysis on DSP core available in SoC Trend for mixed-signal testing To develop cost-effective performance-based test methodology based on BIST/BOST, without loss of test quality 11

12 Typical Platforms for Self-Test Scheme Mixed Analog-Digital BIST [Toner, Haurie, Viyam, Zimmermann] Assumes mixed-signal IC with an ADC-architecture, including signal generator which produces analog test signal, e.g., DAC Tests systematically multiple analog module in IC one by one Issue - amount of hardware resources and complexity for test Oscillation-BIST [Arabi, Novak] Mixed-signal device is part of oscillating feed back loop and DUT is converted into oscillator in test mode Compare oscillation response, e.g., amplitude, frequency for pass/fail Simple and robust test, eliminating test vector generation problem Issue: hard to test parametric faults 12

13 Typical Platforms for Self-Test Scheme (cont ) Polynomial-BIST [Sunter, Huaguo, Rosinger] Measures specifications without changes of hardware in DUT Uses ramp or sinusoidal input and DUT approximated by polynomials Predict performance parameters using known parameters Need highly accurate, nonlinear model for higher accuracy and for tracking erratic curve of nonlinear performance in micro-scale Hybrid-BIST [Ohletz, Zeng, Jas, Jervan] Based on conversion of existing digital BIST structure to analog BIST Test stimulus obtained from D/A conversion of test pattern generator Analog test stimulus fed to different analog sub circuits Output response analysis after A/D conversion of the test response Linear-feedback-shift-register (LFSR) used to perform signature analysis 13

14 Dithering Theory [J. Vanderkoov et al.] Enhancement of resolution Swinging input to constant output Adding dithering to stimulate adjacent codes Constant to swinging response Smearing between two codes by averaging sets of noisy outputs Two-level outputs ADC output Dithered 32-trace avg 960-trace avg 14

15 Dithering Theory (cont ) Dither model Stair case output q: Vin g( ) q Convoluted form Given a fixed Vin, v term is integrated Smeared, linearized behavior No dither Vin p(v) v v Σ g( ) q Gaussian dither of 1 LSB rms 16 averaged output spectra 15

16 Dithering Theory (cont ) Identified more accurate harmonics Use Gaussian dither in general Similar idea from windowing for spectral leakage Quite small noise Extraction technique Irrelevant to harmonic testing 16

17 Polynomial Test [F. Attivissimo et al.] Fourier expansion x(t) y(t) 17

18 Polynomial Test (cont ) Chebyshev polynomial CC nn xx CC VV = cos nn xx CC VV If NN h, then x(t) y(t) h(x) 18

19 Polynomial Test (cont ) Introduces truncation errors: ee xx = h xx gg(xx) 30 harmonics 100 harmonics Enhancement opportunity Lower noise floor than high-order harmonics Given harmonics, linearity test time and test cost to be saved 19

20 Loopback Test for Calibration [W. Jiang et al.] Loopback configuration DUT DUT 20

21 Loopback Test for Calibration (cont ) Characterization for DAC INL Simplified polynomial fitting algorithm Simplified polynomial fitting algorithm 21

22 Loopback Test for Calibration (cont ) Calibration by compensating DAC output 22

23 Loopback Test for Calibration (cont ) Characterization for ADC INL 23

24 Loopback Test for Calibration (cont ) Calibration by compensating ADC output (from simplified polynomial fitting algorithm) 24

25 Loopback Test for Calibration (cont ) Issues to be resolved for enhanced correlation Higher error rate of DAC INL with nonlinearity present in m-adc Fault masking issue For ADC INL, poorly calibrated DAC output resulting in high error rate of ADC INL For ADC calibration, INL polynomial with low correlation to cause high errors in calibrated ADC output 25

26 Harmonic Test using INL [J. Duan et al.] Relation between input signal and output response Vin(tk) ADC C(tk) Input referred noise Offset code Gain error Quantization noise Transition level voltage 26

27 Harmonic Test using INL (cont ) 27

28 Harmonic Test using INL (cont ) If aforementioned equations are rewritten, then Spectral representations of INL terms are obtained to identify harmonics Fundamental Harmonics Noise floor DC 28

29 Thank you! Any Questions? Byoungho Kim, Ph.D. Division of Electrical Engineering Hanyang University

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