Probe Card System for DHP Chip Testing

Transcription

1 Probe Card System for DHP Chip Testing VXD Workshop, Wetzlar, February 4-6, 213 H. Krüger, Bonn University

2 4x JTAG 4x LVDS Gbit TX 4x JTAG 64x HSTL 18x CMOS PXD modules are sensitive to singlepoint-of-failure of the DHP Up to know very little statistics of the DHP yield (+ flip chip mounting to wirebond adapters with low yield only) Need to qualify ICs before flip-chip mounting Motivation To/from DCD (86 CMOS/HSTL) DHP 4 x LVDS To Switcher (4x LVDS) To/from DHH (9x LVDS) VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 2

3 What is needed: DHP Chip Probing Prerequisites Needle card for solder bump probing Test bench for DHP environment IO signals from test system (DHH like) DCD input/output emulation Test procedure to provide full coverage Definition of cut parameters for chip classification Design is based on DHP.2 DHPT 1.x will be pin compatible to DHP.2 VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 3

4 VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn DAC 4 DHP Chip Probe Test System Power Supply Needle Card PCB GPIB or USB DHP test system (XUPV5 FPGA Board) Infiniband JTAG FPGA DCD emulation Sequencer r/b Probe Needles Eth DHP Probe Station

5 Thousands 3685µm VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 2µm bumps to connect: 159 out of µm Thousands 159 bumps need to be connected Material: lead free, LTS Pitch: 2µm (y), 18µm (x) ~11µm diameter Connections: JTAG (4x LVDS) Timing (4x LVDS) Data Link (1x CML) Aux clock (2x LVDS) SWITCHER (4x LVDS) DCD out (8x 8 HSTL) DCD in (8x 2 CMOS) DCD timing (2x CMOS) DCD JTAG DCD_ref (analog) DHP test system FPGA Power (8x VSS, 4x VDD, 2x VDD_CML) PLLxx2Fast FrameSync ResetB (CMOS) Analog IO test signals 3685µm

6 A no bump 2 B 3 C 4 D 5 E 6 F 7 G 8 H 9 J 1 K 11 L 12 M 13 N 14 O 15 P 16 Q 17 R 18 S 19 T 2 U 21 V 22 W 23 X 24 Y 25 Z 26 AA 27 AB 28 AC 29 AD 3 AE 31 AF 32 AG 33 AH 34 AJ 35 AK 36 AL 37 AM Bump coordinates in µm Origin in upper left corner No bump at location (,) Bumps with no needle connection shown in gray VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni 6 Bonn

7 VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 8 DHP.2 Layout Examples from vendor

8 PCB with active components, will need some debugging Very sensitive with needles attached Debug Probe Card Dedicated debug Probe Card (almost) same netlist as needle card PCB replace needle footprint with DHP.2 wire bond adapter Debug PCB is ready and tested DHP communication FPGA programming (DCD emulation, Switcher sequencer read-back) Debug Probe Card VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 9

9 Specs 6 layer PCB 3mm thick mechanical stiffness Needle Card PCB Status PCB Design & Production Component mounting Testing Needle mounting needs ~4 weeks (@ HTT) Needle Probe Card (w/o needles) VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 1

10 Needle card fixture We have diced chips only put single chips on chuck (Ok for now) chess board fixture with array of cavities for production testing tbd External components: Power supply DHP test system (FPGA board via Infiniband cables) extra JTAG for on board FPGA programming/readback, optional: can use JTAG from Infiniband connection Probe Station Setup VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 11

11 Probe Card System Status Hardware components of the needle card test system Debug probe card for HW verification and debugging Needle probe card: components mounted and tested, shipped for needle mounting end of January (takes ~4 weeks) Mechanical fixture for probe station Software based on DHP test system from Mikhail ( ) needs further extensions (for basic testing ok) Planning (more) systematic sequencer and DHP DAC output read-back automation of test sequences coverage definition of cut parameters Start commissioning of the needle card system by end of Feb First (rudimentary) tested DHP chips supposed to be available in March VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 12

12 DHP Chip Availability Only small number of DHP.2 chips left (~15) Next chip version (DHPT 1.) available by mid 213 Need certain number of tested chips for E-MCM and PXD6 large matrix assemblies Possible scenarios: a) DHP has high yield, enough Ok tested die for E-MCM + PXD6 (very optimistic) no action needed b) DHP yield not sufficient, need more chips (more likely) i) Buy remaining MPW chips from MOSIS (rather expensive) ii) iii) Wait for DHPT 1. to become available (maybe too late) Recover unsuccessful DHP.2 flip chip assemblies (quite a few) Recovery procedure De-solder and clean DHP chips (Valencia?) Place new bumps (Heidelberg?) VXD Workshop, Wetzlar, Feb. 213, H. Krüger, Uni Bonn 13