LNBH26S. Dual LNBS supply and control I²C with step-up and IC interface. Datasheet. Features. Applications. Description

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1 Datasheet Dual LNS supply and control I²C with stepup and IC interface Features Complete interface between LN and I²C bus uiltin DCDC converter for single 2 V supply operation and high efficiency (typ. ) Selectable output current limit by external resistor Compliant with main satellite receiver output voltage specification (5 programmable levels) ccurate builtin 22 khz tone generator suits widely accepted standards 22 khz tone waveform integrity guaranteed at noload condition as well Low drop post regulator and high efficiency stepup PWM with integrated power NMOS allowing low power losses LPM function (low power mode) to reduce dissipation Overload and overtemperature internal protection with I²C diagnostic bits LN shortcircuit dynamic protection +/ 4 kv ESD tolerant on output power pins pplications ST satellite receivers TV satellite receivers PC card satellite receivers Maturity status link LNH26S Device summary Order code LNH26SPQR Package QFN24 (4 x 4) Packing Tape and reel Description Intended for analog and digital dual satellite receivers/sattv, and SatPC cards, the LNH26S is a monolithic voltage regulator and interface IC, assembled in QFN24 4 x 4 specifically designed to provide the 3/8 V power supply and the 22 khz tone signaling to the LN downconverter in the antenna dishes or to the multiswitch box. In this application field, it offers a complete solution for dual tuner satellite receivers with extremely low component count, low power dissipation together with simple design and I²C standard interfacing. DS8975 Rev 5 June 28 For further information contact your local STMicroelectronics sales office.

2 lock diagram lock diagram Figure. lock diagram DSQIN DDR SCL SD DSQIN LX LX PGND VUP Isense PWM CTRL I²C digital core DC Drop control Tone ctrl Diagnostics Protections PWM CTRL Isense PGND VUP VOUT Gate ctrl Linear regulator Linear regulator Gate ctrl VOUT DETIN DSQOUT PSW Tone detector Current limit selection Voltage reference Tone detector DETIN DSQOUT PSW FLT ISEL GND YP VCC GIPG22533LM DS8975 Rev 5 page 2/35

3 pplication information (valid for each section /) 2 pplication information (valid for each section /) The LNH26S includes two completely independent sections. Except for ISEL, V CC and I²C inputs, each circuit can be separately controlled and have their independent external components. ll the specifications below must be considered equal for both sections (/). This IC has a builtin DCDC stepup converter that, from a single source (8 V to 6 V), generates the voltages (V UP ) that let the integrated LDO postregulator (generating the 3 V / 8 V LN output voltages plus the 22 khz DiSEqC tone) work with a minimum dissipated power of.5 W 5 m load (the LDO drop voltage is internally kept at V UP V OUT = V typ.). The LDO power dissipation can be further reduced when 22 khz tone output is disabled by setting the LPM bit to (see LPM function description). The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied V CC drops below a fixed threshold (4.7 V typ.). The stepup converter softstart function reduces the inrush current during startup. The SS time is internally fixed at 4 ms typ. to switch from to 3 V, and 6 ms typ. to switch from to 8 V. 2. DISEQC data encoding (DSQIN pin) The internal 22 khz tone generator is factory trimmed in accordance with the DiSEqC standards, and can be activated in 3 different ways:. by an external 22 khz source DiSEqC data connected to the DSQIN logic pin (TTL compatible). In this case the I²C tone control bits must be set: EXTM=TEN=. 2. by an external DiSEqC data envelope source connected to the DSQIN logic pin. In this case the I²C tone control bits must be set: EXTM= and TEN=. 3. through the TEN I²C bit if the 22 khz presence is requested in continuous mode. In this case the DSQIN TTL pin must be pulled HIGH and the EXTM bit set to. Each of the above solutions requires that during the 22 khz tone activation and/or DiSEqC data transmission, the LPM bit must be set to see Section 2.4 LPM (low power mode). 2.2 Data encoding by external 22 khz tone TTL signal In order to improve design flexibility an external tone signal can be input to the DSQIN pin by setting the EXTM bit to. The DSQIN is a logic input pin which activates the 22 khz tone to the V OUT pin, by using the LNH26S integrated tone generator. The output tone waveforms are internally controlled by the LNH26S tone generator in terms of rise/fall time and tone amplitude, while, the external 22 khz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone. TTL compatible 22 khz signal is required for the proper control of the DSQIN pin function. efore sending the TTL signal on the DSQIN pin, the EXTM and TEN bits must be previously set to. s soon as the DSQIN internal circuit detects the 22 khz TTL external signal code, the LNH26S activates the 22 khz tone on the V OUT output with about µs delay from TTL signal activation, and it stops with about 6 µs delay after the 22 khz TTL signal on DSQIN has expired, refer to Figure 2. Tone enable and disable timing (using external waveform). Figure 2. Tone enable and disable timing (using external waveform) DSQIN Tone output ~ µs ~ 6 µs GIPG26529LM DS8975 Rev 5 page 3/35

4 Data encoding by external DiSEqC envelope control through the DSQIN pin 2.3 Data encoding by external DiSEqC envelope control through the DSQIN pin If an external DiSEqC envelope source is available, it is possible to use the internal 22 khz generator activated during the tone transmission by connecting the DiSEqC envelope source to the DSQIN pin. In this case the I²C tone control bits must be set: EXTM= and TEN=. In this way the internal 22 khz signal is superimposed on the V OUT DC voltage to generate the LN output 22 khz tone. During the period in which the DSQIN is kept HIGH the internal control circuit activates the 22 khz tone output. The 22 khz tone on the V OUT pin is activated with a delay of about 6 µs from DSQIN TTL signal rising edge, and it stops with a delay time in the range of 5 µs to 6 µs after the 22 khz TTL signal on DSQIN has expired, refer to Figure 3. Tone enable and disable timing (using envelope signal). Figure 3. Tone enable and disable timing (using envelope signal) DSQIN Tone output ~ 6 µs 5 µs ~ 6 µs GIPG265226LM 2.4 LPM (low power mode) In order to reduce total power loss, each section of the LNH26S is provided with the LPM I²C bit that can be activated (LPM=) in applications where the 22 khz tone can be disabled for long time periods. The LPM bit can be set to when the DiSEqC data transmission is not requested (no 22 khz tone output is present); in this condition the drop voltage across the integrated LDO regulator (V UP V OUT ) is reduced to.6 V typ. and, consequently, the power loss inside the relative LNH26S channel regulator is reduced too. For example, at 5 m load, LPM=, allowing a minimum LDO dissipated power of.3 W typ. It is recommended to set the LPM bit to before starting the 22 khz DiSEqC data transmission; in this condition the drop voltage across the LDO is kept to V typ. Keep LPM= all times if LPM function is not used. 2.5 DISEQC 2. implementation The builtin 22 khz tone detector completes the fully bidirectional DiSEqC 2. interfacing. Each LNH26S section DETIN pin must be C coupled to the DiSEqC bus, and extracted PWK data is available on the corresponding DSQOUT pin. To comply with the bidirectional DiSEqC 2. bus hardware requirements, an output RL filter is needed (per each voltage output pin). In order to avoid 22 khz waveform distortion during tone transmission, each LNH26S section is provided with a PSW pin to be connected to an external transistor, which allows the bypassing of the corresponding output RL filter in DiSEqC 2.x applications while in transmission mode. efore starting tone transmission by means of the DSQIN pin, provide that the TEN bit is preventively set to and after ending tone transmission, provide that the TEN bit is set to. 2.6 Output current limit selection The linear regulators current limit threshold can be set by an external resistor connected to the ISEL pin. The resistor value defines the output current limit by the equation: with ISET = I MX typ. = 6578 RSEL.26 () with ISET = 6452 I MX typ. = RSEL.59 (2) DS8975 Rev 5 page 4/35

5 Output voltage selection where RSEL is the resistor connected between ISEL and GND expressed in kω and I LIM (typ.) is the typical current limit threshold expressed in m. I LIM can be set up to for each channel. However, it is recommended to not exceed, for a long period, a total amount of current of from both sections (I OUT_ + I OUT_ < ) in order to avoid the overtemperature protection triggering and to thoroughly validate the PC layout thermal management in real application environment conditions. 2.7 Output voltage selection Each linear regulator channel output voltage level can be easily programmed in order to accomplish application specific requirements, using bits of an internal DT register see and Table 3. Output voltage selection (data register, write mode) for exact programmable values. Register writing is accessible via the I²C bus. 2.8 Diagnostic and protection functions The LNH26S has 4 diagnostic internal functions provided via the I²C bus, by reading 4 bits on two STTUS registers (in read mode). ll the diagnostic bits are, in normal operation (that is, no failure detected), set to LOW. One diagnostic bit is dedicated to the overtemperature status (OTF), one bit is dedicated to the input voltage power not good function (PNG), while the remaining 2 bits (6 per channel) are dedicated to the overload protection status (OLF), to the output voltage level (VMON), to 22 khz tone characteristics (TMON), to the minimum load current (IMON), to external voltage source presence on the V OUT pin (PDO), and to 22 khz tone presence on the DETIN pin (TDET). Once the OLF (or the OTF or PNG) bit has been activated (set to ), it is latched to until the relevant cause is removed and a new register reading operation is done. 2.9 Surge protections and TVS diodes Each LNH26S device section is directly connected to the antenna cable in a settop box. tmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices. Surge pulses occur due to direct or indirect lightning strikes to an external (outdoor) circuit. This leads to currents or electromagnetic fields causing high voltage or current transients. Transient voltage suppressor (TVS) devices are usually used, as shown in the following schematic Figure 4. Surge protection circuit to protect each section of ST output circuits where the LNH26S and other devices are electrically connected to the antenna cable. Figure 4. Surge protection circuit For this purpose we recommend the use of LNTVSxx surge protection diodes specifically designed by ST. The selection of the LNTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting (see the LNTVS datasheet for further details). 2. FLT: fault FLG In order to get an immediate feedback on a diagnostic status, the LNH26S is equipped with a dedicated fault flag pin (FLT). In the case an overload (OLF bit=), overheating (OTF bit=) or power not good (PNG bit=) condition is detected, the FLT pin (open drain output) is set to low and is kept low until the relevant activating diagnostic bit is cleared. e aware that diagnostic bits OLF, OTF and PNG, once activated, are kept latched to DS8975 Rev 5 page 5/35

6 VMON: output voltage diagnostic until the origin cause is removed and a new register reading operation is performed by the microprocessor. The FLT pin must be connected to a positive voltage (5 V max.) by a pullup resistor. 2. VMON: output voltage diagnostic When one device output voltage is activated (V OUT pin), its value is internally monitored and, as long as the output voltage level is below the guaranteed limits, the relevant VMON I²C bit is set to, see Table 6. Output voltage diagnostic (VMON/ bits, STTUS register) characteristics for more details. 2.2 TMON: 22 khz tone diagnostic The 22 khz tone can be internally detected and monitored if one (or both) DETIN pin are connected to the LN output bus (see Figure 7. DiSEqC 2.x application circuit) through a decoupling capacitor. The tone diagnostic function is provided with the corresponding TMON I²C bit. If the 22 khz tone amplitude and/or the tone frequency is out of the guaranteed limits, see Table khz tone diagnostic (TMON/ bit, STTUS 2 register) characteristics, the corresponding TMON I²C bit is set to. 2.3 TDET: 22 khz tone detection When a 22 khz tone presence is detected on one DETIN pin, the corresponding TDET I²C bit is set to. 2.4 IMON: minimum output current diagnostic In order to detect the output load absence (no LN connected on the bus or cable not connected to the IRD) each LNH26S section is provided with a minimum output current flag by the corresponding IMON I²C bit, accessible in read mode, which is set to if the output current is lower than 2 m (typ.). It is recommended to use the IMON function only with the 22 khz tone transmission deactivated, otherwise the IMON bit could be set to even if the output current is below the minimum current threshold. To activate the IMON diagnostic function, set to the EN_IMON I²C bit in the DT4 register. e aware that as soon as the IMON function is activated by means of EN_IMON=, the V OUT is immediately increased to 2 V (typ.) independently on the VSEL bit setting. This operation is applied in order to be sure that the LNH26S output has the higher voltage present in the LN bus. Do not use this function in an application environment where a 2 V voltage level is not supported by other peripherals connected to the LN bus. 2.5 PDO: overcurrent detection on output pulldown stage When an overcurrent occurs on one section pulldown output stage due to an external voltage source greater than the LNH26S nominal V OUT, and for a time longer than I SINK_TIME_OUT ( ms typ.), the corresponding PDO I²C bit is set to. This may happen due to an external voltage source presence on the LN output (V OUT pin). For current threshold and deglitch time details, see Table 2. / section electrical characteristics. 2.6 Poweron I²C interface reset and undervoltage lockout The I²C interface built into the LNH26S is automatically reset at poweron. s long as the V CC stays below the undervoltage lockout (UVLO) threshold (4.7 V typ.), the interface does not respond to any I²C command and all DT register bits are initialized to zeroes, therefore keeping the power blocks disabled. Once the VCC rises above 4.8 V typ., the I²C interface becomes operative and the DT registers can be configured by the main microprocessor. 2.7 PNG: input voltage minimum detection When input voltage (V CC pin) is lower than LPD (low power diagnostic) minimum thresholds, the PNG I²C bit is set to and the FLT pin is set LOW. DS8975 Rev 5 page 6/35

7 ISW: inductor switching current limit 2.8 ISW: inductor switching current limit In order to allow low saturation current inductors to be used, the maximum DCDC inductor switching current limit threshold can be set by one I²C bit per section (ISW). Two values are available: 2.5 typ. (with ISW = ) and 4 typ. (with ISW = ). 2.9 COMP: boost capacitors and inductor The DCDC converter compensation loop can be optimized in order to properly work with both ceramic and electrolytic capacitors (V UP pin). For this purpose, one I²C bit in the DT 4 register (see COMP ) can be set to or as follows: COMP = for electrolytic capacitors COMP = for ceramic capacitors For recommended DCDC capacitor and inductor values refer to Section 5 Typical application circuits and to the OM in Table 4. LNH26S DiSEqC.x bill of material. 2.2 OLF: overcurrent and shortcircuit protection and diagnostic In order to reduce the total power dissipation during an overload or a shortcircuit condition, each section of the device is provided with a dynamic shortcircuit protection. It is possible to set the shortcircuit current protection either statically (simple current clamp) or dynamically by the corresponding PCL bit of the I²C DT3 register. When the PCL (pulsed current limiting) bit is set lo LOW, the overcurrent protection circuit works dynamically: as soon as an overload is detected, the output current is provided for T ON time (9 ms or 8 ms typ., according to the corresponding TIMER bit programmed in the DT3 register) and after that, the output is set in shutdown for a T OFF time of typically 9 ms. Simultaneously, the corresponding diagnostic OLF I²C bit of the STTUS register is set to and the FLT pin is set to low level. fter this time has elapsed, the involved output is resumed for a time T ON. t the end of T ON, if the overload is still detected, the protection circuit cycles again through T OFF and T ON. t the end of a full T ON in which no overload is detected, normal operation is resumed and the OLF diagnostic bit is reset to LOW after register reading is done. Typical T ON +T OFF time is 99 ms (if TIMER=) or 8 ms (if TIMER=) and is determined by an internal timer. This dynamic operation can greatly reduce the power dissipation in shortcircuit condition, still ensuring excellent poweron startup in most conditions. However, there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen. This can be solved by initiating any power startup in static mode (PCL=) and then, switching to dynamic mode (PCL=) after a chosen amount of time, depending on the output capacitance. lso in static mode, the diagnostic OLF bit goes to (and the FLT pin is set to low) when the current clamp limit is reached and returns LOW when the overload condition is cleared and register reading is done. fter the overload condition is removed, normal operation can be resumed in two ways, according to the OLR I²C bit on the DT4 register. If OLR=, all VSEL bits corresponding to the involved section are reset to and the LN section output (V OUT pin) is disabled. To reenable the output stage, the VSEL bits must be set again by the microprocessor and the OLF bit is reset to after a register reading operation. If OLR=, the involved output is automatically reenabled as soon as the overload condition is removed, and the OLF bit is reset to after a register reading operation. 2.2 OTF: thermal protection and diagnostic The LNH26S is also protected against overheating: when the junction temperature exceeds 5 C (typ.), the stepup converter and both liner regulators are shut off, the diagnostic OTF bit in the STTUS register is set to and the FLT pin is set to low level. fter the overtemperature condition is removed, normal operation can be resumed in two ways, according to the THERM I²C bit on the DT4 register. If THERM=, all VSEL bits are reset to and both LN outputs (V OUT pins) are disabled. To reenable output stages, the VSEL bits must be set again by the microprocessor, while the OTF bit is reset to after a register reading operation. If THERM=, outputs are automatically reenabled as soon as the overtemperature condition is removed, while the OTF bit is reset to after a register reading operation. DS8975 Rev 5 page 7/35

8 Pin configuration 3 Pin configuration Figure 5. Pin connections (top view) DSQOUT DSQIN DSQIN VUP VOUT DETIN DSQOUT PSW 8 2 FLT VCC 7 3 LX YP 6 4 PGND GND 5 5 LX PSW 4 6 DDR DETIN 3 SCL SD ISEL NC VUP VOUT GIPG275333LM Table. Pin description Pin Symbol Name Pin function DSQOUT DiSEqC output 2 FLT FLT Open drain output of channel tone detector to the main microcontroller for DiSEqC 2. data decoding. It is low when tone is detected on the DETIN input pin. Set to ground if not used. Open drain output for IC fault conditions. It is set low in case of overload (OLF bit) or overheating status (OTF bit) or power not good (PNG bit) is detected. To be connected to pullup resistor (5 V max.). 3 LX NMOS drain Channel, integrated Nchannel power MOSFET drain. 4 PGND Power ground DCDC converter power ground. To be connected directly to the exposed pad. 5 LX NMOS drain Channel, integrated Nchannel power MOSFET drain. 6 DDR ddress setting Two I 2 C bus addresses available by setting the address pin level voltage. See Table 5. ddress pin characteristics. 7 SCL Serial clock Clock from I²C bus. 8 SD Serial data idirectional data from/to I²C bus. 9 ISEL N.C. Current selection for both channel and Not internally connected The resistor RSEL connected between ISEL and GND defines the linear regulator current limit threshold. Refer to Section 2.5 DISEQC 2. implementation. The RSEL resistor defines the same current limit both for channels and. Not internally connected pin. Set floating if not used. DS8975 Rev 5 page 8/35

9 Pin configuration Pin Symbol Name Pin function V UP Channel stepup voltage 2 V OUT Channel LN output port 3 DETIN Tone detector input 4 PSW Switch control Input of channel linear postregulator. The voltage on this pin is monitored by the internal channel stepup controller to keep a minimum dropout across the linear pass transistor. Output of channel integrated very low drop linear regulator. See Table 3. Output voltage selection (data register, write mode) for voltage selection and description. Channel, 22 khz tone decoder input, must be C coupled to the DiSEqC 2. bus. Set to ground if not used. To be connected to an external transistor to be used to bypass the channel output RL filter needed in DiSEqC 2.x applications during the DiSEqC transmitting mode (see Section 5 Typical application circuits). Set ground if not used. Open drain pin. 5 GND nalog ground nalog circuit ground. To be connected directly to the exposed pad. 6 YP ypass capacitor Needed for internal preregulator filtering. The YP pin is intended to connect an external ceramic capacitor only. ny connection of this pin to external current or voltage sources may cause permanent damage to the device. 7 V CC Supply input 8 to 6 V IC DCDC power supply. 8 PSW Switch control 9 DETIN Tone detector input 2 V OUT Channel, LN output port 2 V UP Channel stepup voltage To be connected to an external transistor to be used to bypass the channel output RL filter needed in DiSEqC 2.x applications during the DiSEqC transmitting mode (see Section 5 Typical application circuits). Set to ground if not used. Open drain pin. Channel, 22 khz tone decoder input, must be C coupled to the DiSEqC 2. bus. Set to ground if not used. Output of channel integrated very low drop linear regulator. See Table 3. Output voltage selection (data register, write mode) for voltage selection and description. Input of channel linear postregulator. The voltage on this pin is monitored by the internal channel stepup controller to keep a minimum dropout across the linear pass transistor. 22 DSQIN DSQIN for DiSEqC envelope input or external 22 khz TTL input It is intended for channel 22 khz tone control. It can be used as DiSEqC envelope input or external 22 khz TTL input depending on the EXTM I²C bit setting as follows: If EXTM=, TEN=: it accepts the DiSEqC envelope code from the main microcontroller. The LNH26S uses this code to modulate the internally generated 22 khz carrier. If EXTM=TEN=: it accepts external 22 khz logic signals which activate the 22 khz tone output (refer to Section 2.2 Data encoding by external 22 khz tone TTL signal). Pull up high if the tone output is activated by the TEN I²C bit only. 23 DSQOUT DiSEqC output Open drain output of channel tone detector to the main microcontroller for DiSEqC 2. data decoding. It is low when tone is detected to the DETIN input pin. Set ground if not used. 24 DSQIN DSQIN for DiSEqC envelope input or external 22 khz TTL input It is intended for channel 22 khz tone control. It can be used as DiSEqC envelope input or external 22 khz TTL input depending on the EXTM I²C bit setting as follows: if EXTM=, TEN=: it accepts the DiSEqC envelope code from the main microcontroller. The LNH26S uses this code to modulate the internally generated 22 khz carrier. If EXTM=TEN=: it accepts external 22 khz logic signals which activate the 22 khz tone output (refer to Section 2.2 Data encoding by external 22 khz tone TTL signal). Pull up high if the tone output is activated by the TEN I²C bit only. Epad Epad Exposed pad To be connected with power grounds and to ground layer through vias to dissipate the heat. DS8975 Rev 5 page 9/35

10 Maximum ratings 4 Maximum ratings Table 2. bsolute maximum ratings Symbol Parameter Value Unit V CC DC power supply input voltage pins.3 to 2 V V UP DC input voltage.3 to 4 V I OUT Output current Internally limited m V OUT DC output pin voltage.3 to 4 V V I Logic input pin voltage (SD, SCL, DSQIN, DDR pins).3 to 7 V V O Logic output pin voltage (FLT, DSQOUT).3 to 7 V V PSW PSW pin voltage.3 to 4 V V DETIN Detector input signal amplitude.6 to 2 V I O Logic output pin current (FLT, DSQOUT, PSW) m LX LX input voltage.3 to 3 V V YP Internal reference pin voltage.3 to 4.6 V I SEL Current selection pin voltage.3 to 3.5 V T STG Storage temperature range 5 to 5 C T J Operating junction temperature range 25 to 25 C T JMX Maximum junction temperature 5 C ESD ESD rating with human body model (HM) for all pins, except power output pins 2 ESD rating with human body model (HM) for power output pins 4 kv Table 3. Thermal data Symbol Parameter Value Unit RthJC Thermal resistance junctioncase 2 C/W RthJ Thermal resistance junctionambient with device soldered on 2s2p 4layer PC provided with thermal vias below exposed pad 4 C/W Note: bsolute maximum ratings are those values beyond which damage to the device may occur. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to absolutemaximumrated conditions for extended periods may affect device reliability. ll voltage values are with respect to network ground terminal. DS8975 Rev 5 page /35

11 Typical application circuits 5 Typical application circuits Figure 6. DiSEqC.x application circuit D2 2 VUP VOUT 2 LNOUT D C2 C3 LNH26S C5 D3 3 LX Vin 2 V C L L R (RSEL) 9 ISEL C4 C7 I 2 C us { 6 yp 7 Vcc 8 SD 7 SCL DSQIN 22 DSQIN 24 DDR 6 FLT 2 DiSEqC 22 KHz TTL Tone enable control or DiSEqC Envelope TTL 5 LX D C2 C3 VUP P GND GND 4 5 VOUT 2 C5 D3 LNOUT D2 GIPG285243LM Table 4. LNH26S DiSEqC.x bill of material Component R (RSEL) C C2 C3 C5 Notes Smd resistor. Refer to Table 2. / section electrical characteristics and ISEL pin description in Table. Pin description. > 25 V electrolytic capacitor, µf or higher is suitable or > 25 V ceramic capacitor, µf or higher is suitable With COMP =, > 25 V electrolytic capacitor, µf or higher is suitable or with COMP =, > 35 V ceramic capacitor, 22 µf (or 2 x µf) or higher is suitable From 47 nf to 2.2 µf ceramic capacitor placed as close as possible to V UP pins. Higher values allow lower DCDC noise From nf to 22 nf ceramic capacitor placed as close as possible to V OUT pins. Higher values allow lower DCDC noise C4, C7 22 nf ceramic capacitors. To be placed as close as possible to V OUT pin D D2 D3 STPS3 or similar Schottky diode N47, SSM, or any similar general purpose rectifier T54, T43, N588, or any low power Schottky diode with I F (V) >.2, V RRM > 25 V, V F <.5 V. To be placed as close as possible to V OUT pin DS8975 Rev 5 page /35

12 Typical application circuits Component Notes With COMP=, use µh inductor with I ST > I PEK where I PEK is the boost converter peak current L or with COMP= and C2 = 22 µf, use 6.8 µh inductor with I ST > I PEK where I PEK is the boost converter peak current Figure 7. DiSEqC 2.x application circuit D2 2 VUP VOUT C5 2 D3 L2 5 W LNOUT Vin 2 V C D L L D C2 C3 R (RSEL) 9 C7 C4 I 2 C us{ 3 6 LX ISEL yp 7 Vcc 8 7 SD SCL 5 LX LNH26S 4.7 k (optional) PSW k TR DETIN 9 k DSQOUT C6 23 DSQIN 22 DSQIN 24 DDR 6 FLT 2 DSQOUT DETIN k PSW 4 DiSEqC 22KHz Tone enable control Open drains to µcontroller k 4.7k (optional) C6 TR DiSEqC Envelope or TTL TTL C2 C3 VUP VOUT 2 PGND GND 4 5 C5 D3 5 W L2 LNOUT D2 GIPG285323LM Table 5. LNH26S DiSEqC 2.x bill of material Component R (RSEL) C C2 C3 C5 Notes SMD resistor. Refer to Table 2. / section electrical characteristics and ISEL pin description in Table. Pin description. > 25 V electrolytic capacitor, µf or higher is suitable or > 25 V ceramic capacitor, µf or higher is suitable With COMP =, > 25 V electrolytic capacitor, µf or higher is suitable or with COMP =, > 35 V ceramic capacitor, 22 µf (or 2 x µf) or higher is suitable From 47 nf to 2.2 µf ceramic capacitor placed as close as possible to V UP pins. Higher values allow lower DCDC noise From nf to 22 nf ceramic capacitor placed as close as possible to V OUT pins. Higher values allow lower DCDC noise C4, C7 22 nf ceramic capacitors. To be placed as close as possible to V OUT pin D STPS3 or similar Schottky diode DS8975 Rev 5 page 2/35

13 Typical application circuits Component D2 D3 Notes N47, SSM, or any similar general purpose rectifier T54, T43, N588, or any low power Schottky diode with I F (V) >.2, V RRM > 25 V, V F <.5 V. To be placed as close as possible to V OUT pin With COMP=, use µh inductor with I ST > I PEK where I PEK is the boost converter peak current L L2 TR or with COMP= and C2 = 22 µf, use 6.8 µh inductor with I ST > I PEK where I PEK is the boost converter peak current 22 µh 27 µh inductor as per DiSEqC 2.x specification MMT92, 2STR26 or any low power PNP with I C > 25 m, V CE > 3 V, can be used lso any small power PMOS with I D > 25 m, R DS(on) <.5 W, V DS > 2 V, can be used DS8975 Rev 5 page 3/35

14 I²C bus interface 6 I²C bus interface Data transmission from the main microprocessor to the LNH26S and vice versa takes place through the 2wire I²C bus interface, consisting of the 2line SD and SCL (pullup resistors to positive supply voltage must be externally connected). 6. Data validity s shown in Figure 8. Data validity on the I²C bus, the data on the SD line must be stable during the high semiperiod of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 6.2 Start and stop condition s shown in Figure 9. Timing diagram of I²C bus, a start condition is HIGH to LOW transition of the SD line while SCL is HIGH. The stop condition is LOW to HIGH transition of the SD line while SCL is HIGH. STOP condition must be sent before each STRT condition. 6.3 yte format Every byte transferred to the SD line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MS is transferred first. 6.4 cknowledge The master (microprocessor) puts a resistive HIGH level on the SD line during the acknowledge clock pulse (see Figure. cknowledge on the I²C bus). The peripheral (LNH26S) which acknowledges must pull down (LOW) the SD line during the acknowledge clock pulse, so that the SD line is stable LOW during this clock pulse. The peripheral which has been addressed must generate acknowledge after the reception of each byte, otherwise the SD line remains at the HIGH level during the nin th clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. The LNH26S does not generate acknowledge if the V CC supply is below the undervoltage lockout threshold (4.7 V typ.). 6.5 Transmission without acknowledge If detection of the acknowledge of the LNH26S is not required, the microprocessor can use a simpler transmission: it simply waits for one clock without checking the slave acknowledging, and sends the new data. This approach is of course less protected from misworking and decreases noise immunity. DS8975 Rev 5 page 4/35

15 Transmission without acknowledge Figure 8. Data validity on the I²C bus SCL SD DT LINE STLE DT VLID DT CHNGE LLOWED GIPG22536LM Figure 9. Timing diagram of I²C bus SCL SD STRT STOP GIPG22547LM Figure. cknowledge on the I²C bus SCL SD MS CKNOWLEDGMENT FROM SLVE STRT GIPG22554LM DS8975 Rev 5 page 5/35

16 I²C interface protocol 7 I²C interface protocol 7. Write mode transmission The LNH26S interface protocol is made up of: a start condition (S) a chip address byte with the LS bit R/W = a register address (internal address of the first register to be accessed) a sequence of data (byte to write in the addressed internal register + acknowledge) the following bytes, if any, to be written in successive internal registers a stop condition (P). The transfer lasts until a stop bit is encountered the LNH26S, as slave, acknowledges every byte transfer Figure. Example of writing procedure starting with first data address x2 MS CHIP DDRESS LS REGISTER DDRESS MS LS S X R/W = CK X X X CK DT DT 2 DT 3 DT 4 dd=x2 dd=x3 dd=x4 dd=x5 MS LS MS LS MS LS MS LS VSEL4 VSEL3 VSEL2 VSEL VSEL4 VSEL3 VSEL2 VSEL CK N/ EXTM LPM TEN N/ EXTM LPM TEN CK TIMER PCL ISW ISET TIMER PCL ISW ISET CK COMP THERM N/ EN_IMON OLR N/ N/ EN_IMON CK P GIPG22523LM Note: CK = acknowledge S = start P = stop R/W = /, read/write bit X = /, set the values to select the chip address (see Table 5. ddress pin characteristics for pin selection) The writing procedure can start from any register address by simply setting the X values in the register address byte (after the chip address). It can be also stopped by the master by sending a stop condition after any acknowledge bit. 7.2 Read mode transmission In read mode the byte sequence must be as follows: a start condition (S) a chip address byte with the LS bit R/W= the register address byte of the internal first register to be accessed a stop condition (P) a new master transmission with the chip address byte and the LS bit R/W= after the acknowledge the LNH26S starts sending the addressed register content. s long as the master keeps the acknowledge LOW, the LNH26S transmits the next address register byte content DS8975 Rev 5 page 6/35

17 LNH26S Data registers the transmission is terminated when the master sets the acknowledge HIGH with a following stop bit Figure 2. Example of reading procedure starting with first status address X CHIP DDRESS REGISTER DDRESS CHIP DDRESS MS LS MS LS MS LS S X R/W = CK X X X CK P S X R/W = CK MS STTUS dd=x LS MS STTUS 2 dd=x LS PNG OTF PDO PDO VMON VMON N/ N/ IMON IMON TMON TMON TDET TDET CK OLF OLF CK DT DT 2 DT 3 DT 4 dd=x2 dd=x3 dd=x4 dd=x5 MS LS MS LS MS LS MS LS VSEL4 VSEL3 VSEL2 VSEL VSEL4 VSEL3 VSEL2 VSEL CK N/ EXTM LPM TEN N/ EXTM LPM TEN CK TIMER PCL ISW ISET TIMER PCL ISW ISET CK COMP THERM N/ EN_IMON OLR N/ N/ EN_IMON CK P GIPG22533LM Note: CK = acknowledge S = start P = stop R/W = /, read/write bit X = /, set the values to select the chip address, see Table 5. ddress pin characteristics for pin selection) and see Table. STTUS 2 (read register. Register address = X). The reading procedure can start from any register address (status, 2 or Data..4) by simply setting the X values in the register address byte (after the first chip address in the above figure). It can be also stopped by the master by sending a stop condition after any acknowledge bit. 7.3 Data registers Note: The data..4 registers can be addressed both to write and read mode. In read mode they return the last writing byte status received in the previous write transmission. The following tables provide the register address values of data..4 and a function description of each bit. The following tables provide the register address values of data..4 and a function description of each bit. DS8975 Rev 5 page 7/35

18 Data registers Table 6. DT (read/write register. Register address = X2) it Name CH Value Description it (LS) VSEL / it VSEL2 / it 2 VSEL3 / Channel Output voltage selection bits it 3 VSEL4 / it 4 VSEL / it 5 VSEL2 / it 6 VSEL3 / Channel Output voltage selection bits it 7 VSEL4 / Table 7. DT 2 (read/write register. Register address = X3) it Name CH Value Description it (LS) TEN 22 khz tone enabled. Tone output controlled by the DSQIN pin 22 khz tone output disabled it LPM Low power mode activated (used only with 22 khz tone output disabled) Low power mode deactivated (keep always LPM= during 22 khz tone transmission) it 2 EXTM DSQIN input pin is set to receive external 22 khz TTL signal source DSQIN input pin is set to receive external DiSEqC envelope TTL signal it 3 N/ Reserved. Keep to it 4 TEN 22 khz tone enabled. Tone output controlled by the DSQIN pin 22 khz tone output disabled it 5 LPM Low power mode activated (used only with 22 khz tone output disabled) Low power mode deactivated (keep always LPM= during 22 khz tone transmission) it 6 EXTM DSQIN input pin is set to receive external 22 khz TTL signal source DSQIN input pin is set to receive external DiSEqC envelope TTL signal it 7 (MS) N/ Reserved. Keep to DS8975 Rev 5 page 8/35

19 Data registers Table 8. DT 3 (read/write register. Register address = X4) it Name CH Value Description it (LS) ISET Current limit of LN output (VOUT pin) set to lower current range Current limit of LN output (VOUT pin) set to default range it ISW DCDC, inductor switching current limit set to 2.5 typ. DCDC, inductor switching current limit set to 4 typ. it 2 PCL Pulsed (dynamic) LN output current limiting is deactivated Pulsed (dynamic) LN output current limiting is activated it 3 TIMER Pulsed (dynamic) LN output current T ON time set to 8 ms typ. Pulsed (dynamic) LN output current T ON time set to 9 ms typ. it 4 ISET Current limit of LN output (VOUT pin) set to lower current range Current limit of LN output (VOUT pin) set to default range it 5 ISW DCDC, inductor switching current limit set to 2.5 typ. DCDC, inductor switching current limit set to 4 typ. it 6 PCL Pulsed (dynamic) LN output current limiting is deactivated Pulsed (dynamic) LN output current limiting is activated it 7 (MS) TIMER Pulsed (dynamic) LN output current T ON time set to 8 ms typ. Pulsed (dynamic) LN output current T ON time set to 8 ms typ. Table 9. DT 4 (read/write register. Register address = X5) it Name CH Value Description it (LS) EN_IMON IMON diagnostic function is enabled. (VOUT is set to 2 V typ.) IMON diagnostic function is disabled. Keep always at if IMON is not used it N/ it 2 Reserved. Keep to it 3 OLR / In the case of overload protection activation (OLF=), all VSEL bits are reset to and LN relevant output (VOUT pin) is disabled. The VSEL bits must be set again by the master after the overcurrent condition is removed (OLF=) In the case of overload protection activation (OLF=) the LN output (VOUT pin) is automatically enabled as soon as the overload condition is removed (OLF=) with the previous VSEL bit setting it 4 EN_IMON IMON diagnostic function is enabled IMON diagnostic function is disabled. lways keep if IMON is not used it 5 N/ Reserved. Keep DS8975 Rev 5 page 9/35

20 Status registers it Name CH Value Description it 6 THERM / If thermal protection is active (OTF=), all VSEL bits are reset to and LN output (VOUT pin) is disabled (both section and ). VSEL bits must be set again by the master after the overtemperature condition is removed (OTF=) In the case of thermal protection activation (OTF=) the LN output (VOUT pin) is automatically enabled as soon as the overtemperature condition is removed (OTF=) with the previous VSEL bit setting it 7 (MS) COMP DCDC converter compensation. Set to use very low E.S.R. capacitors or ceramic caps on VUP pin DCDC converter compensation. Set to use standard electrolytic capacitors on VUP pin 7.4 Status registers The STTUS, 2 registers can be addressed to read mode only and provide the diagnostic functions described in the following tables. Table. STTUS (read register. Register address = X) it Name CH Value Description it (LS) OLF it OLF it 2 VMON it 3 VMON it 4 PDO VOUT pin overload protection has been triggered (I OUT > I LIM ). No overload protection has been triggered to VOUT pin (I OUT < I LIM ) VOUT pin overload protection has been triggered (I OUT > I LIM ). No overload protection has been triggered to VOUT pin (I OUT < I LIM ) Output voltage (VOUT pin) is lower than VMON specification thresholds. Refer to Table 6. Output voltage diagnostic (VMON/ bits, STTUS register) characteristics Output voltage (VOUT pin) is within the VMON specifications Output voltage (VOUT pin) is lower than VMON specification thresholds. Refer to Table 6. Output voltage diagnostic (VMON/ bits, STTUS register) characteristics Output voltage (VOUT pin) is within the VMON specifications Overcurrent detected on output pulldown stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LN output (VOUT pin) No overcurrent detected on output pulldown stage it 5 PDO Overcurrent detected on output pulldown stage for a time longer than the deglitch period. This may happen due to an external voltage source present on the LN output (VOUT pin) No overcurrent detected on output pulldown stage DS8975 Rev 5 page 2/35

21 Status registers it Name CH Value Description it 6 it 7 (MS) OTF PNG / Junction overtemperature is detected, T J > 5 C (typ.). See also the THERM bit setting Junction overtemperature not detected, T J <35 C (typ.). T J is below thermal protection threshold Input voltage (VCC pin) is lower than LPD minimum thresholds. Refer to Table 2. / section electrical characteristics. Input voltage (VCC pin) is higher than LPD thresholds. Refer to Table 2. / section electrical characteristics. N/ = reserved bit ll bits reset to at poweron Table. STTUS 2 (read register. Register address = X) it Name CH Value Description it (LS) TDET it TDET 22 khz tone presence is detected on the DETIN pin No 22 khz tone is detected on the DETIN pin 22 khz tone presence is detected on the DETIN pin No 22 khz tone is detected on the DETIN pin it 2 TMON it 3 TMON it 4 IMON it 5 IMON 22 khz tone present on the DETIN pin is out of TMON specification thresholds. That is: the tone frequency or the TONE (tone amplitude) are out of the thresholds guaranteed in Table khz tone diagnostic (TMON / bit, STTUS 2 register) characteristics 22 khz tone present on the DETIN pin is within TMON specification thresholds. Refer to Table khz tone diagnostic (TMON/ bit, STTUS 2 register) characteristics 22 khz tone present on the DETIN pin is out of TMON specification thresholds. The tone frequency or the TONE (tone amplitude) is out of the thresholds guaranteed in Table khz tone diagnostic (TMON/ bit, STTUS 2 register) characteristics 22 khz tone present on DETIN pin is within TMON specification thresholds. Refer to Table khz tone diagnostic (TMON/ bit, STTUS 2 register) characteristics Output current (from VOUT pin) is lower than IMON specification thresholds. Refer to Table 7. Output current diagnostic (IMON/ bits, STTUS 2 register) characteristics Output current (from VOUT pin) is higher than IMON specifications. Refer to Table 7. Output current diagnostic (IMON/ bits, STTUS 2 register) characteristics Output current (from VOUT pin) is lower than IMON specification thresholds. Refer to Table 7. Output current diagnostic (IMON/ bits, STTUS 2 register) characteristics Output current (from VOUT pin) is higher than IMON specifications. Refer to Table 7. Output current diagnostic (IMON/ bits, STTUS 2 register) characteristics DS8975 Rev 5 page 2/35

22 Status registers it Name CH Value Description it 6 it 7 (MS) N/ Reserved N/ = reserved bit ll bits reset to at poweron DS8975 Rev 5 page 22/35

23 Electrical characteristics 8 Electrical characteristics Refer to Section 5 Typical application circuits, T J from to 85 C, all DT..4 register bits set to except VSEL =, RSEL = kω, DSQIN = low, V IN = 2 V, I OUT = 5 m, unless otherwise stated. Typical values are referred to T J = 25 C. V OUT = V OUT pin voltage. See Section 6 I²C bus interface and Section 7 I²C interface protocol. Table 2. / section electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit V IN Supply voltage () V oth sections and enabled I OUT = m 2 I IN Supply current 22 khz tone enabled (TEN/ =, DSQIN/ = high), I OUT = m 9 m oth sections and set in standby: VSEL=VSEL2=VSEL3=VSEL4= 2 V OUT Output voltage total accuracy Valid at any V OUT selected level % V OUT Line regulation V IN = 8 to 6 V 4 V OUT Load regulation I OUT from 5 to 75 m mv I LIM Output current limiting thresholds RSEL = kω, ISET = 75 RSEL = 5 kω, ISET = 5 75 RSEL = 2 kω, ISET = m I LIM Output current limiting thresholds RSEL = kω, ISET = 4 RSEL = 5 kω, ISET = 28 RSEL = 2 kω, ISET = 2 m I SC Output shortcircuit current RSEL = kω, ISET = 5 m SS Softstart time V OUT from to 3 V 4 ms SS Softstart time V OUT from to 8 V 6 ms T38 Soft transition rise time V OUT from 3 V to 8 V.5 ms T83 Soft transition fall time V OUT from 8 V to 3 V.5 ms T OFF T ON Dynamic overload protection offtime Dynamic overload protection ontime PCL =, output shorted 9 ms PCL = TIMER =, output shorted T OFF / PCL =, TIMER =, output shorted T OFF /5 DSQIN=high, EXTM=, TEN= TONE Tone amplitude I OUT from to 75 m V PP C US from to 75 nf F TONE Tone frequency khz D TONE Tone duty cycle DSQIN=high, EXTM=, TEN= % tr, tf Tone rise or fall time (2) µs DS8975 Rev 5 page 23/35

24 Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit Eff DC/DC F SW DCDC converter efficiency DCDC converter switching frequency I OUT = 5 m 93 % 44 khz UVLO Undervoltage lockout thresholds UVLO threshold rising 4.8 UVLO threshold falling 4.7 V V LP Low power diagnostic (LPD) thresholds V LP threshold rising 7.2 V V LP threshold falling 6.7 V IL DSQIN, pin logic low.8 V V IH DSQIN, pin logic high 2 V I IH DSQIN, pin input current V IH = 5 V 5 µ F DETIN V DETIN Z DETIN V OL Tone detector frequency capture range Tone detector input amplitude Tone detector input impedance DSQOUT, FLT pin logic LOW.4 V PP sine wave (3) khz Sine wave signal, 22 khz.3.5 V PP 5 kω DETIN tone present, I OL = 2 m.3.5 V I OL_PSW = 5 m V OL_PSW PSW pin low voltage DSQIN = high, EXTM =,.7 V TEN = I OZ DSQOUT, FLT pin leakage current DETIN tone absent, V OH = 6 V µ I OK Output backward current ll VSELx =, V OK = 3 V 3 6 m I SINK Output lowside sink current V OUT forced at V OUT_nom +. V 7 m V OUT forced at V OUT_nom I SINK_TIMEOUT Lowside sink current timeout +. V PDO I²C bit is set to after this time is elapsed ms V OUT forced at V OUT_nom I REV Max. reverse current +. V, after PDO bit is set to 2 m (I SINK_TIMEOUT elapsed) T SHDN Thermal shutdown threshold 5 C DT SHDN Thermal shutdown hysteresis 5 C. In applications where (V CC V OUT ) >.3 V, the increased power dissipation inside the integrated LDO must be taken into account in the application thermal management design. 2. Guaranteed by design. 3. Frequency range in which the DETIN function is guaranteed. The V pp level is intended on the LN bus (before the C6 capacitor. See typical application circuit for DiSEqC 2.x) I OUT from to 75 m, C US from to 75 nf. DS8975 Rev 5 page 24/35

25 Output voltage selection 8. Output voltage selection Each LNH26S channel is provided with 5 output voltage levels (7 levels for 3 V range when VSEL4/= and 8 levels for 8 V range when VSEL4/=) which can be selected through the register Data. Table 3. Output voltage selection (data register, write mode) shows the output voltage values corresponding to VSELx bit combinations both for channel and. If all VSELx are set to the device is set in standby mode and VOUT/ is disabled. T J from to 85 C, V I = 2 V Table 3. Output voltage selection (data register, write mode) VSEL4/ VSEL3/ VSEL2/ VSEL/ V OUT min. V OUT / pin voltage V OUT max. Function V OUT / disabled. The LNH26S sets in standby mode T J from to 85 C, V I = 2 V Table 4. I 2 C electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit V IL Low level input voltage SD, SCL.8 V IH High level input voltage SD, SCL 2 V I IN Input current SD, SCL V IN =.4 to 4.5 V µ V OL Low level output voltage () SD (open drain), I OL = 6 m.6 V F MX Maximum clock frequency SCL 4 khz. Guaranteed by design. T J from to 85 C, V I = 2 V DS8975 Rev 5 page 25/35

26 Output voltage selection Table 5. ddress pin characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit V DDR (R/W) address pin voltage range R/W bit determines the transmission mode: read (R/ W=) write (R/W=).8 V V DDR2 (R/W) address pin voltage range R/W bit determines the transmission mode: read (R/ W=) write (R/W=) 2 5 V Refer to Section 5 Typical application circuits, T J from to 85 C, all DT..4 register bits set to, RSEL = kω, DSQIN = low, V IN = 2 V, I OUT = 5 m, unless otherwise stated. Typical values are referred to T J = 25 C. V OUT = V OUT pin voltage. Table 6. Output voltage diagnostic (VMON/ bits, STTUS register) characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit V THL Diagnostic low threshold at V OUT = 3. V VSEL =, VSEL2 = VSEL3 = VSEL4 = % V THL Diagnostic low threshold at V OUT = 8.5 V VSEL4=, VSEL = VSEL2 = VSEL3 = % Note: If the output voltage is lower than the min. value the VMON I²C bit is set to. If VMON= then V OUT > 8% of V OUT (typ.). If VMON= then V OUT < 95% of V OUT (typ.). Note: Refer to Section 5 Typical application circuits, T J from to 85 C, RSEL = kω, DSQIN = low, V IN = 2 V, unless otherwise stated. Typical values are referred to T J = 25 C. V OUT = V OUT pin voltage. Table 7. Output current diagnostic (IMON/ bits, STTUS 2 register) characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit I TH Minimum current diagnostic threshold EN_IMON = (V OUT is set to 2 V typ.) m If the output current is lower than the min. threshold limit, the IMON I²C bit is set to. If the output current is higher than the max. threshold limit, the IMON I²C bit is set to. Refer to Section 5 Typical application circuits, T J from to 85 C, all DT..4 register bits set to except VSEL =, TEN=, RSEL = kω, DSQIN = HIGH, V IN = 2 V, I OUT = 5 m, unless otherwise stated. Typical values are referred to T J = 25 C. V OUT = V OUT pin voltage. Table khz tone diagnostic (TMON/ bit, STTUS 2 register) characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit THL mplitude diagnostic low threshold DETIN pin C coupled mv THH mplitude diagnostic high threshold DETIN pin C coupled 9 2 mv F THL Frequency diagnostic low thresholds DETIN pin C coupled khz F THH Frequency diagnostic high thresholds DETIN pin C coupled khz Note: If 22 khz tone parameters are lower or higher than the above limits, the TMON I²C bit is set to. DS8975 Rev 5 page 26/35