FIELD programmable gate arrays (FPGA s) are widely

Transcription

1 276 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 2, JUNE 1998 Testing Configurable LUT-Based FPGA s Wei Kang Huang, Fred J. Meyer, Member, IEEE, Xiao-Tao Chen, and Fabrizio Lombardi, Member, IEEE Abstract We present a new technique for testing field programmable gate arrays (FPGA s) based on look-up tables (LUT s). We consider a generalized structure for the basic FPGA logic element (cell); it includes devices such as LUT s, sequential elements (flip-flops), multiplexers and control circuitry. We use a hybrid fault model for these devices. The model is based on a physical as well as a behavioral characterization. This permits detection of all single faults (either stuck-at or functional) and some multiple faults using repeated FPGA reprogramming. We show that different arrangements of disjoint one-dimensional (1-D) cell arrays with cascaded horizontal connections and common vertical input lines provide a good logic testing regimen. The testing time is independent of the number of cells in the array (C-testability). We define new conditions for C-testability of programmable/reconfigurable arrays. These conditions do not suffer from limited I/O pins. Cell configuration affects the controllability/observability of the iterative array. We apply the approach to various Xilinx FPGA families and compare it to prior work. Index Terms C-testability, field programmable gate array, programmability, reconfigurability, testing. Horizontal Vertical Phase Session C-testable I. NOTATION AND DEFINITIONS The internal inputs (outputs) of an iterative array. These propagate dependency between the CLB s in the array. The external inputs of an iterative array. These can be directly specified in the test patterns and require I/O blocks. Each testing phase is a reprogramming of the FPGA followed by test vector application. Since reprogramming is slow, the number of phases is a good measure of testing time. The application of every CLB test configuration to those CLB s that are under test. Multiple sessions are required if not all CLB s can be under test simultaneously. An FPGA is C-testable with a given testing method if the number of programmings is independent of the circuit size. In particular, for an iterative array, it is independent of the length of the array. The number of primary inputs to a CLB. Manuscript received March 15, 1997; revised July 1, This work was supported in part by the State of Texas Advanced Research Program. W. K. Huang is with the Department of Electronic Engineering, Fudan University, Shanghai, China. F. J. Meyer and F. Lombardi are with the Department of Computer Science, Texas A&M University, College Station TX USA. X.-T. Chen is with FPGA Software Core Group, Lucent Technologies, Allentown, PA USA. Publisher Item Identifier S (98) The number of primary outputs of a CLB. The number of columns in the grid of CLB s. The number of rows in the grid of CLB s. The number of CLB s The number of I/O blocks. For a given test method and FPGA family, the number of configurations needed to test a single CLB. The part of due to the combinational partition of the CLB. The part of due to the sequential partition of the CLB. For a given method, the total phases needed for the specified FPGA family FPGA. For a given test method and FPGA family, the number of test patterns needed to test a single CLB. The part of due to the combinational partition of the CLB. The part of due to the sequential partition. For a given test method, for the specified FPGA family FPGA (plus any extra clock cycles needed to get the CLB response to chip I/O). For a given FPGA, the number of sessions needed by the BIST method [7]. For a given FPGA, the number of sessions needed by the naive method [5]. The regeneration period of a given iterative array. (The number of CLB s traversed before the input, output, and CLB configurations begin to repeat.) The number of vertical (external) inputs to each CLB in a given iterative array. The number of iterative array vertical inputs that differ for each CLB in one period. In the degenerate case of period 1, II. INTRODUCTION FIELD programmable gate arrays (FPGA s) are widely used for rapid prototyping and manufacturing of complex digital systems, such as microprocessors and high-speed telecommunication chips [1]. FPGA s are commercially available from many vendors. Our prototypical FPGA is a twodimensional (2-D) grid of configurable logic blocks (CLB s). The CLB s can be programmed to implement combinational as well as sequential logic functions [1] and each CLB is identical before programming. CLB s are separated by a programmable interconnection network; the interconnect consists of either programmable connector and/or switching blocks [2], or a series of horizontal/vertical routing tracks /98$ IEEE

2 HUANG et al.: TESTING CONFIGURABLE LUT-BASED FPGA S 277 and segments with programmable devices. Customization is accomplished by configuring the interconnect and the CLB s by loading them with appropriate data from an external storage device. The FPGA also includes input/output blocks (IOB s), which provide the interface between the package pins and the internal logic. The numbers of CLB s and IOB s vary widely depending on the particular chip and manufacturer [2]. FPGA s are versatile and in widespread use, due to their programmable nature and their ease of reconfiguration [3]. Internal static configuration (memory) elements determine the logic functions and the interconnections. The SRAM in memory-based FPGA s can be used to configure functions via look-up tables (LUT s). Also, they often have a mode where the configuration SRAM is usable as memory. We focus on CLB testing for SRAM-based FPGA s that implement functions via LUT s. Fig. 1. One programming phase with the naive testing method. III. BACKGROUND Testing FPGA s is addressed in the literature such as [4] [7]. These works and this paper deal with manufacturing test. Other tests in the field, such as verifying correctly loaded configuration data, are typically handled by architectural features for reprogrammable FPGA s [2]. Reference [4] discusses testing of row-based (segmented channel) FPGA s. The approach sequentially tests every cell using a modified scan procedure, providing 100% fault coverage of single stuck-at faults. It requires many tests and does not fully exploit the regularity of the FPGA to reduce test time. The methodology in [8] for testing uncommitted segmented channel FPGA s for single stuck-at faults is based on connecting the cells of each row as a one-dimensional (1-D) unilateral array, such that the FPGA could be tested as a set of disjoint arrays. This yields considerable reduction in both vectors and test circuitry. Simultaneous testing of disjoint arrays helps achieve constant test set size (C-testability), so that test cost will be independent of chip size [9]. In [7], the FPGA is configured to conduct direct output comparisons of pairs of logic cells using full cell controllability. Test generation and output response comparison are handled internally using some of the logic resources in a builtin self-test (BIST) arrangement. This requires at least one extra session, i.e., a doubling of chip programmings so that the cells previously used for test pattern generation and for output comparisons can become cells under test. Fault simulation established that 100% fault coverage can be accomplished for single stuck-at faults. In [10], the logic resources are arranged as an iterative logic array (ILA) [9]. This allows better scalability than the previous BIST arrangement [7]; however, it also requires another additional session i.e., a tripling of chip programmings. A simple testing arrangement (referred to as naive ) was mentioned in [5]. It connects together all input lines to the CLB s (cells) under test from the IOB s, and uses the remaining IOB s for direct observability of the output lines of each cell under test. Fig. 1 shows a single programming phase with the three leftmost CLB s under test. Each CLB Fig. 2. Interior of a Xilinx XC5200 CLB. in the figure has three inputs and two outputs. Three IOB s are consumed in order to provide the cells under test with their input vectors. The cells under test have no connections between them. Their output response is directly observed at the IOB s. In each programming phase, only a few CLB s can be tested in parallel. This is basically restricted by the number of IOB s and the number of output lines of each CLB. In Fig. 1, only three CLB s can be under test, because, after three IOB s are used for CLB inputs, only seven IOB s remain to observe output response. IV. PROPOSED FAULT MODEL Fig. 2 shows a portion of a Xilinx XC5200 CLB. A full CLB consists of four stacked copies of the figure (with the carry in (CI) and carry out (CO) signals rippled through) plus a little extra logic. The portion in Fig. 2 has a single LUT with four inputs, so it has 2 4 configuration bits to specify its function. Of the three multiplexers, M1 is a conventional multiplexer. M2 and M3 are programmable multiplexers; each needs only a single configuration bit to specify which input it passes. There is also a D flip-flop. Our generalized internal CLB structure permits these devices: LUT s, programmable (configurable) multiplexers, conventional multiplexers, and flip-flops. Some conventional logic usually does not interfere with test generation. We assume the interconnect and the IOB s have already been tested; the interested reader should refer to [11] and [12] for a detailed treatment. In our proposed testing strategy, we

3 278 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 2, JUNE 1998 divide CLB s into independent sets (linear arrays). For our fault model, within each linear array, we assume at most one faulty CLB; otherwise, fault masking might occur. For the single faulty CLB, the nature of the fault could take any form. For simplicity of illustration, in our investigation, we limited a CLB to a single faulty device. The nature of a device fault varies with the device. We model single device faults both physically (e.g., stuckat) and functionally [13]. This hybrid fault model is adaptable to emerging FPGA technology and to different products as they become commercially available [2]. The fault model was shown suitable to FPGA s in [5] and confirmed by industrial experiments. In particular, by device as follows. For a LUT, a fault can occur in any one of the: memory matrix, decoders, and input and output lines. A faulty memory matrix makes some memory cells incapable of storing the correct logic value (the LUT has a single bit output, so this value is either 0 or 1) [2]. Any number of memory cells in the LUT could be faulty. If the fault is in the decoder, the erroneous address leads to reading the contents of the wrong cell, i.e., a one-bit address fault. The third possible LUT fault is on the I/O lines, with respect to which we allow any single stuck-at fault. The one-bit decoder address fault can be collapsed to the stuck-at fault of a LUT input line. So this fault type is detected when the decoders are tested. A stuck-at fault on a LUT output line is covered by the tests for the LUT memory matrix. For a multiplexer, we use a functional fault model, because the internal logic structure varies from FPGA to FPGA [2]. Testing confirms the multiplexer s ability to select each input. For the D flip-flops, we use a functional fault model. A fault can cause a flip-flop to receive no data, to be unable to be triggered by the correct clock edge, or to be unable to be set or reset. Our testing objectives are as follows: a 100% fault coverage under a single faulty device model with neither delay nor area overhead; ease of test pattern generation, because patterns are generated for a CLB, not the whole FPGA; efficient implementation of the testing process as measured by the amount of memory required to store the test instructions (configuration bits and test patterns); the number of programming phases must be as small as possible, because reprogramming time is much greater than test pattern application time [3]. V. TESTING A CLB We generate test patterns in two steps according to the CLB partitioning. Consider initially a CLB made of a single LUT. We can test the LUT memory matrix by reading all the memory bits in two phases. The programmed memory matrix contents in the second phase are complements of the first. The scenario is different for testing stuck-at faults at the LUT inputs. The LUT matrix contents must be arranged such that the boolean difference is one for the input to be tested; multiple patterns are required. Furthermore, each LUT output must be observable at a primary CLB output. So we require a sensitized path from the LUT output to a primary CLB output. By definition of the combinational partition, this can be achieved by configuring the multiplexers (or other devices) in the partition. We use a functional test for the multiplexers. Since a multiplexer selects from among all inputs, each data input must be active in at least one phase. Further, the functional test consists of applying logic 1 to the selected input while holding all others at logic 0, and a second test pattern with these logic values reversed. The multiplexer output must be observable from at least one primary CLB output. If a multiplexer is not simultaneously controllable/observable, additional phases could be required. We need at least phases to test a multiplexer with inputs. A multiplexer can be tested with a LUT (if connected); a possible way to accomplish this consists of choosing a memory matrix for the LUT that satisfies the multiplexer(s) testability conditions. In this way, test phases can be overlapped (reduced). A. Testing the Sequential Partition The sequential partition includes the D flip-flops as well as multiplexers and control circuits emanating from them or only observable through them. During test generation, we seek to overlap testing of programmable multiplexers with that of flip-flops. In some FPGA s, flip-flops are more complicated than the D type. In particular, the Xilinx XC4000 family [2] has D flipflops plus added logic that can be programmed to add set/reset capability. The S/R controllers are configurable to allow a set function, a reset function, or neither. For the XC4000, this requires three separate programming phases; however, testing of the S/R controllers can be overlapped with testing the flip-flops. 1) Testing the D Flip-Flops: We functionally test the D flip-flops. We test the input and hold function with the data sequence 010 (or 101) at D. Separate phases are required to test both rising and falling edge trigger mechanisms, if applicable. We can test the set (reset) function by applying the set (reset) signal after a flip-flop is in the 0 ( 1 ) state. The set/reset disable functions must also be tested if present, leading to another phase. To test the clock enable function, we use the five-vector sequence given in Fig. 3. Some functional tests can be overlapped to reduce the number of phases. We can possibly also overlap phases with those for multiplexers, depending on the sequential partition s structure. VI. PROPOSED TEST STRATEGY Fig. 4 shows a linear iterative array. There is a cascaded (horizontal) input reflecting the dependence of the cells in the iterative array, and test vector is obtained from the IOB s and applied to this input. Other (vertical) inputs to the cells are not shown, but are also obtained directly from the IOB s. The CLB s in the array are programmed to implement functions:, etc. The period of the array, is the

4 HUANG et al.: TESTING CONFIGURABLE LUT-BASED FPGA S 279 Fig. 3. Fig. 4. Testing the enable function. Iterative array with period three. number of cells we must traverse in order to repeat the cascaded input. We do not allow all test patterns; the test generation process must ensure the periodicity is satisfied as it searches the input space. In Fig. 4 it must ensure that. The programmed functions could all be different, but we will constrain them to be identical so, if we have then various cells see inputs and Speaking in terms of single-pattern (combinational) testing, we only need to concatenate and to the input vector (and schedule the corresponding vertical CLB inputs) and we will have every CLB experience test vector The test set can then be compacted by eliminating unnecessary patterns. For successful testing, faulty outputs must also propagate through the array. Again, the test pattern generation procedure must ensure that excited faults propagate [9]. Our proposed approach depends not only on the number of CLB inputs and outputs (compared with the number of IOB s), but also on the nature of the array under test (either combinational or sequential). The novelty of the approach comes from using different types of array configurations to test the CLB s. Initially, each CLB is divided into two partitions: a combinational partition (which includes those cell outputs (and their fan-in nodes) that are combinational functions of the cell inputs) and a sequential partition (which includes the remaining devices). We use the following strategy. For testing the combinational partition of each CLB along an FPGA row, we program a 1-D (combinational) array. Each LUT is loaded with values such that the iterative arrays form a C-testable system (constant test set size). Let there be independent iterative arrays with horizontal inputs, horizontal outputs, and vertical inputs. Then, we need IOB s for controllability/observability when For testing the CLB sequential partition, we program a 1-D (sequential) array and use the pipeline technique of [8]. To reduce the number of required IOB s, as many as possible vertical inputs are made common (i.e., they will have identical logic values when test vectors are applied). This is beneficial because, in a sequential array, the requirements of controllability and observability are far more stringent than for a combinational array of the same size [8], [9]. Let the number of vertical inputs with different logic values in the test process for the pipeline technique be. So, IOB s IOB s) are required for the primary horizontal inputs (outputs). IOB s are used as primary vertical inputs for the vertical inputs of the CLB s with different logic values during the test process and IOB s are used as primary common vertical inputs for those vertical inputs that do not need to be distinguished. The total required IOB s is then when. The issue of different possible arrangements for the CLB inputs in each 1-D array must be considered with respect to the number of IOB s and the number of programming phases. In [14], we give different testing arrangements that depend on the values of and and on whether the array is combinational or sequential. The implication of FPGA programmability is that the test patterns for a CLB can be applied in different phases. Also, in each phase different CLB input(s)/output(s) can be selected as horizontal. So the C-testable process is not static as in [8], [9]; for example, the regeneration period can be different in different phases. The definition of C-testability remains unaltered i.e., the number of phases is independent of the array size. VII. EVALUATION OF XILINX FPGA s We applied our array-based testing method to three FPGA families from Xilinx [2] the XC3000, XC4000, and XC5200. We use the XC5200 for examples. Further details are in [14]. We measure testing complexity with the following: the number of programming phases for testing a CLB is where denotes the number of programming phases for testing the combinational (sequential) partition; the number of patterns for testing the whole FPGA is where denotes the number of patterns for the combinational (sequential) partitions. For the XC4000, we omitted testing some logic in this study; specifically, logic to bypass the sequential outputs, RAM functionality of the LUT configuration memory, and some embedded logic to aid carry arithmetic. To test the combinational (sequential) logic module of a CLB, and and Hence, a CLB in an XC4000 FPGA requires a total of tests and phases. In each phase for testing the CLB sequential partition, we need additional clock cycles to deliver the response to the IOB s [8]. and hence, the total

5 280 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 2, JUNE 1998 TABLE I XC5200 TESTING Fig. 5. Block diagram of an XC5200 CLB. number of test patterns for the CLB sequential partitions is The total number of patterns to test the whole FPGA is the total number of phases is For the XC3000, we can test the two partitions using and phases; however, some data paths are shared between the partitions, so some phases can be combined, yielding a reduced total of [5]. The total number of tests is Again, the number of required phases for testing the whole FPGA is the same as that for testing a single CLB, so The configured arrays are sequential in 12 of the required 19 phases. For the combinational arrays, the number of vectors required in each phase is the same as for a single CLB. Using the sequential arrays in [8], we need additional cycles equal to the number of CLB s in an iterative array. Therefore, A. Example: The XC5200 FPGA Family An XC5200 CLB has four independent four-input LUT s, 14 multiplexers, and four D flip-flops (Fig. 5). This is a stack of four independent logic cells (LC s). Each LC in Fig. 2 contains one four-input LUT, three multiplexers, and one D flip-flop for a total of five independent inputs ( and ) and three outputs ( and ). Also, it has a input and output; the of an LC connects to the of the next LC. In an LC, the LUT output can be configured as a CLB output and/or drive the flip-flop D input. The dotted lines in Fig. 5 show the extra logic mentioned earlier, which is not symmetrical; in the extra logic, controls a MUX so that two LC s can realize a five-input function. LC2/3 are identical to LC0/1 in Fig. 5. We partition each LC into a combinational partition and a sequential partition, as shown in Fig. 2. The combina- tional partition consists of the LUT and the multiplexers and while the sequential partition consists of the D flip-flop and the multiplexer The combinational partition has six inputs ( and ) and three outputs ( and ), while the sequential partition has five inputs and the two inputs to and one output. The input and output of an LC are not independent within a CLB. and are common inputs to all four LC s. s inputs are not independent. Table I shows the tested functions and number of test patterns required for each phase. Of eight phases, only two are needed for the sequential partition. In each phase the inputs of each LC are held identical. So only four signals are needed to furnish these inputs for an entire CLB. Also, we never use more than one output from each LC (four per CLB). The XC5200 family is rich in I/O blocks, so four outputs are easily observed. We now describe the configurations for each phase. Phase 1: This phase tests s ability to select in each LC. So, for the horizontal array connections, we cascade each to the in the same LC of the next CLB. This propagates any excited faults. For MUX functional test, we only need two patterns per MUX input, as mentioned earlier. In this case, however, these patterns are not achievable in LC0/2, because the MUX inputs are dependent. So we test s ability to distinguish from separate from its ability to distinguish from the extra logic (dotted line input in Fig. 5). We program the LC0/2 LUT s to implement XOR and the LC1/3 LUT s for XNOR. This makes it easy to get either 0 or 1 at any LUT output, so can be made opposite to. Also, with identical in each LC, the LUT outputs alternate between LCs; so, since controls the MUX in the extra logic, the extra logic will produce or its complement. For the first two patterns, we let the LC0 4 LUT s output (0, 1, 0, 1), which tests in LC1/3 and tests distinguishing from the extra logic in LC0/2. For the other two patterns, we let the LUT s output (1, 0, 1, 0), which tests in LC0/2 for distinguishing from Phase 2: This phase tests s ability to select Again, we cannot test everything simultaneously. So, we test LC0/2 separately from LC1/3. We let the LUT s output (0, 1, 0, 1) to test LC1/3. Two patterns are needed. Complementing the LUT outputs for the remaining two

6 HUANG et al.: TESTING CONFIGURABLE LUT-BASED FPGA S 281 patterns tests LC0/2. At the same time, we notice that we have tested s ability to select in every LC. When each LC is tested, in that LC. In the case of LC1 3, when tested, comes from for LC0 2. So, to propagate faulty outputs, we connect the horizontal outputs LC0 3 to the horizontal inputs LC0 LC1 and LC2 respectively. Phase 3: This phase tests s ability to select the extra logic in LC0/2. We let the LUT s output (0, 1, 0, 1). For LC0/2, then, This means we can connect as horizontal output to and excited faults will propagate. For the two patterns that test So we concatenate the patterns experienced by the CLB s in the array to get four patterns; however, eliminating redundant patterns leaves only two. In the process of testing we partially tested the MUX in the extra logic. We now let the LUT s output (1, 0, 1, 0), and apply two more test patterns to finish testing the extra logic (stuck-ats and MUX function). Phase 4: has only been tested for its ability to select so we now test it for selecting In this case, we program all LUT s for the 0 function. Also, to observe we program to select Each LC then implements We can now program the horizontal connections so that propagates to We make an exception for LC3 and connect (instead of to LC3 This allows us to also test for a stuck-at fault that does not affect LC3 (e.g., a stuck-open). Phases 5 and 6: We now test for stuck-at faults in the memory matrix. By programming the LUT s to implement XOR/XNOR functions, it is easy to propagate any excited faults by connecting horizontal output to (Again, but the concatenated test patterns are redundant.) Due to the XOR/XNOR functions, we also detect stuck-at faults together with their corresponding addressing faults. We are also detecting node stuck faults. We need two phases, because we need to program each memory cell for both 0 and 1. There are 16 memory cells in each LUT and we need to access each in both phases for a total of 32 test patterns; however, six of these have already been performed (two each in phases 2 4). Phase 7: In this sequential test phase we test s ability to select For complete control of we make select and program all LUT s for XOR. For the horizontal connection, we connect to We test most flip-flop functions in this phase. We also detect stuck faults. Phase 8: In this sequential test phase we test s ability to select the LUT. Again, we control by programming to select and all LUT s for XOR. Since follows the LUT output, we propagate errors by horizontally connecting to We also test flip-flop reset in this phase. By Table I, we require the whole FPGA, because patterns to test cycles are required for each of TABLE II PHASES AND TEST PATTERNS BY METHOD TABLE III NUMBER OF TEST SESSIONS IN BIST APPROACH sequential test phases for the response to appear at the array output. VIII. COMPARISON OF TESTING APPROACHES A. Test Sessions Required The proposed array-based technique can be compared with other methods, such as the naive approach of [5] and the BIST-based approach of [7], with respect to the number of programming phases. For fairness, we use the same fault model (from Section IV) for each method. For simplicity, for each approach we assume the same test configurations we obtained for the array-based approach. In actuality, this could be noticeably fewer for the naive approach and somewhat fewer for the BIST approach, because CLB output observability is superior. Note that all of these methods allow 100% coverage of the modeled faults. As shown in Table II, the naive approach needs test phases proportional to which is itself proportional to [14]. For the BIST approach [7], denotes the number of test sessions. In each session, different CLB s are under test. Comparing the formulae for and is equivalent in nature to must be at least two. It is typically three or more [7], but we note that is good for the Xilinx families studied, especially the XC3000. Table III gives for these Xilinx families. Not all the members of the Xilinx families studied herein were considered for the BIST approach [7]. The values of in Table III would be increased if the BIST-ILA configuration of [10] were used. For the array-based method, all CLB s are under test simultaneously, so the equivalent to and is 1 in Table II. B. Multiple Fault Detection A further point of comparison is the fault bound of an approach i.e., the maximum number of faults such that test invalidation (fault masking) cannot occur. We give as a range. The lower bound for is under worst case conditions. The upper bound can be achieved if the faulty CLB locations are favorable. We assume that test invalidation always occurs if the CLB locations permit it. is given as follows.

7 282 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 2, JUNE 1998 TABLE IV CLB ARCHITECTURAL COMPARISON Naive Approach. Every CLB is tested independently, hence BIST Approach. In each session, the CLB s are configured into disjoint groups: the test pattern generators, pairs of CLB s under test, and response comparators for each test pair. We conclude that (For the upper bound, we assumed that was barely achievable.) Array-Based Approach. We assume test invalidation occurs in a 1-D array if there is more than one faulty CLB. Since we configure the arrays along the rows of the FPGA, IX. ARCHITECTURES AND COMPARATIVE ANALYSIS We compare the Xilinx FPGA s in the series 3000, 4000, and 5200 with respect to their CLB structures and IOB limitations. We compare each CLB architecture by considering programmability and controllability/observability and the required programming phases. Further details are in [14]. A. Comparison of CLB Devices and Features Table IV gives the numbers of D flip-flops, LUT s, and programmable and conventional multiplexers together with the test patterns and programming phases needed by the arraybased method. It also gives the configuration memory size due to the flip-flops and programmable multiplexers. The difference between the XC3000 and XC4000 families is not large. The XC4000 has an extra 8-bit LUT connected in series with the other two LUT s. This partially affects controllability and observability; however, some of the required tests for the additional LUT can still be combined with the tests for the other two LUT s. We consider the R/S control elements equivalent to two MUX s each, so the XC4000 CLB has more programmable MUX s. Also, six MUX s have four inputs. Since the number of programming phases to test a MUX depends linearly on the number of MUX input lines [5], these need more phases (and test vectors) for the XC4000 compared to the XC3000. Two main XC5200 features contribute to its suitability to the array-based testing approach. First, it can be treated as four parallel simple logic cells (LC s) with little hassle. Like the XC4000 LUT s, internal signals are not independent (due to MUX and the extra logic). But these devices have adequate controllability, so testing the dependent logic only requires extra test patterns, not phases. The second fortunate XC5200 feature is its simple sequential structure. This leads to two sequential phases, cf. 12 (13) for the XC3000 (XC4000). The XC4000 has several programmable MUX s that are in the sequential partition, in addition to the programmable R/S logic. The XC3000 has TABLE V QUALITATIVE COMPARISON OF XILINX FPGA FAMILIES similar woes. Also, XC3000 sequential outputs feed back to its LUT s. That feedback must be tested sequentially, because the XC3000 flip-flops are always enabled. X. CONCLUSIONS We presented a new approach for testing LUT-based FPGA s by utilizing their reprogrammability. Under a hybrid (functional and/or stuck-at) single device fault model, we can test an FPGA by configuring the CLB s as 1-D arrays: the approach s novelty compared to previous work is that we use different array structures for different testing needs. This array-based technique takes into account the limited controllability/observability due to limited chip I/O. In testing with our approach we do not consider the actual application configurations; the whole FPGA is fully tested, confirming its programmability for all applications, and results in significant advantages, such as a unique testing regimen independent of how many applications there are and their specifics. It is suitable for manufacturing test and to serve as a universal power-on self-test. Our approach has no area/delay penalty cf. design for testability approaches. We analyzed the array-based technique with respect to the numbers of chip reprogrammings and test patterns needed. We demonstrated its applicability to three Xilinx FPGA families. We draw the following general conclusions. For our method, the number of chip programmings to fully test all logic blocks (CLB s) is the same as that to test a single CLB with perfect controllability/observability. With CLB s, given that there are I/O blocks, the number of clock cycles to apply the test vectors is Since chip programming time is typically at least equivalent to cycles, our method s testing time is essentially independent of FPGA size. With our approach, all CLB s can be under test simultaneously. This is possible with neither the naive approach [5] nor the BIST approach [7]. Table V compares Xilinx families and test methods. We use and to denote superiority and inferiority, respectively, while is neutral. So means fewer tests, fewer phases, more

8 HUANG et al.: TESTING CONFIGURABLE LUT-BASED FPGA S 283 IOB s cf. CLB outputs, and better CLB observability compared to other families. For a test method, means faster testing (fewer phases) for that family than with other methods. Our method uses only three different array layouts. I/O limitations were never a problem, despite studying FPGA s of various sizes and with various architectural features. We confirmed that the CLB architecture has a major impact on array test complexity. In particular, LUT s connected in series or programmable multiplexers with many inputs are two characteristics that lead to more chip programmings. As seen with the Xilinx XC5200, a large CLB can still be very efficiently tested due to the regularity of its internal organization and the simplicity of its sequential partition. For the naive and BIST approaches, a small number of I/O blocks adversely impacts testing time. Our approach is largely independent of I/O blocks, but can benefit only slightly from having many CLB outputs. ACKNOWLEDGMENT The authors would like to thank the reviewers for providing very detailed comments. [13] J. Gailaiy, Y. Crouzet, and M. Vergniault, Physical versus logic faults: Impact on their testability, IEEE Trans. Comput., vol. C-20, pp , June [14] W. K. Huang, [Online]. Available FTP: //ftp.cs.tamu.edu/pub/fmeyer/ reports/test/abstracts.html. Wei Kang Huang was born in Shanghai, China, in 1941 and graduated from the Department of Physics, Fudan University, Shanghai, China, in From 1985 to 1987, he was a Visiting Scholar at the University of Arizona, Tucson, and at the University of Colorado, Boulder. During the period from 1994 to 1996, he was a Postdoctoral Research Associate at the Department of Computer Science, Texas A&M University, College Station, where he pursued research in testing and fault tolerance of FPGA s. Currently, he is a Professor in the Department of Electronic Engineering, Fudan University. He is a Group Leader in the computer-aided design/computer-aided testing (CAD/CAT) area. His research interests include test generation and simulation, VLSI design, design for testability, and fault tolerance. Fred J. Meyer (M 95) received the B.Sc. (Hons.) degree in computer systems engineering and the Ph.D. degree from the University of Massachusetts, Amherst, in 1984 and 1991, respectively. He is a Research Associate in the Department of Computer Science at Texas A&M University, College Station. He was previously with the United States Air Force. His research interests are in distributed computer systems and algorithms, reliable and secure communication protocols, reliable system design and validation, and IC yield enhancement and assessment. REFERENCES [1] S. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic, Field Programmable Gate Arrays. Boston, MA: Kluwer Academic, [2] Programmable Gate Array Data Book, Xilinx, Inc., San Jose, CA, [3] B. K. Fawcett, Taking advantage of reconfigurable logic, in Proc. 2nd ACM Workshop on FPGA s, Berkeley, CA, [4] K. El-Ayat, R. Chan, C. L. Chan, and T. Speers, Array architecture for ATPG with 100% fault coverage, in Proc. IEEE Workshop on DFT in VLSI Systems, Hidden Valley, CA, 1991, pp [5] W. K. Huang and F. Lombardi, A general technique for testing FPGA s, in Proc. IEEE VLSI Test Symp., Princeton, NJ, May 1996, pp [6] W. K. Huang, F. J. Meyer, and F. Lombardi, Array-based testing of FPGAs: Architecture and complexity, in Proc. IEEE Conf. on Innovative Syst. Silicon, Austin, TX, 1996, pp [7] C. Stroud, P. Chen, S. Konala, and M. Abramovici, BIST of logic blocks in FPGA s, in Proc. IEEE VLSI Test Symp., Princeton, NJ, May 1996, pp [8] T. Liu, W. K. Huang, and F. Lombardi, Testing of uncustomized segmented channel FPGA s, in Proc. ACM Symp. FPGA s, 1995, pp [9] A. D. Friedman, Easily testable iterative arrays, IEEE Trans. Comput., vol. C 22, pp , [10] C. Stroud, E. Lee, S. Kanala, and M. Abramovici, Using ILA testing for BIST in FPGA s, in Proc. IEEE Int. Test Conf., 1996, pp [11] T. Liu, F. Lombardi, and J. Salinas, Diagnosis of interconnects and FPIC s using a structured walking 1 approach, in Proc. IEEE VLSI Test Symp., 1995, pp [12] C. Feng, W. K. Huang and F. Lombardi, A new diagnosis approach for short faults in interconnects, in Proc. IEEE Fault-Tol. Comput. Symp., Pasadena, CA, June 1995, pp Xiao-Tao Chen was born in Shanghai, China, on April 28, He received the B.S. and M.S. degrees in electronics engineering from Fudan University, Shanghai, China, and the Ph.D. degree in computer science from Texas A&M University, College Station, in 1985, 1991, and 1997, respectively. From 1985 to 1988, he was involved in data communication, and from 1991 to 1994, he was a faculty member at Fudan University. Since 1989, he has been working on computer-aided testing (ATPG and DFT), design verification, computer architecture, and algorithms. He is currently with Lucent Technologies, Allentown, PA, working on ORCA FPGA design and development. Fabrizio Lombardi (M 82) received the B.Sc. (Hons.) degree in electrical engineering from the University of Essex, U.K., in He received the Master s degree in microwave and modern optics, the Diploma in microwave engineering, and the Ph.D. degree from the University College London, U.K., in 1978, 1978, and 1982, respectively. In 1977, he joined the Microwave Research Unit at the University College London. Previously, he was with the University of Colorado, Boulder, and Texas Tech University, Lubbock. He is currently a Full Professor in the Department of Computer Science at Texas A&M University, College Station, where his research interests are in fault-tolerant computing, testing and design of digital systems, and parallel and distributed computer systems. Current topics under investigation include design and test of programmable digital systems (such as FPGA and FPIC), defect tolerance for IC manufacturing, mapping for parallel processing applications, testing of arrays, and protocol design and verification.