Mimosa32: Tower CIS October 2011 submission: 4 Metal, MiM Capacitor, Quadruple Well (deep-n and deep-p wells), HR epi

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1 3.3 Discri-per-pix 80x25 array 16x80 µm JTAG structure SPAD Mimosa32: Tower CIS October 2011 submission: 4 Metal, MiM Capacitor, Quadruple Well (deep-n and deep-p wells), HR epi - Overall chip dimension: 3.3x13 = 43 mm 2 - Diodes&amplifiers: 22 SF blocs for charge collection tests, 10 ampli blocs (block: 64rows x 16 columns), NMOS and PMOS based structures - Discriminators (two variety) equipped with 64 rows of pixels (4 variety of ampli?) - Novel discri-in-pixel structure ( frame readout time <10 µs) - Small blocs (LVDS I/O), novel ampli-shaper (AD-ts) - SPAD: CMOS SiPMs (InESS) Ramp generator Nwell diode 2x2 mm Diodes&Ampli: charge collection and radiation hardness study Discri (+pixels) 128 columns, two variety of discri Low power LVDS I/O AD-ts 1

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3 SF0 SF00 20x40 µm 1 Diode 20x40 µm 2 Diodes 20x80 µm 1 Diode 20x80 µm 2 Diodes Amp1 Amp10 SF1 SF2 SF16 Mimosa32: Diodes&Ampli area Basic block: 16 columns x 64 rows Basic pitch: 20x20 µm, except four structures (20x40 and 20x80 µm) 16 parallel analog outputs, 5 bit (static) address)to connect single block to the output bus. Basic diode size: 3x3 µm (except Deep_Nwell, half-pinned ) Integr. time 32 µs (&2 MHz) A0 A1 A15 5 bit array address A16 A17 A31 Analog_out bus (x16) 3

4 SF structures: - P1: Nwell (octo, ~10 µm 2 ), 2T_ll, ELT - P2: Nwell_1 (octo, ~10 µm 2 ), 3T_ll, ELT - P3: Nwell_2 (TOWER design, ~10 µm 2 ), 3T_ll, ELT - P4: Nwell_1 (octo, ~10 µm 2 ), 3T_ll, SF_lin - P5: Nwell_1 (octo, ~10 µm 2 ), 3T_ll, SF_lin, bias_lin - P6: Nwell_1 (octo, ~10 µm 2 ), 3T_NMOS, SF_lin, bias_lin - P7: Dnwell (sq, ~20 µm 2 ), 3T_ll, ELT - P8: Nwell_1 (octo, ~10 µm 2 ), DeepPwellSmall, 3T_ll, ELT - P9: Nwell_1 (octo, ~10 µm 2 ), DeepPwellMedium, 3T_ll, ELT - P10: Nwell_1 (octo, ~10 µm 2 ), DeepPwellLarge, 3T_ll, ELT - P11: Half_Pinned (~9 µm 2 ), 3T_ll, ELT - P12: Half_Pinned+Nwell (9 µm 2 ), 3T_ll, ELT - P13: Nwell_gated(3x3 µm), 3T_ELT_reset_ll P14: Nwell_3.3 (octo, ~10 µm 2 ), 2T_ll, ELT - P15: Half_Pinned (sq, ~15 µm 2 ), 3T_ll, ELT - P16: Half_Pinned+Nwell (sq, ~15 µm 2 ), 3T_ll, ELT - P0: Nwell (sq. ~9 µm 2 ), 2T_ll, ELT - P00: 32xNwell + 32xNwell_NS (sq. ~9 µm 2 ), 3T_ll, ELT - Pitch 20x40 µm, 1diode - Pitch 20x40 µm, 2diodes - Pitch 20x80 µm, 1diode - Pitch 20x80 µm, 2diodes Ampli structures (preliminary): - AD_ncmos - AD_ncmos_FELT - AD_nmos - AD_nmos_FELT - AD_pcmos - AD_pmos - YD_nmos2 - YD_nmos3 - YD_pmos_4 - YD_pmos_5 4

5 Diodes&Ampli area: SF pixels - 3T readout (2T like readout) - 2T readout Vdiode (Vclamp) Vdda Vdiode (Vclamp) Vdda Reset (or LineReset) plus Global Reset Pixel SF-3T Pixel SF-2T Pixel Array Periphery Gnd Select (or LineSelect) Gnd Select (or LineSelect) Iref Out (or ColumnOut) Iref Out (or ColumnOut) Gnd Gnd 5

6 Diodes&Ampli area: clamping pixels (amplifiers) Vclamp Vdda Clamp (LineClamp) Clamping Pixel CS Amplifier PowerOn (LinePowerOn) Pixel Array Periphery Gnd Select (or LineSelect) Iref Out (or ColumnOut) Gnd 6

7 Sync Clock In Mimosa32: SF pixel array steering (clock frequency : 2 MHz) Sync Clock In Reset, Clamp PowerOn PowerOn LSelect LReset, LClamp LSelect GReset Individual Pixel Array: 16 columns x 64 rows (lines) Out 64 bit Shift Register: two hot bits Out 64 bit Shift Register: one hot bit Analog_out bus (x16) 7

8 SF pixel array steering (clock frequency : 2 MHz) Self-bias mode (Grst=1, Lrst=0): 3T reset transistors in diode setting (permanently on ) Integration time (64 clok pules) First row Last row First row, next frame Clock Sync Out In Out may be shorted to In on the PCB

9 SF pixel array steering (clock frequency : <2 MHz) Line-reset mode (Grst=0,): 3T reset transistors activated during line addressing by Lrst pulse. Integration time (64 clok pules) First row Last row First row, next frame Clock Sync Example of CDS implementation using Lrst function Signal = Frame2-Frame1, Frame5-Frame4 etc. Frame «0» Frame «1» Frame «2» Frame «3» Frame «4» Frame «5» Lrst 9

10 Discriminators area 128 columns x 64 rows Two varieties of discri, four pixels types Basic pitch: 20x20 µm 16 parallel digital outputs 3 bit (static) address to connect single block to the output bus Integration time: down to 10 µs Ampli1 Ampli2 Ampli3 Ampli4 DsA DsB DsA DsB DsA DsB DsA DsB Digital_Out (x16) 10

11 Sync Clock In Mimosa32: Ampli pixel array & discriminator steering (clock frequency : 100/16 MHz) Sync Clock In Reset, Clamp PowerOn PowerOn LSelect LReset, LClamp LSelect Individual Pixel Array: 16 columns x 64 rows (lines) Out Out Read, Calib, Latch 16 Column Discriminators 64 bit Shift Register: two hot bits 64 bit Shift Register: one hot bit Digital_out bus (x16) 11

12 Pixel (Ampli&Discri) array steering (clock frequency : 100/16 = 6.25 MHz) Integration time (64 clok pules) First row Last row First row, next frame Clock Sync Out (Pout) In (Pin) Out (Pout) may be shorted to In (Pin) on the PCB 12

13 Sensor steering signals: Ampli+Discri example Sequence corresponding to one (array) Clock Cycle (derived from 16 pulses of 100 MHz master clock) f CK =100 MHz PWRON Sel_Pix Clamp RD ( 1) Version 1 CALIB ( 2) LATCH 160 ns f CK =100 MHz PWRON Sel_Pix Clamp RD ( 1) Version 2 CALIB ( 2) LATCH 160 ns

14 Sensor steering signals Power Analog Ref Array Address: static Digital Inputs Outputs (A&D) DAQ sync Outputs 14

15 Reference Analog Voltage Settings Definition Typical value from simulations Dynamic Range Resolution Iref (VLN) Column load transistor bias of pixels ~50 µa µa ~5 µa Vclp Clamping voltage of pixels ~1.2 V V 50 mv Vref1 Threshold value Vref2±30 mv 0.5 mv Vref2 Threshold common mode value of ~572.5 mv mv 5 mv discris. Vclp_discri Clamping voltage of discriminators ~975 mv mv 25 mv Vb1 Discriminators gain stage bias ~481.5 mv (to give 10 µa) mv 10 mv Vb2 Discriminators buffer stage bias ~438.5 mv (to give 5 µa) mv 10 mv All Analog Voltage Settings controlled by I 2 C DACs (or manual potentiometers) on AuxPCBs In addition: Vref (analog buffers baseline on ProxPCB_A, V) and Vcommon (Common Baseline Voltage on AuxPCB_A, only manual setting ~0V) 15

16 Annexe 16

17 Design status: back from fabrication! Tests preparation in progress 17

18 DAQ_ANALOG Mimosa32: Test PCB s design concept DAQ_DIGITAL DAQ_D DAQ_A CLK_A MK_SYNC_A 18

19 M32 tests goals ENC - Charge collection efficiency - Leakage current - Noise ENC -. - Irradiations (ionizing dose and equivalent neutron flux) -. - Tracking performance (S/N, efficiency, spatial resolution) M32 tests procedure - Correlated double sampling (digital or analog): NO diode reset between two consecutive frame readouts) - Signal = Frame2 Frame1-55 Fe photon spectrum (5.9 kev 1640 electrons): seed pixel, clustersation 55 Fe Spectrum example (M18) 19