STV6412A AUDIO/VIDEO SWITCH MATRIX

Transcription

1 STV642A AUDIO/VIDEO SWITCH MATRI FEATURES I ² C Bus Control Standby Mode with Interrupt Signal Output Video Section 4 CVBS Inputs, 3 CVBS Outputs (one with Selectable Chroma Trap Filter) 3 Y/C Inputs, 2 Y/C Outputs 6 db Gain on all CVBS/Y and C Outputs Integrated 5 Ω Buffers Y/C Adder 2 RGB/FB Inputs, Tri-state RGB/FB Output with 6 db Adjustable Gain (from +3dB to +9dB) Video Muting on all Outputs 2 Slow Blanking Inputs/Outputs Sync Bottom Clamp on all CVBS/Yand RGB Inputs, Average Clamp on C Inputs Bandwidth: 5 MHz Crosstalk: 5 db Minimum Audio Section 4 Stereo Inputs, 3 Stereo Outputs Mono-Sound Output Stereo-to-Mono Sound Capability /6/9 db Selectable Gain on one Stereo Input Full Range Volume Control with Soft Control Audio Muting on all Outputs TQFP64 (4 x 4 x.4 mm) (Thin Full Plastic Quad Flat Pack) ORDER CODE: STV642ADT DESCRIPTION The STV642A is a highly integrated I ² C bus-controlled audio and video switch matrix, optimized for use in digital set-top box applications. It provides all the audio and video routings required in a full two SCART set-top box design. September 23 /24

2 Table of Contents GENERAL OVERVIEW PIN CONNECTIONS ELECTRICAL CHARACTERISTICS ABSOLUTE MAIMUM RATINGS Thermal Data Latch Up RECOMMENDED OPERATING CONDITIONS AUDIO SECTION CHARACTERISTICS VIDEO SECTION CHARACTERISTICS CHROMA SECTION CHARACTERISTICS BLANKING SECTION I²C BUS CHARACTERISTICS I 2 C BUS SELECTION I 2 C BUS ADDRESSES POWER-ON RESET BUS REGISTER INITIAL CONDITIONS INPUT/OUTPUT GROUPS APPLICATION DIAGRAM PACKAGE MECHANICAL DATA /24

3 STV642A GENERAL OVERVIEW. PIN CONNECTIONS Figure. Pinout Diagram LOUT_TV FILTER AOUT_RF VOUT_RF VccB 5 BOUT_TV VccB 4 GOUT_TV GNDB R/COUT_TV VccB 3 Y/CVBSOUT_TV VccB 2 COUT_VCR VccB Y/CVBSOUT_VCR FBOUT_TV FBIN_VCR FBIN_ENC C_GATE VDD ADD SCL SDA GND IT_OUT SLB_TV R/CIN_VCR SLB_VCR GIN_VCR Vcc2 BIN_VCR ROUT_TV Vccao LOUT_VCR ROUT_VCR LOUT_CINCH ROUT_CINCH NC GNDA VccA RIN_TV LIN_TV CVBSIN_TV RIN_VCR LIN_VCR Y/CVBSIN_VCR GND DECA NC BIN_ENC LIN_ENC GIN_ENC RIN_ENC R/CIN_ENC LIN_AU CIN_ENC RIN_AU YIN_ENC GND Y/CVBSIN_ENC DECV CVBSIN_AU Vcc Figure 2. Pin Description Pin No. Symbol Description V CC +5 V Supply 2 CVBSIN_AU CVBS Input from Auxiliary 3 DECV Video Decoupling Capacitor 4 Y/CVBSIN_ENC Y/CVBS Input from Encoder 5 GND Ground 6 YIN_ENC Y Input from Encoder 7 RIN_AU Audio Right Input from Auxiliary 8 CIN_ENC Chroma Input from Encoder 9 LIN_AU Audio Left, Input from Auxiliary R/CIN_ENC Red/Chroma Input from Encoder RIN_ENC Audio Right, Input from Encoder 2 GIN_ENC Green Input from Encoder 3 LIN_ENC Audio Left, Input from Encoder 4 BIN_ENC Blue Input from Encoder 5 NC Not Connected 6 DECA Audio Decoupling Capacitor 7 GND Ground 8 Y/CVBSIN_VCR Y/CVBS Input from VCR SCART 9 LIN_VCR Audio Left, Input from VCR SCART 3/24

4 STV642A Pin No. Symbol Description 2 RIN_VCR Audio Right, Input from VCR SCART 2 CVBSIN_TV CVBS Input from TV SCART 22 LIN_TV Audio Left, Input from TV SCART 23 RIN_TV Audio Right, Input from TV SCART 24 V CCA Audio Supply Voltage - or - Audio Supply Decoupling 25 GNDA Audio Ground 26 NC Not Connected 27 ROUT_CINCH Audio Right Output to Cinch 28 LOUT_CINCH Audio Left Output to Cinch 29 ROUT_VCR Audio Right Output to VCR SCART 3 LOUT_VCR Audio Left Output to VCR SCART 3 V CCAO Audio Output Supply Voltage - or - Main Audio Supply Voltage 32 ROUT_TV Audio Right Output to TV SCART 33 LOUT_TV Audio Left Output to TV SCART 34 FILTER Chroma Trap Filter 35 AOUT_RF Audio (L+R) Output to RF Modulator 36 VOUT_RF CVBS Video Output to RF Modulator 37 V CCB5 Video Output Buffer Supply Pin 38 BOUT_TV Blue Output to TV SCART 39 V CCB4 Video Output Buffer Supply Pin 4 GOUT_TV Green Output to TV SCART 4 GNDB Video Buffer Ground 42 R/COUT_TV Red/Chroma Output to TV SCART 43 V CCB3 Video Output Buffer Supply Pin 44 Y/CVBSOUT_TV Y/CVBS Output to TV SCART 45 V CCB2 Video Output Buffer Supply Pin 46 COUT_VCR Chroma Output to VCR SCART 47 V CCB Video Output Buffer Supply Pin 48 Y/CVBSOUT_VCR Y/CVBS Output to VCR SCART 49 FBOUT_TV Fast Blanking Output to TV SCART 5 FBIN_VCR Fast Blanking Input from VCR SCART 5 FBIN_ENC Fast Blanking Input from Encoder 52 C_GATE External MOS Command for C_VCR bidirectional mode 53 V DD +5 V I 2 C Supply 54 ADD I 2 C Address Selection 55 SCL I 2 C Bus Clock 56 SDA I 2 C Bus Data 57 GND Ground Digital 58 IT_OUT Interrupt Output 59 SLB_TV Slow Blanking Input/Output from TV SCART 6 R/CIN_VCR Red Input (or C Input) from VCR SCART 6 SLB_VCR Slow Blanking Input/Output from VCR SCART 62 GIN_VCR Green Input from VCR SCART 63 V CC2 +2 V Supply 64 BIN_VCR Blue Input from VCR SCART 4/24

5 STV642A Figure 3. STV642A Block Diagram FBIN_ENC FBIN_VCR BIN_ENC BIN_VCR GIN_ENC GIN_VCR R/CIN_ENC R/CIN_VCR CIN_ENC FBIN_ENC FBIN_VCR BIN_ENC BIN_VCR GIN_ENC GIN_VCR R/CIN_ENC R/CIN_VCR Mute Mute R/CIN_VCR CIN_ENC R/CIN_ENC Mute FB Switch RGB Switch 6 db 3 to 9 db 3 to 9 db 3 to 9 db FBOUT_TV BOUT_TV GOUT_TV R/COUT_TV CVBSIN_AU Y/CVBSIN_VCR YIN_ENC Y/CVBSIN_ENC CVBSIN_AU Y/CVBSIN_VCR YIN_ENC Y/CVBSIN_ENC Mute C Switch 6 db Y/CVBS Switch Mute Mute CIN_ENC R/CIN_ENC Mute 6 db VOUT_RF FILTER Y/CVBSOUT_TV C_GATE COUT_VCR CVBSIN_TV CVBSIN_AU CVBSIN_TV Y_ENC Y/CVBSIN_ENC Mute C Switch 6 db SLOW BLANK MONITOR INTERRUPT SIGNAL IT_OUT SLB_TV SLB_VCR Y/CVBSOUT_VCR Y/CVBS Switch LIN_AU LIN_ENC /6/9 db LIN_AU LIN_ENC LIN_TV RIN_AU RIN_ENC LOUT_VCR ROUT_VCR LIN_TV RIN_TV Mute /6 db ROUT_CINCH RIN_AU RIN_ENC /6/9 db VCR Switch /6 db LOUT_CINCH RIN_TV LIN_VCR LIN_AU LIN_ENC LIN_VCR LIN_TV RIN_AU RIN_ENC -62 db /6 db /6 db AOUT_RF LOUT_TV ROUT_TV RIN_VCR RIN_VCR RIN_TV Mute TV Switch -62 db /6 db I²C BUS DECODER ADD SDA SCL 5/24

6 STV642A Figure 4. Functional Block Diagram SCART TV R/C G B FAST BLANK CVBS AUDIO L AUDIO R CVBS/Y AUDIO L AUDIO R SLOW BLANK STV642A R, G, B, FB SWITCHES CVBS/Y SWITCHES AUDIO L AUDIO R R/C G B FAST BLANK CVBS/Y C AUDIO L AUDIO R Y CINCH OUTPUT ENCODER RF MOD AU MICRO CVBS AUDIO L+R CVBS AUDIO L AUDIO R INTERRUPT CHROMA SWITCHES AUDIO SWITCHES SLOW BLANK, I/O CONTROL R/C G B FAST BLANK CVBS/Y AUDIO L AUDIO R CVBS/Y C AUDIO L AUDIO R SLOW BLANK SCART2 VCR 6/24

7 STV642A 2 ELECTRICAL CHARACTERISTICS 2. Absolute Maximum Ratings Symbol Parameter Value Units V CC2 Supply voltage for: - Slow blanking sections 3.2 V V CCAO - Audio drivers 3.2 V V CCA - Internal Digital Audio parts V V DD - Digital parts 6 V V cc, V CCBi - Video sections 6 V V I Voltage at Pin I to GND: - Audio pins, V CCA V - Video pins, V CC or V CCBi V - Bus pins, 5.5 V - Slow blanking pins, V CC2 V V ESD Maximum ESD voltage allowed. pf capacitor discharged through.5 kω serial resistor (Human Body Model) ±4 kv T oper Operating Ambient Temperature, +7 C T stg Storage Temperature -2, +5 C 2.. Thermal Data Symbol Parameter Value Units R th(j-a) Junction-ambient Thermal Resistance (Maximum) 48 C/W 2..2 Latch Up At an ambiant temperature of 25 C, all pins meet the following specifications: I trigger = 2 ma or I trigger = 2 ma. Pin 58 (IT_OUT) does not meet this specification and the trigger current must be limited to - ma. 2.2 Recommended Operating Conditions T amb =25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. Table. Supply Voltages V DD Digital Supply Voltage V V CCAO Audio Operating Supply Voltage - Decoupling capacitor on V CCA.2 - Connected to V CCA 8.5 V CC Video Operating Supply Voltage V V CC2 Slow Blanking Control Supply Voltage V V V Table 2. Active Mode (All channels ON) I DD Digital Supply Current V DD = 5 V 4.5 ma I CCA Audio Supply Current V CCAO = 2 V, no load 9 5 ma 7/24

8 STV642A I CCV Total Video Supply Current (V CC +V CCB +V CCB2 +V CCB3 +V CCB4 +V CCB5 ) V CC = 5 V, no load 43 6 ma I CC2 2 V Supply Current V CC2 = 2 V SLB input mode SLB output mode, no load ma Table 3. Standby Mode (All channels OFF) I DD Digital Supply Current V DD = 5 V 4.5 ma I CCAstd Audio Supply Current V CCA = 2 V, no load 3 ma I CCVstd Total Video Supply Current V CC = 5 V ma 2.3 Audio Section Characteristics T amb = 25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. Table 4. Audio Section Characteristics SVR Supply Voltage Rejection V RIPPLE = 5m V RMS at f = Hz, Gain= db, DECA filter cap = 47 µf DECA filter cap = 22 µf SVRK Supply Voltage Rejection V RIPPLE = 5m V RMS at f = khz, Gain = db 7 8 db V INDC Input DC Level V CCA = 9 V V CCA/2 V V INAC Input Signal Amplitude 2 V RMS R IN Input Resistance 3 5 kω R INmatch Input Resistance Matching ±2 ± % F RANGE Flatness CS Bandwidth Spread of Gain in Audio Band Channel Separation, from audio inputs Between L & R of TV outputs -3 db,.5 V RMS, R LOAD = kω, Gain = db -.5 V RMS, 2 Hz to 2 khz, Gain = db V IN =.5V RMS, f = khz, on one input, R LOAD = kω, Gain = db db db 5 khz db Ci Channel Isolation from video inputs V IN = V pp, f = 5 khz, on one point 85 db V OUT Output DC Level V CCA = 9 V V CCA/2 V V OFF DC Offset Change Switching between inputs ±5 mv R OUT Output Resistance 6 2 W PHD ASN eni G Phase Difference S/N Ratio Equivalent RMS Input Voltage Noise db Gain f = khz, V RMS input on each input channel f = khz, V RMS input (gain = db) weighted CCIR quasi peak BW = 2 Hz, 2 khz Flat, Gain = db.5 V RMS, R LOAD = kω, Gain = db db db 3 deg. 7 db 5 µv db 8/24

9 STV642A G STEP Gain Step -62 db to +6 db ( see Figure 2) 2 db G MATCH Gain matching between different inputs of one output V IN =.5 V RMS, khz, Gain = db db G MATCH2 Gain matching between Left/Right outputs of one input channel V IN =.5 V RMS, khz, Gain = db db THD THD6 THD9 Total Harmonic Distortion ENC Input at db ENC Input at 6 db ENC Input at 9 db V OUT =.5 V RMS, khz, 8 khz % % % V CL Output Clipping Level THD =.2%, khz V RMS V R L Output Load Resistance IN = V RMS, THD =.3%, kω Gain = db Mute Mute Suppression V IN =.5 V RMS, on one point -9 db 2.4 Video Section Characteristics T amb =25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. Table 5. Video Section Characteristics V DCIN DC Input Level Bottom Synch Pulse 2 V I CLAMP Clamping Current at V DCIN -4 mv 2 ma I LEAK Input Leakage Current V IN = V DCIN + V µa C IN Input Capacitance 2 pf V IN Max Input Signal V CC = 5 V.5 V PP DYN Dynamic Output Signal V CC = 5 V 3 V PP BW Bandwidth at -3 db Y/CVBS V IN = V PP 2 5 MHz RGB V IN = V PP 2 5 MHz Y/C Mixer (on VOUT-RF) V IN = V PP, V INC = muted 8 MHz Flatness CTi CTo Spread of Gain in Video Band (5 khz - 5 MHz) Y/CVBS RGB Y/C Mixer (on VOUT-RF) Crosstalk Isolation between Input Channel Crosstalk Isolation between Output Channel V IN = V PP V IN = V PP V IN = V PP, V INC = muted V IN = V PP at f = 4.43 MHz, on one point V IN = V PP at f = 4.43 MHz, on one point, R LOAD = 5Ω +/-.5 +/-.5 +/-.5 db db db 6 db 5 db R OUT Output Resistance 5 Ω G RGB Gain at RGB outputs V IN = V pp, gain set to 6 db db G RGBM Gain matching between R, G, B V IN = V PP, gain set to 6 db db G RGBSTEP Step of Gain 3 db to 6 db db G YCVBS Gain on Y,/CVBS channels V IN = V PP db G YCVBSM Gain matching between Y, CVBS inputs V IN = V PP db 9/24

10 STV642A DC OUT DC Output Voltage Bottom sync pulse.6 V DC OUT RF RF Output Voltage Bottom sync pulse V DPHI Differential Phase V IN = V PP at f = 4.43 MHz 5 deg. DG Differential Gain V IN = V PP at f = 4.43 MHz 5 % V Mute Mute Suppression IN = V PP at f = 5 MHz on one -55 db point LNL Luminance non-linerarity.3 3 % VSN Video S/N Ratio Refer to Note 65 db Note : S/N = 2 log (V OUT Black to White =.7 V PP / V Noise (mv RMS ) weighted CCIR 567). 2.5 Chroma Section Characteristics T amb =25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. Table 6. Chroma Section Characteristics V DCIN DC Input Level 3 V R IN Input Resistance 3 5 kω C IN Input Capacitance 2 pf V IN Max Input Signal.5 V PP DYN Dynamic Output Signal 3 V PP DC OUT DC Output VCR Voltage 2.2 V CBW Chroma Bandwidth C IN = V PP at -3 db MHz CTi CTo Crosstalk Isolation between Input Channel Crosstalk Isolation between Output Channel V IN = V PP at f = 4.43 MHz, on one input V IN = V PP at f = 4.43 MHz, on one input, R LOAD = 5 Ω 55 db 5 db R OUT Output Resistance 5 W G OUTC Gain at OUTC V IN = V pp db G CM Gain matching between C inputs V IN = V PP db Mute Mute Suppression V IN = V PP at f = 4.43 MHz, on one input -55 db CToYdel Chroma to luma delay, source Y/C Pin other than VOUT_RF, V 4.43 MHz, 2 ns CToYdel Chroma to luma delay, source Y/C Pin VOUT_RF 2 ns 2.6 Blanking Section T amb =25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6 Ω, R LOUTA = kω, R GV = 5 Ω, R LOUTV = 5 Ω, unless otherwise specified. Table 7. Slow Blanking Section INPUT MODE SLBlow Input Low Level Threshold V SLBhigh Input High Level Threshold V /24

11 STV642A I IN Input Current 5 µa OUTPUT MODE SLBlow Output Low Level (int. TV).2.5 V SLBmed Output Medium Level (ext. 6/9) V SLBhigh Output High Level (ext. 4/3) 2 V Table 8. Fast Blanking Section INPUT MODE FBlow/high Input Low/High Level Threshold V I IN Input Current 2 µa OUTPUT MODE FB LOW Output Low Level.5 V R LOAD = 5 Ω FB HIGH Output High Level V FB DEL Fast Blanking RGB delay At 5% on digital RGB transients, at 2 V on FB rise transient, at V 5 ns on FB fall, C LOAD = pf maximum FB TRANS FB Transitions at FB output C LOAD = pf maximum Rise Time between % and 9% ns Fall Time between 9% and % ns Table 9. C_Gate Function Output C_GATE-H Pull-up Resistor Value to V CCB 2 kω C_GATE-L Output Low Level I IN = ma I IN = ma.3.7 V V Table. Interrupt Output (Refer to Note 2) IT-Leak High Level Leakage External pull-up to 5 V µa IT-Low Output Low Level (Active) I IN = ma I IN = ma.3.7 V V Table. Address Selection Input ADDsel_L Address Selection Low Level.2 V ADDsel_H Address Selection High Level 2.5 V DD V I LEAK Leakage Current µa Note 2: The interrupt is forced to a low level when a change is detected on slow blanking inputs. It can be used in Standby mode to wake up the microprocessor. It is released when the I 2 C bus register is read. /24

12 STV642A 2.7 I²C Bus Characteristics T amb = 25 C, V CCAO = 2 V, V CC = 5 V, V CC2 = 2 V, V DD = 5 V R GA = 6Ω, R LOUTA = kω, R GV = 5Ω, R LOUTV = 5Ω, unless otherwise specified. Table 2. I²C Bus Characteristics SCL V IL Low Level Input Voltage V V IH High Level Input Voltage V I LI Input Leakage Current V IN = to 5.5 V - µa SDA V IL Low Level Input Voltage V V IH High Level Input Voltage V I LI Input Leakage Current V IN = to 5.5 V - µa C I Input Capacitance pf t R Input Rise Time.5 V to 3 V µs t F Input Fall Time 3 V to.5 V 3 ns V OL Low Level Output Voltage I OL = 3 ma.4 V t F Output Fall Time 3 V to.5 V 25 ns C L Load Capacitance 4 pf TIMING t LOW Clock Low Period 4.7 µs t HIGH Clock High Period 4 µs t SU,DAT Data Setup Time 25 ns t HD,DAT Data Hold Time 34 ns t SU,STO Setup Time from Clock High to Stop 4 µs t BUF Start Setup Time following a Stop 4.7 µs t HD,STA Start Hold Time 4 µs t SU,STA Start Setup Time following Clock Low to High Transition 4.7 µs Note 3: The device can also operate at 4 khz and is capable of interfacing with +3.3 V or + 5 V logic levels. Figure 5. I ² C Bus Timing (start, stop) 2/24

13 STV642A 3 I 2 C BUS SELECTION Data transfers follow the usual I 2 C format; i.e. after the start condition (S), a 7-bit slave address is sent, followed by an eight-bit data direction bit (W). An 8-bit sub-address is sent to select a register, followed by an 8-bit data word to be included in the register. The IC s I 2 C bus decoder enables the automatic incrementation mode in write mode. String Format Write only mode (S = Start condition, P = Stop condition, A = Acknowledge) S SLAVE ADDRESS A SUB-ADDRESS A DATA A P Read only mode S SLAVE ADDRESS A DATA A P Slave Address Address A6 A5 A4 A3 A2 A A Value Auto Increment Mode S SLAVE AD- A SUB-ADDRESS A DATA A DATA A DATAn A P... DRESS Sub-Address Sub-Address + Sub-Address + N 3. I 2 C Bus Addresses Write Address:, Read Address: Address Selection Pin Grounded: =, write address = 94(hex), read address = 95(hex) Address Selection Pin to Supply: =, write address = 96(hex), read address = 97(hex) Table 3. Input Signal Summary (Write Mode) Reg Data Addr (Hex) d7 d6 d5 d4 d3 d2 d d AUDIO TV Stereo Mono VCR Stereo Mono VIDEO 2 VCR Chroma muted 3 RGB and FB Tri-state MISCELLANEOUS STB-BY Note 4: Unused data must be set to. TV /6 db TV Volume-62 db to db - 2 db steps Soft Volume Mode Not Used VCR Audio Switch Control VCR Video and Chroma Switch Control RGB Gain 4 IT Enable SLB Mode Not Used VCR-C Output Control 5 VCR Slow Blanking TV Slow Blanking 6 RF Outputs TV Outputs CINCH Outputs VCR Outputs CINCH Audio Gain TV Chroma muted RGB Switch Control VCR-C Gate Control TV/CINCH Audio Switch Control TV Video and Chroma Switch Control RF Trap Filter Control ENC Audio Input Gain /6/9 db AU Inputs TV Inputs Fast Blanking Mode/Input Selection RF Adder Control VCR R/C sub Clamp VCR Inputs TV R or C Output Selection ENC R/C sub Clamp ENC Inputs 3/24

14 STV642A Table 4. TV Audio Output Reg. Addr (Hex) Description Soft Volume Change Level Adjustment 6 db Extra Gain TV Stereo or Mono Mode Bits 5 Data d7 d6 d5 d4 d3 d2 d d Active Disabled Comments db -62 db (-2 db/step) db +6 db = Stereo = Mono Table 5. Audio Selection & VCR Audio Output Reg. Data Addr Description Bits (Hex) d7 d6 d5 d4 d3 d2 d d TV & CINCH Audio Output Selection CINCH Audio Gain VCR Audio Output Selection VCR Stereo or Mono Mode 3 2 Comments Muted Encoder L/R selected VCR L/R selected AU L/R selected TV L/R selected Not allowed Not allowed Not allowed db Follow TV Gain Muted Encoder L/R selected TV L/R selected AU L/R selected = Stereo = Mono 4/24

15 STV642A Table 6. TV & VCR Video Selection Reg. Addr (Hex) 2 Description TV Video Output Selection Bits 3 Data d7 d6 d5 d4 d3 d2 d d Table 7. RGB & Fast Blanking Outputs Reg. Data Addr Description Bits (Hex) d7 d6 d5 d4 d3 d2 d d 3 TV Chroma Output Control VCR Video Output Selection VCR Chroma Output Control 3 Fast Blanking Control 2 RGB Selection 2 RGB Gain 2 RGB and Fast Blanking Control Comments Y/CVBS muted & Chroma muted Y/CVBS_ENC & R/C_ENC Y_ENC & C_ENC Y/CVBS_VCR & R/C_VCR CVBS_AU & Chroma muted Not allowed Not allowed Not allowed Chroma defined by d2dd Chroma force to mute Y/CVBS muted & Chroma muted Y/CVBS_ENC & R/C_ENC Y_ENC & C_ENC CVBS_TV & Chroma muted CVBS_AU & Chroma muted Not allowed Not allowed Not allowed Chroma defined by d6d5d4 Chroma force to mute Comments FB forced to low level FB forced to high level FB from Encoder FB from VCR Muted RGB_ENC selected RGB_VCR selected Not allowed +6 db gain +5 db gain +4 db gain +3 db gain + db extra gain +3 db for weak input signals RGB and FB outputs high impedance state RGB and FB outputs active 5/24

16 STV642A Table 8. RF & Miscellaneous Control Reg. Addr (Hex) 4 Description Bits R/C TV Output Selection Data d7 d6 d5 d4 d3 d2 d d Table 9. Slow Blanking & Inputs Control Reg. Data Addr Description Bits (Hex) d7 d6 d5 d4 d3 d2 d d 5 RF Output: Adder control and chroma sub-carrier filter selection C_Gate Output Control C_VCR Output Control Slow Blanking Mode IT Enable Encoder R/Csub Clamp VCR R/Csub Clamp Encoder Input Level Adjustment Slow Blanking TV SCART Slow Blanking VCR SCART Comments Red signal selected Chroma signal selected CVBS to RF output Y + C to RF output Filter not active Filter active High level Low level Tri-state mode (high impedance) Active Normal Mode SLB TV is driven by SLB VCR No interrupt flag IT enable Comments Bottom level clamp Average level clamp Bottom level clamp Average level clamp db for normal audio inputs +6 db for weak audio inputs +9 db for weak audio inputs Input mode only Output < 2 V Output 6/9 format Output 4/3 format Input mode only Output < 2 V Output 6/9 format Output 4/3 format 6/24

17 STV642A Table 2. Standby Modes Reg. Addr Description (Hex) 6 ENC Inputs VCR Inputs TV Inputs AU Inputs VCR Outputs CINCH Outputs TV Outputs RFmod Outputs Bits Data d7 d6 d5 d4 d3 d2 d d Full Stop Table 2. Output Signals (Read Mode) Reg. Data Addr Description Bits (Hex) d7 d6 d5 d4 d3 d2 d d Slow Blanking TV SCART Slow Blanking VCR SCART Interrupt Flag 2 2 Inputs active Inputs disabled Inputs active Inputs disabled Inputs active Inputs disabled Inputs active Inputs disabled Comments Audio & Video Outputs ON Audio & Video Outputs OFF Audio & Video Outputs ON Audio & Video Outputs OFF Audio & Video Outputs ON Audio & Video Outputs OFF Audio & Video Outputs ON Audio & Video Outputs OFF Only I 2 C bus and slow blanking detection parts are supplied. Comments Input <2 V Input 6/9 format Input 4/3 format Input <2 V Input 6/9 format Input 4/3 format No change since read One change has been detected (refer to Note 5) Note 5: The Interrupt Flag will be cleared when this register is read. To prepare for a new interrupt, a must be re-written in the IT Enable bit (Reg. 4, d7). 3.2 Power-on Reset Bus Register Initial Conditions Power-on Reset is active when the supply V DD is less than 3.5 volts. Non-significant bits () are pre-set to. Reg. Data Addr Comments (Hex) d7 d6 d5 d4 d3 d2 d d Audio TV and Cinch outputs are in Stereo Mode, db Gain Adjustment. TV, Cinch and VCR audio outputs are muted. VCR output is in Stereo Mode. 2 VCR, TV and RFmod video outputs are muted. 3 Fast Blanking is forced to. RGB outputs are muted and in high impedance. 4 C_GATE is high. C_VCR is high impedance. 7/24

18 STV642A Reg. Addr (Hex) Data d7 d6 d5 d4 d3 d2 d d 5 Encoder and VCR R/Csub Bottom Level Clamp, RGB outputs 6 db Gain, and Slow Blanking parts are in read mode. 6 All internal blocks are ON. Figure 6. Volume Control Characteristics Comments ±.5 db 8 3 Step Number -36 ±.5 db + 2 db -62 db -.5 db 8/24

19 STV642A 4 INPUT/OUTPUT GROUPS Figure 7. Bottom Clamped Video Inputs (Pins 2, 4, 6, 2, 4, 8, 2, 62, 64) V CC 5V V CC 5V Figure. Average Clamped Video Inputs (Pin8) VCC 5 V I B VCC 5 V 2V + V D 25 kω 25 kω 3V 5 kω tri tri Figure 8. R/C Clamped Video Inputs (Pins, 6) Figure. Cgate Logical Output (Pin 52) V DD 5V V CCB 5V R/C inputs may be configured either as a bottom clamped input or as an average clamped input. In either case, the simplified input schematic is very close to one of the graphics shown above. 8 kω 5 ohms Figure 9. Fast Blanking Inputs (Pins 5, 5) V CCB 5V Figure 2. Fast Blanking Output (Pin 49) V CCB 5V V CCB 5V tri 9/24

20 STV642A Figure 3. Video Outputs (Pins 38, 4, 42, 44, 46, 48) V CC 5V V CCB, V Figure 6. Trap Filter (Pin 34) V CC 5V V CCB5 5V kω Ω ib Figure 4. Audio Inputs (Pins 7, 9, 3, 9, 2, 22, 23) V CCA 9V Figure 7. Audio Outputs (Pins 27, 28, 29, 3, 32, 33,35) V CCAO I2 V 5 kω V CC /2 6 W I B Figure 5. Slow Blanking I/O (Pins 59, 6) V CC 2 V Figure 8. Interrupt Output (Pin 58) V DD 5V Float V CC2 2 V kω 4 Ω 25 kω kω 55 kω 2/24

21 STV642A Figure 9. I 2 C Bus (SDA) (Pin 56) Figure 2. I²C Bus (SCL) (Pin 55) V DD 5V Float V DD 5V Float Acknowledge kω kω Figure 2. I 2 C Bus (ADD) (Pin 54) V DD 5V Float kω Figure 22. Power Supply Connection V CC B V CC B2 V CC B3 V CC B4 V CC B5 V CC A V CC A V CC V CC 2 V DD Float V V 2 V 5V GNDP GNDA GNDref GNDV GDD These symbols represent some huge diode and Zener-like components used for ESD protection of the device. They are not supposed to be paths for any current in normal operation mode. 2/24

22 STV642A 5 APPLICATION DIAGRAM Modulator 4.43MHzTrap STV642A For more details refer to STV642 Application Note. 22/24

23 STV642A 6 PACKAGE MECHANICAL DATA Figure Pins Thin Full Plastic Quad Flat Pack (TQFP) e , mm.4 inch SEATING PLANE A A A2 E3 E E B D3 32 D D c L L K,25 mm. inch GAGE PLANE Dimensions Millimeters Inches Min. Typ. Max. Min. Typ. Max. A.6.63 A A B C D D D e.8.35 E E E L L..39 K (Min.), 7 (Max.) 23/24

24 STV642A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 23 STMicroelectronics - All Rights Reserved. Purchase of I 2 C Components by STMicroelectronics conveys a license under the Philips I 2 C Patent. Rights to use these components in an I 2 C system is granted provided that the system conforms to the I 2 C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. 24/24