A Low-Power Time-Synchronization Processor With Symmetric Even/Odd Timer for Charge-Shared LCD Driving of 3DTV Active Shutter Glasses

Transcription

1 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 10, NO. 12, DECEMBER A Low-Power Time-Synchronization Processor With Symmetric Even/Odd Timer for Charge-Shared LCD Driving of 3DTV Active Shutter Glasses Daejin Park, Member, IEEE, TagGonKim, Senior Member, IEEE, and Jeonghun Cho, Member, IEEE Abstract The proposed sync-processor enables a fractional-order time-synchronization to generate an efficient lens shutter-control timing for the charge-shared LCD lens driving in the 3DTV active shutter glasses. This design implements a universal sync-edge tracer as a pre-processor to form the unit event of the wireless sync-packet, a fractional-order timer to measure the timing period for accurate synchronization of the stereo-vision, and charge-shared driver controlled by the proposed symmetric even/odd timer to provide an efficient charge equalization method. The proposed symmetric even/odd timer block sequentially generates the driver switching events by distributing the driver activation into four pins of the LCD active shutter lenses to reuse the pre-pumped charge of the charge-shared LCD driver, which is sequentially shared between four pins for LCD lens. The proposed sequential lens control by distributing the charge-sharing events also enables the reduction of the hardware size required for the counters and overflow comparators in the switching timer to generate the pulse width modulation (PWM) pulse waveform of the LCD lens control for time-sequential 3D stereo-vision. The implemented one-chip solution, which is applied with all of the proposed techniques to improve the previous work, reduces about 140 A of LCD lens driving current, which results in about 30% current reduction in total. This paper describes the system s architecture and the details of the proposed techniques, while also identifying the key concepts and functions. Index Terms Charge-pump circuit, charge-shared LCD driver, fractional-order circuit, low-power design, stereovision, time synchronization. I. INTRODUCTION T HE 3D vision technology has been one of important features in the flat panel LCD TV market. There are many ways to provide the 3D visual effect to implement the 3D home theater [1] [3]. Manuscript received December 22, 2013; revised April 14, 2014 and June 05, 2014; accepted July 10, Date of publication July 18, 2014; date of current version November 10, This work was supported by the BK21 Plus Project funded by the Ministry of Education, School of Electronics Engineering, Kyungpook National University, Korea, under Grant 21A and by the Ministry of Science, ICT & Future Planning, Korea, under the C-ITRC(Convergence Information Technology Research Center) support program NIPA-2014-H supervised by the National IT Industry Promotion Agency. (Corresponding author: Jeonghun Cho.) D. Park was with the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon , Korea. He is now with the School of Electronics Engineering, Kyungpook National University, Daegu , Korea ( daejin.park@kaist.ac.kr). T. G. Kim is with the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon , Korea ( tkim@ee. kaist.ac.kr). J. Cho is with the School of Electronics Engineering, Kyungpook National University, Daegu , Korea ( jcho@ee.knu.ac.kr). Color versions of one or more of the figures are available online at ieeexplore.ieee.org. Digital Object Identifier /JDT Fig. 1. Sync-pulse synchronization and LCD lens on/off timing generation for time-sequential 3D vision effect. (a) 3DTV active shutter glasses for time-sequential 3D vision effect. (b) On/off timing generation for LCD lens driving. The TV manufacturers have adopted the stereoscopic 3D vision technology as a commercialized technology. There are two types of approaches, which are active shutter glasses (SG) [4] [6] and film-type patterned retarder (FPR). Many electronic appliance companies of TV manufacturers use the shutter glasses 3D technology, even though it requires an expensive electronic system including the LCD lenses as active shutters powered by an on-board battery. The short operating lifetime of the 3DTV shutter glasses is one of major disadvantages by requiring the inconvenient battery charging. The more operating power consumed by 3DTV active shutter glasses, the more frequently a 3DTV user has to charge the battery. If low-power operation is powered by special techniques, it can also reduce the overall cost by lowering the capacity of the on-board battery. Fig. 1(a) shows a stereoscopic 3DTV system using the active shutter glasses. The emitter unit in 3DTV side continuously transmits the sync-packets with the wireless transmitter and the sync processor unit in the active shutter glasses receives the incoming sync packet to synchronize the switching time of the LCD lenses for 3D vision X 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See for more information.

2 1048 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 10, NO. 12, DECEMBER 2014 Fig. 1(b) illustrates the synchronization between 3D vision in TV side and the switching time of LCD lenses in the active shutter glasses. The 3DTV transfers the emitter-side time information for each sync period and the active shutter glasses reconstructs the time domain information in the glasses-side with more accurate resolution, which are described in Fig. 1(b). The time domain with the dotted box is expanded to describe the switching time of the LCD lenses, which is controlled by the reconstructed synchronization time. The switching operation of the LCD lenses enables the stereoscopic 3D vision from the left and right image, which is displayed on the left eye and right eye sequentially. The on/off switching operation of the LCD lenses requires the high voltage level (20 V) compared to the operating voltage (5 V) of the sync processor chip. The high voltage generation method based on the charge-pumping technique, which integrates the pre-charged voltage in the external capacitors, is widely used to generate the higher voltage than the operating voltage of the main chip. The existing approach reduces the power consumption in sync-packet analysis and noise-filtering by the digital signal processing method to perform the low-power synchronization between the 3DTV and active shutter glasses, but the major power consumption in the charge-pumping operation to generate the high voltage for the LCD lens switching still exists. Thecharge-pumpingoperationtoturnontheLCDlensfor each switching event requires inefficient power consumption. The charge-sharing technique in the charge-pumping operation to generate the high voltage provides an efficient way to share the pre-charged energy in the adjacent LCD pin. In this paper, we propose a power-efficient timer design technique to provide the low-power time-synchronization and shutter control timing reconstruction to provide the efficient charge-sharing method for the high-voltage, charge-pumped LCD driver in 3DTV active shutter glasses. This paper is organized as follows. In Section II, motivation and related works are discussed. Section III describes the details of the proposed techniques. Measurement results and some discussions are presented in Section IV. Finally, Section V concludes the paper. II. MOTIVATION AND RELATED WORK The charge-pump approach to generate the high voltage using the low voltage of the on-board battery utilizes the internal/external capacitor holding the pumped charge to step up sequentially from the pre-charged voltage. The circuit designer considers the charge-pump method as a cost-effective way to design the high voltage generator because the capacitor in CMOS process is easily implemented compared to the inductor. There are significant literatures on the charge-pump circuit designs [7] and many approaches are presented to enhance the power efficiency based on the current reuse approach such as charge-sharing technique [8]. The charge-shared timing control requires more complex control using the additional timer and comparator to determine the charge-sharing timing. Our approach adopts the advantage of the conventional charge-sharing technique to pump up the high voltage efficiently. To utilize the charge-sharing method in the 3DTV shutter glasses, four pins controlled by the proposed even/odd TABLE I DEFINITIONS OF NOTATIONS timer are assigned to the LCD lenses. The pin assignment between the charge pump driver and lenses is modified to generate the pulse width waveform with minimum edge events using the reduced timer and comparator block to perform the efficient charge-sharing operations. Using the proposed pulse control, the distribution of the charge-sharing operations, which are assigned to the all pins for the LCD lenses in space and in time, enables the control of the LCD driver pins with single linear timer and minimized comparators III. PROPOSED SYSTEM ARCHITECTURE In this section, the proposed system architecture and its operation are presented in detail. Table I lists the notations, which are used in this paper. A. Fractional-Order Timer for Shutter Timing Reconstruction The 3DTV transfers the sync-packets by the wireless signals or infrared radio (IR) signals, which have very long-term duty between the packets to reduce the communication overhead. Fig. 2 describes the reconstruction of the synchronization time from the received sync packet, which is transferred by the 3DTV side. The Traced Sync-Event waveform describes how to extract the duration of the fundamental synchronization time from the received external sync-packet, which is transferred from the emitter in the 3DTV. The Tracking (Freq, Phase) waveform describes how to represent the internal re-synchronization time information with the local clock in the sync processor of the active shutter glasses, which includes the time duration and phase information of with.the LCDDrive Timing Reconstruction waveform describes the reconstruction of the LCD lens control timing SI(n) from the adaptation result of with the phase information. The reconstructed is used as a unit to control the switching time of the LCD lenses, which is illustrated in the last of Fig. 2. The accurate timing generation using local clock requires a very high bits counter in the local timer block. The proposed fractional-order timer consists of the integer-level timer to divide the multiple timing sectors from the and fractional-

3 PARK et al.: LOW-POWER TIME-SYNCHRONIZATION PROCESSOR FOR CHARGE-SHARED LCD DRIVING 1049 Fig. 2. LCD drive timing reconstruction from sync-event generation by tracing the sync packets. level timer to measure the residue-part as phase error. The duration of external sync (SE) timing is simply measured using the timer and divided into the internal sync (SI) timing by the integer timer using the local clock in the 3DTV SG. The LCD control timing reconstruction is described in the following equation: The fractional error term is represented with the proposed fractional-order timer (FRT) block. Due to the two independently clocked systems in the 3DTV and SG, synchronization timing always evokes a fraction (residue) of the error described in (1). The FRT approach presents an effective way to compensate for the residue-part of the synchronization result [9], [10], which is implemented with a dedicated timer. This timer compensates for the fractional error in the synchronization by employing two independent parts of the timer. The following equations describe the data path of the proposed hardware block for the FRT to enable the measurement of sync duration in the fractional-order scale (1) - - (2) - (3) - where is the arrival time of SE and is the elapsed time re-synced from SE. stands for the number of sync pulses reconstructed during one period of the external sync-timing. The sync reconstruction performs frequency adaptation and phase adaptation to generate SI from SE - (4) (5) The current SI includes the long-term prediction, the phase error, and compensation part produced by the FRT The long-term prediction reflects the current SI(n) value, which is measured from the current arrived : The predicted sync timing SI(n) is accurately adjusted into the fractional-order scale represented by (3) and (4) (6) (7) (8) (9) Equation (8) shows that the next internal sync timing can be predicted by the current external sync timing and the resynchronization timing error, which is caused by the local clock. The dashed red line in Fig. 2 represents the predicted internal sync timing, which includes the phase error term caused by the long term prediction. The dashed red arrow in Fig. 2 represents the final internal sync timing including the phase error value, which is minimized by the adaptation block. The adaptation block minimizes the distance between the phase error and the resynchronization timing error, which is described in (9). From the result of the proposed fractional timer, the fractional-level timing reconstruction to control the LCD lens switching performs the accurate synchronization with the displayed 3D stereovision timing, which is illustrated in Fig. 2. The local timing generation using the digital timer instead of the analog-mixed circuit such as PLLs provide an efficient way in terms of the power consumption and hardware size. The reconstructed timing is used as a unit to control the LCD lens described in the next section.

4 1050 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 10, NO. 12, DECEMBER 2014 Fig. 3. Comparisonofconventional LCDdrivertimingandproposedcharge-sharedLCDdrivertimingusingdistributed-pumpingevents. (a) Conventional driver timing for 3DTV shutter glasses. (b) Proposed control timing for charge-shared LCD driving of 3DTV shutter glasses (pumping edge events are distributed in balance). B. Switching Edge Distribution The conventional LCD lens driver controls three pins of L, R and C as COM in Fig. 3(a). The voltage difference from the COM pin causes the lens to turn off from the light. The time-sequential LCD lenses switching for the stereovision is performed with the voltage level control of L, R, and C pins. The edge timing of the driving waveform is controlled by the unit timing, which was reconstructed by the FRT in the previous section. The pre-pumped voltage in the L pin can be reused to pump up the voltage in the R pin. Then stable high voltage in the R pin is also shared in the charge to generate the high voltage in the L pin. However, the C pin does not have an edge to reuse the pre-pumped charge by the control method in Fig. 3(a). Considering symmetric switching operations of the LCD lens, the edges to toggle the voltage are equally distributed into the four pins of L, LC, R, and RC to form the chain of the voltage up/down, which is illustrated in Fig. 3(b). The pre-pumped charge is shared to assist the high voltage generation in the charge-pump block, which the circular-chained charge sharing is performed from L to R, from R to LC, from LCtoRC,andfromRCtoL. The abstracted model of the proposed LCD lens switchingtiming control in Fig. 3(b) is described in Fig. 4 by illustrating the trajectory of the voltage transitions across the entire switching pins of the LCD lenses, which is represented in red line. As a result of the proposed edge distribution technique, there are always two switching edges as a pair of the voltage up/down per the lens pin channel, which is described in the notation. The number of the switching pins per phase window is always two times, which is represented with the notation. The red line shows the trajectory where the pumped charge is shared across the control pins for the LCD lenses. The blue line in Fig. 4 describes the counter value of the timer to determine the switching timing. The trajectory of the Fig. 4. Trajectory of shared-charge and timer counter by edge distribution. counter value without any overlapped region enables the simple hardware implementation to control the switching timing for the charge-sharing control with the single linear timer. C. Symmetric Even/Odd Timer Architecture The symmetric driving waveform for the LCD switching control, which is described in Fig. 3, enables the reduction of the timer and overflow comparators by utilizing the symmetric counter operation for two LCD lenses to implement the 3D stereovision by the 3DTV shutter glasses. Fig. 5(a) shows the proposed even/odd timer block, which is included in the sync processor for the 3DTV active shutter glasses. The control timer for the charge-shared LCD driver generates the PWM pulses. The charge-shared LCD driver generates the high-voltage waveform to drive the LCD lenses with the proposed control sequence for the charge-sharing method. The even/odd timer as a core block, which is used to control the charge-shared LCD driver, generates the PWM waveform into the LP of PMOS switch and the LN of NMOS switch for

5 PARK et al.: LOW-POWER TIME-SYNCHRONIZATION PROCESSOR FOR CHARGE-SHARED LCD DRIVING 1051 Fig. 5. Proposed sync processor architecture including even/odd timer for charge-shared LCD driver. (a) Proposed sync processor architecture including even/odd timer for charge-shared LCD driver. (b) Increasing counter (even timer). (c) Decreasing counter (odd timer). (d) Symmetric even-odd timer. left lens L in Fig. 3(b), which is previously described. In the same manner, the RP and RN are used for right lens R, the LCP and LCN are used for right lens COM LC pin, and the RCP and RCN are used for right lens COM RC pin. The equalization pins of,,,, which are used to redirect the charge-pumped voltage into another one, are assigned to indicate the charge-sharing timing for the charge-pumping block. The charge-sharing between LC pin and RC pin is activated by the equalization pin. The even/odd timer includes only a single linear timer, which is divided into the two counters of and. The even-phase,whichisafirst timing window in Fig. 4, is measured by the even overflow value using the m-bit comparator. The timer counter value in increases until, which is illustrated in Fig. 5(b). In the overflow timing at the end of, the charge in the LC pin is shared to assist the charge-pumping in the RC pininfig.3(b). The second step of the timer counter operation starts from the upper side value of the timer by shifting right, which results in zero ground transition effect. (10) The phase measures the charge-sharing timing by using only the reduced bit counter value and determines the overflow using bit comparator. (11) (12) The (12) describes the maximum counter value for the event phase and timing window. The switching timing in the LC pin is determined by the counter value during the phase to generate the voltage waveform in the LC pin channel and then to perform the charge-sharing in the RC pin by reusing the reconstructed timing of the LC pin. The switching timing in the RC pin is determined by the counter value during the phase to generate the voltage waveform in the RC pin channel and then to perform the charge-sharing in the L pin by reusing the reconstructed timing of the RC pin. The phase starts from the pre-counted value of by decreasing the counter value until the over- crosses zero, which is described in Fig. 5(c). flow value (13) (14) The result of the up-counter operation is reused by the downcounter to measure the timing window for the phase and. The switching timing in the L pin is determined by decreasing the counter value of the during the phase to generate the voltage waveform in L pin channel and then perform the charge-sharing in the R pin by reusing the reconstructed timing of the L pin. The symmetric counter operation of the even/odd timer utilizes the characteristics of the symmetric LCD lens driving waveform to reduce the timer bits and number of counters with the reduced counter bit-width. Fig. 5(d) illustrates the even/odd operation of the counter in the circular ring style. The segmented phase timing enables the splitting of the counter value into the and to measure the timing window; only four comparators are needed to determine the time bound at the overflow value,,,and.

6 1052 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 10, NO. 12, DECEMBER 2014 Fig. 6. Event/odd timer using symmetric overflow control to share the timer counter and comparator. (a) Even/odd sync timing to control the equalization pulse generation. (b) Final LCD drive waveform to switch the LENS with charge-shared pumping method. The blue-colored circle in Fig. 5(d) shows that the counter is increasing to determine the timing of even phase and. The timing region between the end of and the start of is used as the temporary time to control the equalization pins of,,, to redirect the pre-charged voltage pin to the next shared pin. IV. IMPLEMENTATION AND EXPERIMENTAL RESULTS The proposed sync processor includes the functional features that are presented in the our previous works [9] [11]. In this work, the sync processor for 3DTV active shutter glasses is improved with the low-power operation in the LCD lenses driving mode with the efficient charge-sharing method using the symmetric even/odd timer. The charge-shared LCD driving, which is illustrated in Fig. 6(a), requires the complex switching time control by using conventional multiple linear timers, which are also implemented with more number of counter depths to control the switching time of LCD lenses independently during the four switching of each lens (Off-On-Off-On) in Fig. 6(b). The proposed symmetric even/odd timer architecture utilizes the symmetric switching property of LCD lenses in 3DTV active shutter glasses and implements the independent switching time for the charge-shared LCD driving with single linear timer block with oven/odd symmetric overflow comparators, which is described in the previous section. The proposed approach is applied to improve the result of our previous work [10] in terms of the power consumption of the entire chip, including the LCD lenses driving. Fig. 6(a) shows the result of the pins waveform for the chargeshared LCD driver based on the charge-pump high-voltage generator. The voltage transition edges of the pins L, LC, R, and RC are symmetrically distributed into all of the LCD pins according to the time advance. The symmetric distribution of the voltage transition edges enables the non-overlapped increase/decrease operation of the counter value, which is implemented with a single linear timer. The equalization control pulses to activate the charge-sharing operation at the specific time are sequentially triggered using the existing counter value, which is used for the even/odd timer for the timing of L, R, LC, and RC. The external pads, which are connected with LCD lenses for L, LC, R, and RC, drive the high voltage to switch the LCD lenses. The voltage difference between L and LC is biased on the left LCD lens. The voltage difference between R and RC is driven on the right LCD lens. The switch control of the left and right lenses by driving these voltage differences is described in Fig. 6(b). The high voltage generation is achieved by the chargepumping circuit by controlling the charge-sharing timing, which is synchronized with the equalization switch pulse. The proposed sync processor, including the proposed charge-shared LCD driver based on the even/odd timer, is fabricated using 0.18 m 2-poly 6-metal embedded-flash CMOS technology. Fig. 7(a) summarizes the chip s features and Fig. 7(b) shows its micro-graph. The 2.4 mm 2.3 mm

7 PARK et al.: LOW-POWER TIME-SYNCHRONIZATION PROCESSOR FOR CHARGE-SHARED LCD DRIVING 1053 Fig. 7. Chip feature and power reduction comparison. (a) Chip features. (b) Chip microphotograph. (c) Operating current comparison. chip area contains about 3,400 logic gates for the proposed even/odd timer. Fig. 7(c) shows the reduction of the current consumption by measuring the operating current of the 3DTV active shutter glasses in case of 120 Hz 3D vision play. Our previous works include the edge tracer [9] and the fractional-order timer and sync-less synchronization mode with sensor-off mode [10], by which the total current consumption is 470 A without any reduction in the LCD driving current. This work focus on the current consumption in the LCD driving block and reduces 140 A of the current consumption in the LCD driving block, which results in total 330 Acurrent consumption in running the 3DTV active shutter glasses with the small area overhead of the proposed symmetric even/odd timer architecture, which is about 30% current reduction comparedtoourpreviouswork. The proposed charge-sharing approach to drive the LCD lenses requires the intermediate region of the voltage transition during the charge equalization with adjacent LCD driving pins, which is illustrated with the red dotted lines in Fig. 6(b). The slow voltage transition on driving the LCD lenses may affect the 3D vision, which is displayed on the eyes of a 3DTV viewer, by causing the delay between the shutter switching time and the play time of the stereoscopic 3D image time at the TV screen. As a future work, a detailed study is required to consider the side effect caused by using the proposed charge-shared LCD driving. V. CONCLUSION The proposed sync-processor reduces the total current consumption including the charge-pumped high voltage driving for LCD lens of 3DTV active shutter glasses. The sync receiver, as a front-end timer that is based on the edge tracer and fractional-order time-synchronization block, performs the unit timing reconstruction for LCD lens driving. The dedicated timing controller as a second back-end timer is added to utilize the charge-sharing technique to reduce the operating current in the LCD lens driving. Although the complex charge-sharing timing control is needed for many switching pins in the charge-pumping-based driver, the proposed even/odd timer is implemented with a single linear timer counter by utilizing the symmetric switching characteristic of the LCD shutter operations. For the lenses switching in playing 120 Hz 3D vision, the average 140 A current is reduced in the LCD driver based on the charge-pumping circuit, and total 30% operating current reduction is achieved in entire sync processor chip for the 3DTV active shutter glasses. REFERENCES [1] W. Tam, F. Speranza, S. Yano, K. Shimono, and H. Ono, Stereoscopic 3DTV: Visual comfort, EEE Trans. Broadcast., vol. 57, no. 2, pp , Jun [2] P. Benzie, J. Watson, P. Surman, I. Rakkolainen, K. Hopf, H. Urey, V. Sainov, and C. von Kopylow, A survey of 3DTV displays: Techniques and technologies, IEEE Trans. Circuits Syst. Video Technol., vol. 17, no. 11, pp , Nov [3] N. Holliman, N. Dodgson, G. Favalora, and L. Pockett, Three-dimensional displays: A review and applications analysis, IEEE Trans. Broadcast., vol. 57, no. 2, pp , Jun [4] P. Tsang, Apparatus for three-dimensional display, U.S. Patent , Jan. 21, [5] B. Javidi and F. Okano, Three-Dimensional Television, Video and Display Technology, ser. Physics and Astronomy Online Library. Berlin, Germany: Springer, [6] A. Srivastava, J. de Bougrenet de la Tocnaye, and L. Dupont, Liquid crystal active glasses for 3D cinema, J. Display Technol., vol. 6, no. 10, pp , Oct [7] G. Palumbo, D. Pappalardo, and M. Gaibotti, Charge-pump circuits: Power-consumption optimization, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 49, no. 11, pp , Nov [8] C. Lauterbach, W. Weber, and D. Romer, Charge sharing concept and new clocking scheme for power efficiency and electromagnetic emission improvement of boosted charge pumps, IEEE J. Solid-State Circuits, vol. 35, no. 5, pp , May 2000.

8 1054 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 10, NO. 12, DECEMBER 2014 [9] D. Park, T. G. Kim, C. Kim, and S. Kwak, A low-power sync processor with floating-point timer and universal edge tracer for 3DTV active shutter glasses, in Proc. IEEE Symp. Low-Power and High-Speed Chips, 2011, pp [10] D.Park,C.Kim,S.Kwak,andT.Kim, Alow-powerfractional-order synchronizer for sync-less time-sequential synchronization of 3dtv active shutter glasses, IEEE Trans. Circuits Syst. Video Technol., vol. 23, no. 2, pp , Feb [11] D. Park and T. G. Kim, A sync processor with noise robustness for 3DTV active shutter glasses, in Proc. Int. SoC Design Conf., 2010, pp Tag Gon Kim (S 84 M 88 SM 95) received the Ph.D. degree in computer engineering with a specialization in systems modeling/simulation from the University of Arizona, Tucson, AZ, USA, in In Fall, 1991, he joined the Electrical Engineering Department, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, as an Assistant Professor, and since Fall 1998, has been a Full Professor with the Department of Electrical Engineering and Computer Science. Between 1980 and 1983, he was a full-time Instructor with the Communication Engineering Department, Bookyung National University, Pusan, Korea, and from 1989 to 1991, he was an Assistant Professor with the Electrical and Computer Engineering Department, University of Kansas, Lawrence, KS, USA. His research interests include methodological aspects of systems modeling simulation, analysis of computer/communication networks, and development of simulation environments. He has published more than 150 papers on systems modeling, simulation, and analysis in international journals/conference proceedings. He is a coauthor (with B. P. Zeigler and H. Praehofer) of Theory of Modeling and Simulation (Academic Press, 2000, 2nd ed.). Dr. Kim was the Editor-in-Chief of SIMULATION: Transactions of SCS published by the Society for Computer Simulation International (SCS). He is a member of Eta Kappa Nu. Daejin Park (GSM 10 M 14) received the B.S. degree in electronics engineering from Kyungpook National University, Daegu, Korea, in 2001, and the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2003 and 2014, respectively. He was a Research Engineer with major semiconductor companies such as SK Hynix Semiconductor, Samsung Electronics, and ABOV Semiconductor for over 12 years from 2003 to 2014, respectively, and has worked on processor architecture design and low-power ASIC implementation with custom-designed software algorithm optimization. Jeonghun Cho (A 05 M 06) received the B.S. degree in electrical engineering, M.S. degree, and Ph.D. degree in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 1996, 1998, and 2003, respectively. He was with the MCU Application Team of Hynix Semiconductors, Korea, where he worked on C Compiler development for 8-bit microprocessors. He is currently an Associate Professor with the School of EECS, Kyungpook National University, Taegu, Korea. His research interest includes optimized compiler, operating system, and design automation for embedded systems and reconfigurable computing. Dr. Cho is a member of ACM.