IC Design of a New Decision Device for Analog Viterbi Decoder

Transcription

1 IC Design of a New Decision Device for Analog Viterbi Decoder Wen-Ta Lee, Ming-Jlun Liu, Yuh-Shyan Hwang and Jiann-Jong Chen Institute of Computer and Communication, National Taipei University of Technology Taipei, Taiwan, R.O.C. wtlee@en.ntut.edu.tw, s48040@ntut.edu.tw, hys@en.ntut.edu.tw, jjc@en.ntut.edu.tw Abstract Under the base-band signal model, this new In this paper, we have developed a new structure has more advantages than the wireless architecture that can process the analog received communication system now. First of all, the signal with the analog circuit design method and proposed structure can reduce the hardware cost the processed analog signal can be used for the than the traditional digital realizations, because analog Viterbi decoder. Moreover, we have the A/D converter and memory unit of channel designed an analog decision device using QAM decoder will not be used. Therefore, the new demodulator. Finally, to verify our architecture, structure will minify the chip area and reduce the we have designed this analog decision device chip system power consumptions. The modified with UMC 0.8-µm P6M CMOS technology. This structure can record the decoding information by chip contains 494 transistors, operates to 00Mb/s electric charge of the capacitor instead of using and consumes 7.46mw. The chip area of the memory cell to save the digital data. This paper analog decision is about 0.544mm. This chip has describes an integrated analog decision device the advantages of low-power, small-area and is with can generate analog input signals for the easy to be combined with the RF front-end analog Viterbi decoder. The analog decision receiver. device is based on a new structure of the difference metric wireless communication. Introduction hardware manufacturing steps. The rest of the paper is organized as follows. We will introduce the new structure of analog demodulator in section. The circuit structure of analog decision device will be revealed in section ; the experimental results and the analysis are shown in section ; the conclusion will be given in section. The Viterbi decoder[][] is employed in many digital communication systems applications, generally involving very noise, where high levels of error correction coding are required. The Viterbi decoder is quiet popular channel decoder, application examples for IEEE-80.a, digital cellular telephony and digital video broadcasting, because it has the modified function to Gaussian noise, and is more economic and effective in channel decoding. In digital realizations, using a highresolution and high-speed A/D converter is necessary in wireless communication hardware implementation[3]. The A/D converter can translate the received analog signals into digital signals for the DSP Chip, and the A/D converter usually cost large power consumption at high speed. In this paper, we propose a new structure based on the model of analog integrated circuit which can process the analog signal without the aid of DSP. It can directly demodulate the analog signals without A/D converter and transmit the analog signals to the analog Viterbi decoder[4][5] and finish the error correction of channel decoding.. The Analog Demodulator The analog demodulation contains four main circuit blocks, as shown in Fig.. The analog demodulation is composed of LO(Local Oscillator), Mixer, LPF(Low Pass Filter) and analog decision device. Because the signal is modulated to high frequency form the transmitter, signal will up converts by the carrier in the transmitter. Therefore, downconverter is necessary in the receiver. Received signal and local oscillation signal is mixed in downconverter, then received signal is translated to low frequency. The received signal down converts form RF frequency, and image signal also down converts to IF frequency. As a result, image rejection is needed to filtrate image signal with the LPF. The function block is called

2 r(t) Heterodyne receiver as shown in the Fig.. Although there are many problems and issues of Heterodyne receiver, but Heterodyne receiver is the most common and popular receiver architecture for wireless communication nowadays. Although the Quadrature Amplitude Modulation(QAM) has been traditionally implemented in the digital domain, high-speed, small size, and low-power constraints have motivated researchers to look for analog realizations. Analog QAM decision has demonstrated many advantages over digital realizations. In an analog implementation, savings are mainly due to the elimination of the A/D converter[7], which usually cost a large chip area and power consumption at high speed. Since the analog decision device for QAM demodulator here is less complex than digital realizations, in this paper, we will focus on the VLSI architecture of an analog decision device. LO Tb () 0 Analog Decision Device Analog Viterbi Decode r Data A. Sample/Hold Circuit The Sample/Hold(S/H)[8] circuit is mainly responsible for proceeding the uniform quantification to the input analog signal, and then transmitting the processed analog signal to the comparator, which can divide the unlimited possibility of analog signal into the limited possibility of quantification signal. The Sample/Hold circuit is shown in Fig. 3, in our design, we need to combine the sampling circuit(m~m8) and the source follower NMOS(M9,M0). This circuit consists of two basic S/H s to operate on a common analog input signal. A commutator can keep the previous sample value, held by one of the S/H s, to the output, while the other S/H samples the new value of the analog input. The input switches NMOS(M,M) are decreased by setting the common-sampling operation. The holding capacitor used in our design is 0.5pF. The system phase φ and φ are two nonoverlapping phases obtained form a divide-by-two clock generator. φ Bias M5 Vdd M6 φ M3 DEMODULATION N Fig.. Block diagram of the analog demodulation M Input φ M M7 M8 φ M4 Bias M9 vout M0 Input v ref S/H v ref3 v ref. The architecture of Analog QAM Decision Device Circuit Our proposed new analog decision device for QAM demodulator contains five function blocks, shown in Fig.. There are Sample/Hold circuit, circuit, Encoder circuit, Multiplexer select output circuit and Clock generator. These blocks are described as follows. Encoder Encoder Encoder3 Encoder4 Encoder MUX MUX Fig.. Block diagram of the analog decision device MUX3 Data Fig. 3. The Sample/Hold circuit B. Circuit Before the signal entering the comparator, it is still analog state, which are unlimited states of analog signal. We can not process the analog signal to decode directly. So we must transform the unlimited possibility of analog signal into the limited state, and then could be used for the analog Viterbi decoding. To process this function, we must use a high-resolution comparator to do this work. The schematic diagram of the comparator[9] is shown in Fig. 4. The input stage of the comparator comprises a source-coupled pair(scp, M8 and M9), a cross-coupled pair load PMOS(M6, M7), and a PMOS transistor switch. In the comparator circuit, a single clock system is used. The PMOS pair becomes regenerative when φ 3 goes high and the switch PMOS(M5) is off. The comparator use latch(m6~m9) that provides two normally outputs, one will be low or high depending on the results of the

3 Vdd M6 Vdd M7 Input CK Vout M A V in φ 3 M5 M3 M4 M M8 V ref φ 3 M0 M9 CK Fig. 5.The circuit diagram of one encoder Fig. 4. The comparator circuit comparison. These two outputs then provide the clocking for the slave encoder. The comparators also need consider the following issues. We use the 6-QAM as an example. The system symbol of 6-QAM is four bits, thus it has 6 states for distinguish the signal space. There are two base spaces for channel, and four states are separated into each part of two bits. The comparators need outside reference voltage that affect rate of bit error probability in this system. Before using reference voltage, we assume the noise distribution is additive white Gaussian noise (AWGN) and data type of transmission is uniform distribution. The maximum-likelihood decision rule (MD) is the one which results in the minimum accumulate bit error. The final result is shown in the equation (). ( V S ) ref 0 exp σ π σ ( V S ) ref exp σ π σ =..() C. Encoder block circuit The received signal of the encoder is from the output signals of previous comparator. Encoders are used to eliminate the phenomenon undefined of state, and the code rule is to accord with the systematic symbol that QAM encoder defines and distributes states. Here, we use CMOS transistors as switch component. Fig. 5 shows one encoder circuit example. The cycle of input signal is controlled by CK, the capacitor is charged by the current of input signal. It can generate different voltage level and hold on a period time by the CK. Finally the capacitor can translate the hold analog voltage into logic level so as to accord with the systematic symbol of QAM. D. Multiplexer Select Output circuit The Multiplexer select output as shown in Fig., is made up of three - multiplexer using transmission gates. The multiplexers are divided into two stages. The first stage is made up by MUX and MUX, they are mainly responsible for Encoder and Encoder3 or Encoder and Encoder4 that will choose the output signal. The second stage is MUX3, which will select the positive analog signal or negative analog signal as the final result. E. Clock Generator The nonoverlapping clock phases φ and φ are shown in Fig 6. The divided-by-two output is then converted to phases φ and φ by nonoverlapping clock generator circuit and are used for the sample/hold circuit. CLK Fig.6. The clock generator circuit Finally, with the five function blocks mentioned above, the decision chip can translate the analog signal to the analog Viterbi decoder without an A/D converter.. Experimental Results We have designed this analog decision device with UMC 0.8-µm CMOS P6M process. In order to be compatible with IEEE-80.a [9]-[] applications, we use a single 3.3-V power supply in our design. The typical received signal and the output of decision device is shown in Fig. 7. The wave forms show that the chip is capable of operating at 00Mb/s. The layout of analog decision device chip is shown in Fig. 8. The analog decision device is simulated with encoder input signal contaminated by additive white Gaussian noise. Fig. 9 describes the chart φ φ

4 (a) (b) (c) (d) Fig. 7.(a) A typical received signal (b)the analog decision output of MUX- (c)the analog decision output of MUX- (d)the analog decision output of MUX-3 of BER and V ref for the analog decision device. Obviously, different V ref can be obtained from BER and V ref in situation. The results are consistent with the union bound, there is some expected degradation at high SNR as shown in Fig. 9, which depicts the results different V ref. The specifications of our analog decision device chip are summarized in Table. The analog integrated decision device chip has the advantage of small size of processor chip area and the efficiency of the proposed over digital realization. TABLE. Summary Performance. Conclusion Fig. 8. The layout of analog decision device with UMC 0.8µm CMOS P6M process. In traditional implementation of wireless communication, it is essential to use a high-speed and high-resolution A/D converter when the receiver signal gets into the digital

5 demodulator and channel decoder. In this paper, we propose a new structure based on the model of analog integrated circuit which can process the analog signal without the aid of DSP. It can directly demodulate the analog signals without A/D converter and transmit the analog signals to the analog Viterbi decoder. Finally, we have designed an analog decision device chip using QAM demodulator, and was designed in UMC 0.8-µm P6M CMOS technology. The chip contains 494 transistors, operates to 00Mb/s and power consumes 7.46mw. This new architecture can provide a new efficient design for future SOC communication. Acknowledgment The authors would like to thank the National Science Council and Chip Implementation Center of Taiwan, ROC, for financial and technical supporting. The work was sponsored by NSC-93-5-E References [] Fettweis G. and H. Meyr, High-speed parallel Viterbi decoding algorithm and VLSI-architecture, IEEE Trans on Commun., vol. 7, no., May 99. [] Wen-Ta Lee, Geng-Huan Lin, Chia -Chun Tsai and Trong-YenLee, A window based Viterbi decoder IP builder for RCPC codes, in Proc. of The 003 International Symposium on Communications, Paper 7.4, Dec [3] Chia-Chun Tsai, Kai-Wei Hong, Yuh-Shyan Hwang, Wen-Ta Lee and Trong-Yen Lee, New power saving design method for CMOS flash ADC, in Proc. The IEEE 47 th International Midwest Symposium on Circuits and Systems, pp. III ,July 004. [4] Demosthenous, A. and Taylor, J., A 00-Mb/s.8-V CMOS current-mode analog Viterbi decoder, IEEE J. Solid-State Circuits, vol. 37, pp , July 00. [5] K. He and G. C., Integrated 64-state parallel analog Viterbi decoder, in Proc. IEEE 000 ISCAS, vol. 4, Geneva, Switzerland, pp , May 000. [6] D. Sun, A. Xotta and A. Abidi, A GHz CMOS analog-front-end for a partial- response read channel, ISSCC. Digest of Technical Papers, vol., pp , Feb [7] M. H. Shakiba, D. A. Johns and K. W. Martin, BiCOMS circuits for analog Viterbi decoders, IEEE Trans. circuits syst. II, vol. 45, pp , Dec [8] T. W. Matthews and R. R. Spencer, An integrated analog COMS Viterbi detector for digital magnetic recording, IEEE J. Fig. 9. BER performance of the analog decision device Solid-state circuits, vol.8, pp , Dec [9] M. H. Shakiba, D. A. Johns,and K. W. Martin, An integrated 00MHZ 3.3V BiCMOS class-iv partial-response analog Viterbi decoder, IEEE J. Solid-state circuits, vol. 33, pp. 6-75, Jan [0] Planex Communication, Wireless Access Card Data Sheet, [] VastVAN Communication, Wireless LAN Products Data Sheet, Dec