CALIFORNIA STATE UNIVERSITY, NORTHRIDGE. Reconfigurable RGB Video Test Pattern Generator

Transcription

1 CALIFORNIA STATE UNIVERSITY, NORTHRIDGE Reconfigurable RGB Video Test Pattern Generator A graduate project submitted in partial fulfillment of the requirements For the degree of Master of Science in Electrical Engineering By Linda Megerdichian December 2016

2 Signature Page The graduate project of Linda Megerdichian is approved by: Dr. Ramin Roosta Date Professor Benjamin Mallard Date Dr. Shahnam Mirzaei, Chair Date California State University, Northridge ii

3 Acknowledgment First and foremost, I would like to express my sincere gratitude to my advisor Prof. Dr. Shahnam Mirzaei for the continuous support, encouragement and thoughtful guidance during the project execution phase. I want to express my deep thanks to members of the reading committee, Prof. Dr. Benjamin Mallard and Prof. Dr. Ramin Roosta for agreeing to be members of the project committee and for their detailed review. I would also like to thank Prof. Dr. George Law for introducing me to world of Digital Hardware Design and for promptly responding to every single . I want to express my deepest appreciation to my manager Mr. Vince Hann for his help and understanding during this process, also to my teammates Ray Duran and Matt Reister for their interesting ideas and assistance. I will never forget all your help and support. At last, I cannot finish without thanking my family especially my mother and siblings for their patience and unconditional support during this journey. And my father whose loving memory always gives me strength. This accomplishment would not have been possible without them. Thank you. iii

4 Table of Contents Signature Page... ii Acknowledgment... iii List of Tables... viii Abstract... ix Chapter 1: Introduction Background System Block Diagram and Description Block Diagram Design Description... 3 Chapter 2: Video Introduction to Video Video Data Video Timing Video Resolution High Definition Video Progressive and Interlaced... 8 Chapter 3: Color Space What is a Color Space? Introduction to RGB system... 9 Chapter 4: VGA Introduction to Video Graphics Array (VGA) VGA Data and Timing signals Pattern Generation Resolution constants Applications Chapter 5: Analysis of Results Simulations Pattern Verification Timing Verification Chapter 6: Screenshots of Display Chapter 7: Conclusion Design Runs iv

5 7.2 Summery Timing Summery Schematic Chapter 8: VHDL Code Top Level Wrapper Ball Top Level, vid_test_ball Ball Sync Generator Ball Static Pattern Generator Test bench Constraint file Resources v

6 List of Figures Figure 1. 1 Block Diagram... 2 Figure 2. 1 On the left: Progressive. On the right: Interlaced [1]... 8 Figure 3. 1 RGB Color Space [2] Figure 3. 2 RGB color cube [1] Figure 3. 3 Signal Representation of Color Bars Figure 3. 4 Color Bars FIgure 4. 1 VGA Port [4] FIgure 4. 2 Flyback or Blanking Area FIgure 4. 3 Raster Scanning and Horizontal and Vertical Flyback FIgure 4. 4 VGA Waveforms [3] FIgure 4. 5 Single TDMS [1] Figure 5. 1 Clock Generation Figure 5. 2 White Background Figure 5. 3 Hsync Signal Figure 5. 4 Vsync Signal Figure 5. 5 Blue Flat Screen Figure 5. 6 Red Flat Screen Figure 5. 7 Green Flat Screen Figure 5. 8 Ramp Figure 5. 9 Color Bars Figure Gray bars Figure Checkered Figure Stripes Figure Vsync Period Figure Hsync Period Figure 6. 1 White Flat Screen Figure 6. 2 Green flat screen Figure 6. 3 Blue flat screen Figure 6. 4 Red flat screen Figure 6. 5 Horizontal bars Figure 6. 6 Vertical bars Figure 6. 7 Mesh Figure 6. 8 Grayscale bars Figure 6. 9 Color bars vi

7 Figure Horizontally Split Color Bars Figure Checkered Figure Alternating pixels Figure Vertically moving square Figure 7. 1 Design Runs Figure 7. 2 Summery Figure 7. 3 Timing Summery Figure 7. 4 Schematic of the design vii

8 List of Tables Table p Timing constants... 4 Table bit RGB values for Color Bar [1] Table bit RGB values for Color Bar Table 4. 1 ZedBoard VGA pin description [4] Table 4. 2 VGA Signal Description [3] Table 4. 3 Color Borders Table 4. 4 Resolution Constants viii

9 Abstract Reconfigurable RGB Video Pattern Generator By Linda Megerdichian Master of Science in Electrical Engineering The main goal of this project is to provide video test patterns that can be used to verify video processing cores. It is common to break down large designs into subprojects among different development teams. Each team is in charge of developing a specific part of the design. Having a verification system for sub designs assures that the development team can move forward without staying on hold for delivery of particular part of the design. Detecting any bug in a sub design before putting all other parts next to each other gives the designer the ability to limit the scope of debugging to a particular block and knowing where to look for is the biggest step in resolving the issue. As a result, partial design tests can be performed rapidly to save time and control the cost. In the development of video systems, an internal video source gives the ability to test the design independent from the input source. It generates patterns for system debugging and evaluation. Static pattern generator can be used to assess quality, linearity, color, and edge depending on the specification of the targeted design. Adding a pattern with motion such as screen saver will add the ability to debug motion performance and detect frozen images. Color bars are used to verify reproduction of color correction functions and the color scope of a display monitor. Vertical and Horizontal stripes are used to test system linearity and edges, an edge can be the border where one color is changing to another. Flat fields are used to detect any Chroma issues. All the patterns are used to detect flicker caused by video processing cores. The functionality of IP cores and components such as Packetizer, Color space converter, Encoder/Decoder, DDR memory can be tested using video pattern generator. ix

10 Chapter 1: Introduction 1.1 Background The project involves video test pattern generation implemented on ZedBoard (Zynq Evaluation and Development) and VGA. The board is based on Xilinx Zynq-7000 extensible processing platform. A combination of 85,000 seris-7 programmable logic cells and dual corex- A9 processing system. The FPGA (Field Programmable Gate Array) used in the board is Xilinx XC7Z020-1CSG484CES with 512 MB DDR3 and 256 Mb Flash memory. The display features on ZedBoard include HDMI output, 12-bit color VGA and OLED display. The VGA output of the board is used to display the image generated in the FPGA on the display. This project includes design and implementation of Video RGB pattern generator. The code is developed in VHDL using Xilinx Vivado. The goal is to generate the patterns without using any IP cores and without reading the images from memory. This makes the design portable. It can be implemented on any FPGA device independent from manufacturer, which gives the designer the ability to use this design as a testing method to verify the functionality of their design in any device. In this project patterns are displayed via VGA port in 640x480 resolution at 60 Hz refresh rate, Dip switches on the board are used to switch between patterns. 1.2 System Block Diagram and Description Block Diagram Block diagram of the system is shown in Figure 1.1. System includes two different generators. The first one, named Dynamic pattern generator generates the screen saver pattern. This pattern is a green square moving from top to bottom of the screen. The second generator called Static pattern generator, it generates a variety of static patterns such as flat screens and color bars and etc. 1

11 Timing signals are generated in both blocks separately instead of having them generated in one single block to insure synchronous data and timing signals. In dynamic generator, using slightly different timing constants to get a stable image. Two different counters are used to count the number of pixels in each row and the number of rows in each frame. The counter values are compared with the resolution constants defined in the design to generate timing signals (timing signals are explained in chapter 4). Dip switches on the ZedBoard are used to control the resolution and patterns. The Motion selector signal (8 th bit if Resolution select signal in this design) is used to control the multiplexor to select between the two generators. Once the Dynamic Pattern Generator is selected the screen saver pattern is sent to VGA of the FPGA and then to Display. Figure 1. 1 Block Diagram If the Static Pattern Generator is selected by changing the values of Resolution_sel the synchronization signals for that specific resolution are generated. The design has the ability to generate the resolutions starting from 640x480p to 4K. The design is parameterized and any other resolution can be added only by adding the constant values of that particular resolution to the design. The design frequency is 60 Hz which means 60 frames per second are sent to the output, which will be explained more in Video Timing section. 2

12 Changing values of Pattern_sel generates different patterns in Static Pattern Generator. The first bit of Resolution select selects between the moving ball and static pattern generator. The patterns generated by static generator are: - Black flat field - Red flat field - Green flat field - Blue flat field - Gray scale ramp - Gray Scale bars - Color bars and color bars - Color bars and horizontally swapped color bars - Black and white checkered generating a 32x32 pixels square - Alternating pixels - Mesh with 8x8 internal squares - Vertical Stripes, 16-pixel wide - Horizontal bars, 8-pixel wide The top level files includes the port mapping of the blocks shown in Figure Design Description The first step in this design is understanding the concept of video and video timing, what video data is and what the monitor expects to receive in order to function correctly and display the image (explained in Chapter2). The next step is to generate the video signals and the timing signals, keep in mind that there is a relationship between video timing signals, the image resolution and video data. This step involves assigning the selected resolution values to related signals such as horizontal and vertical frontporch and backporch, horizontal start, vertical start and so on which are show in table 4.4. For each resolution the design will assign specific values to timing constants which are used to generate timing signals, consider a 640x480 resolution image with the following specifications. 3

13 Resolution V freq (Hz) H Total H Front H Sync H Back H Active V Total V Front V Sync V Back V Active 640x480 / Table p Timing constants Vertical frequency equal to Hz (Approximately 60 Hz) means that in one second 60 frames are sent to the display. In this design to send 60 frames per second all timing constants are declared as above (Chapter 4). The timing constants in the table above are in pixel size and in the dynamic generator component, some changes were required in the constant values to get a stable video and to avoid flickers. The changes are minor in size of 1 or 2 pixels. In static pattern generator, to generate the timing signals two counters are used. First one is used to count the number of pixels in a row. It counts from 0 to H_total which is 800 pixels in a 640x480 resolution. When the pixel_count is equal to H_total-2 the end_horizontal_line signal is set high in other cases it is set low. From 0 to H_total-1 is 800 pixels, and the signal will be triggered in the next clock cycle that is why the pixel count is compared to H_total-2 instead of H_total-1. The second counter is the row counter and is counting from 0 to V_total which is the total number of vertical lines. In 640p resolution V_total equals to 525 pixels. When the row_count is equal to V_total the counter value is set to 0. If the row_count value is between the vertical front porch and V_total, then the vertical_sync signal is enabled. When the vertical sync is enabled and pixel count is between horizontal_front_porch value and H_total then Vertical sync is set high or else it is set low. Importance of timing signals and more details about them will be discussed in Chapter 4. For having a synchronous design, the same pixel and row counters are used to generate the patterns which is discussed in more details in Chapter 4.3. The top level of dynamic pattern generator is called vid_test_ball, which is a wrapper where two components called ball.vhd and vga_sync.vhd are instantiated. Initially ball.vhd is generating a green square in the middle of the screen at (320,240). The square is moving 5 pixel at a time to top or bottom of the screen. On Y coordinate, if the current location of the square plus the size of the square is greater than 480 then at next time frame the ball will move 5 pixels up, and if on Y it is smaller than the size then it will move 5 pixels down. Timing signals for this component are 4

14 generated using vga_sync.vhd which is designed the same as the timing generator section in static pattern generator, the only difference is minor changes in timing constants. The test bench, vid_test_tb.vhd, is used to provide the input to the design for simulation. The inputs to the unit under test are clk, rst and res_sel. The res_sel (3 downto 0) is connected to pattern select in vid_test_pat_gen.vhd and is used to switch between patterns. At the end the video and timing signals are sent to VGA using the pin assignments in the constant file (see table 4.1 for pin numbers). 5

15 Chapter 2: Video 2.1 Introduction to Video Video signals are a way of transmitting visual data from source to destination. The data may come from a computer, VCR, cable television or other sources. In order to transfer data from one device to another there are many requirements and as a result many ways to do so. Most video equipment was designed for analog video until a few years ago, but nowadays all consumers use digital video on daily bases. [1] 2.2 Video Data Essentially video signal contained only gray scale information which is also called black and white video. Over years, attempts were made to transmit the Red, Green, Blue (RGB) video using analog signals, the problem with this system was the high bandwidth consumption. The Analog RGB signals occupy 3 times more bandwidth than alternate methods which were developed later. In the new methods such SECAM, or PAL only one analog signal was transmitted and the bandwidth was reduced accordingly. The Digital video consists of encoded digital data which represents Visual images. Nowadays there are different ways of representing video data which are mathematically related to RGB, these variations such as RGB itself, YUV, YCbCr, are called color spaces (Chapter3). Most common color spaces used are RGB and YCbCr. RGB is digitalized version of analog Red,Green and Blue signals and YCbCr is digitalized version of analog YPbPr. In YCbCr, Y (Luma) indicates brightness and Cb and Cr represent color difference signals, while RGB represents the primary colors. (Chapter 3). YCbCr is used in DVDs, digital TV and Video CDs where MPEG compression is used. Generating the colors in RGB is simpler. YCbCr color space is used when the data is transmitted from a source to destination, the data is encoded in transmitter and is decoded to RGB in receiver. 6

16 2.3 Video Timing A Video is series of still images, typically changing 50 to 70 times per second with is fast enough to look like a continuous motion. Vertical Sync is the timing information used to indicate the speed of refresh of each image. Each image includes sequential scan lines. Horizontal Sync is the timing information used to indicate when a new line starts. Horizontal and vertical Sync which are also called Video Timing Signals can be transferred in one of these three ways: 1- Separate Horizontal and Vertical Signals 2- Separate Composite Sync Signal which is the combination of Hsync and Vsync signals 3- Composite Signal embedded within Video Signal. VGA is expecting separate sync signals therefore third method is used in this design. So, separate Horizontal and Vertical Sync signals are generated. 2.4 Video Resolution Video resolution is referred to the number of horizontal pixels and vertical scan lines. More technically video resolution is the number of distinct pixels in each dimension that can be displayed. A 720p video has 720 lines that are each 1,280 pixels, which is twice as sharp as a 480p video and can be viewed on a larger screen. Higher resolution means better video quality and lower resolution means lower video quality. By increasing the resolution, more pixels are needed to display an image. If pixels are sent at the same rate as before, the time to transmit one frame will go up, so the number of frames in a certain timespan will go down. Since a CRT displayed pixel only gives light for a short time before running out of energy, it needs to be repeatedly refreshed. If this is done fast enough, at about 50Hz, the screen appears smooth and constant to the human eye. This improves when the refresh rate is higher where human eye is unable to recognize the frame change. But, when the rate is too low, the screen will start flashing. Therefore, we need to keep the frequency at, at least, 50Hz. 7

17 2.5 High Definition Video HD (High Definition) video is referred to a video which has 720p (progressive), 1080i (interlaced), or more active lines. HDTV displays are capable of displaying minimum 720p or 1080i scan lines. 2.6 Progressive and Interlaced The progressive display scans an image starting from top left corner of display moving to the right end of the display. Then scans the following lines one by one (Figure 2.1). As a result, images appear smoother. Artifacts are much less. If the display rate is 60Hz then the progressive video displays the entire image in 1/60th of a second. Figure 2. 1 On the left: Progressive. On the right: Interlaced [1] In earlier days of television and image processing, another technique named interlaced was used. Interlaced scanning reduces the amount of information sent for each image or frame. In this method lines with odd numbers are sent and they are followed by lines with even numbers, as a result the amount of information sent at a time is halved. Why use the progressive method then? In interlaced method, each scan is happening in half time as it would be in a progressive display which means half time lower refresh rate, which can generate flickers. In reality, all digital, non- CRT displays are natively progressive, and if they receive any interlaced video signal it must be converted to the progressive format before it can be displayed. In progressive method there is not a line to line change limit consequently it is capable of previewing higher resolutions without flickers. The Plasma and computer displays are progressive. 8

18 Chapter 3: Color Space 3.1 What is a Color Space? Color spaces or color models (or Color Systems) are mathematical representation of colors as tuples numbers. A range of colors can be created by the primary colors of pigment and these colors then define a specific color space. In other words, color space is an elaboration of the coordinate system and sub-space where every color in the system is represented by a single dot. RGB (used in computer graphics), CMYK (cyan, magenta, yellow and key for black) and YUV or YCbCr (used in video systems) are the most used color spaces. RGB used in computer graphics because all other color spaces can be generated using R, G and B values. Therefore, designing in RGB standard makes the architecture of the design simpler. A system designed in RGB color model is compatible with most software applications. Keep in mind that RGB is not the most efficient when transferring the data from one location to other; All the components in RGB color space require same band width to generate any color in RBG color space which is why in transmitting data the data is converted to other color spaces such as YCbCr. 3.2 Introduction to RGB system Human eye is able to see using receptors located on the retina. There are two types of receptors, classified by function: The Rods, responsible for black and white perception, and the Cones, in charge of color discrimination. There are three types of cones. One type reacts to Red light, another to Green light and the last group to blue light. In simple words we catch red, green and blue colors but we are able to see all the colors. Considering this fact, we can conclude that we only need to know the relative amount of the three basic colors: Red, Green and Blue. These three colors are primary colors in color generation and are used to generate any other color. To generate the color for each pixel we will need to generate the RGB values for that particular pixel at the same time. An RGB color space can be interpreted as "all possible combinations of colors" which can be generated from three colors for red, green and blue. In such conception, each pixel 9

19 of an image is assigned a range of 0 to 255 (in an 8-bit system) intensity values of RGB components. Any color in the following coordinate system can be generated by assigning the corresponding axis value to Red, Green, Blue data signals. Figure 3. 1 RGB Color Space [2] Using only these three colors in an 8-bit system, 16,777,216 colors can be displayed on the screen by different mixing ratios. The system can be designed 8, 10 or 12 or more bits depending on application, for instance an 8-bit system has total data value of 24 bits, for a 10-bit system there are total of 30 bits, 10 bit for each color and the same applies the 12-bit system generating total of 36 bits. Figure3.2 shows the three-dimensional representation of RGB system which is also shown in Figure 3.1. The representation is also called Cartesian coordinate system. As shown in the Figure3.2 the gray diagonal of cube is a representation for various gray levels where all primary color values are equal. 10

20 Figure 3. 2 RGB color cube [1] Table 3.1 contains the RGB values for values for color bars with 100% amplitude for 1-bit color representation. White Yellow Cyan Green Magenta Red Blue Black Green Red Blue Table bit RGB values for Color Bar [1] Figure 3.3 is the signal representation of the color bars, each combination in the table above is shown below. Figure 3. 3 Signal Representation of Color Bars If each color is represented by 8 bits, then the high 100% amplitude value for each color will be 2 8 = 255 and for a 10-bit system it will be 1023 and so on (Table3.2). White Yellow Cyan Green Magenta Red Blue Black Green Red Blue Table bit RGB values for Color Bar 11

21 According to the values shown above black, red, green and blue flat fields are also generated according to table above, for example to generate blue, Green and Red data bus are set low and Blue data bus is set high. A basic color bar with 8 different colors is shown in Figure 3.4. Figure 3. 4 Color Bars Consider an 8-bit system. To generate the white bar, the values for Red, Green and Blue should have high voltage levels, high voltage level is shown by 1 and low voltage level is shown by 0. Which will give us the values in table below for colors shown in Figure 3.1. Depending of the processing technique the RGB format of the data can be converted to any other color space such as YUV,Y UV,YCbCr, ect. For example in a YUV system Y represents the luminance component (brightness of the image) and U and V are the chrominance (color components). And the following equations are used to convert the RGB to YUV color space. [1] Y = 0.299xR xG xB U = xR xG xB V = 0.615xR xG xB By using the equations for other color spaces and by adding a small block to convert the Data the system can adopt to any color space required. What are color bars? And why are they widely used in video processing? Color bars are electronically generated video signals. In color bars the levels of the Luma and Chroma are standardized and they can be used for passing through different components of a video system to see how each device is affecting the signal, by seeing the effects of every component the error occurred in that component can be identified and fixed. 12

22 When to use a color bar? Analog devices always need to be calibrated, because of heat, noise, cable length, and many other factors affect the voltage of an analog video signal, which affects the brightness and color of the video image. Color bars provide a reference signal which can be used to calibrate the output levels of an analog device. Digital devices may also process the pixels in incorrect order, they may delay the timing signals and so many other factors can cause different bugs in the design, color bars can be used as a reference to identify and debug these design problems. 13

23 Chapter 4: VGA 4.1 Introduction to Video Graphics Array (VGA) VGA refers to the display hardware first introduced with the IBM PS/2 line of computers in VGA originally supported the 640x480 resolution with refresh rate of 60Hz. The VGA connector has 15 pins (Figure 4.1). Each pin has its own functionality. Which is shown in the table below (Table 4.1). The ZedBoard allows 12-bit color video output through VGA connector [4]. FIgure 4. 1 VGA Port [4] PIN SIGNAL DESCRIPTION EPP PIN 1 RED Red Video V18, V19, U20, V20 2 GREEN Green Video AB21, AA21,AB22, AA22 3 BLUE Blue Video AB19, AB20, Y20, Y21 4 ID2/RES Formerly Monitor ID bit 2-5 GND Ground (Hsync) - 6 RED_RTN Red return - 7 GREEN_RTN Green return - 8 BLUE_RTN Blue return - 9 KEY/PWR Formerly key - 10 GND Ground (Vsync) - 11 ID0/RES Formerly Monitor ID bit 0-12 ID1/SDA Formerly Monitor ID bit 1-13 Hsync Horizontal sync AA19 14 Vsync Vertical sync Y19 15 ID3/SCL Formerly Monitor ID bit 3 - Table 4. 1 ZedBoard VGA pin description [4] 14

24 4.2 VGA Data and Timing signals Video Graphic Array (VGA) is a standard developed to drive Cathode Ray tube (CRT) displays by Personal Computer (PC). The first image resolution was 640x480 in RGB standard. By time VGA the standard has been evolved to support a wide variety of resolutions. The screen is built up scan line by scan line which means the data is transmitted line by line. The appropriate RGB data is sent to display over the connection. However, only a stream of data will not provide enough information to tell the display which part of the stream belongs to the top-left-pixel on the screen and where the frame starts. Let us take a step back and remind ourselves the origin of terms Vertical Sync and Horizontal Sync. The main fact to remember is that, when the original VGA standard was introduced, the main form of computer display was based on the CRT, in which an electron beam is used to scan a phosphorescent screen. The CRT used magnetic fields to project electron beams onto a phosphoric layer, making them visible for a short period of time. Hence the video signal has to have some gaps to adopt with the time a monitor needs to alter the magnetic fields and point the electron beam back to left side of the screen. In the meantime, there is no data sent to display. There are different ways in which an electron beam can be directed to create images on a CRT screen, by far the most common technique is the raster scan. In this technique the display is scanned line by line and pixel by pixel from left to right. When the beam reaches the right-hand side of the screen it undergoes a process known as horizontal Flyback, or Horizontal Blanking. The blanking and display areas are shown in Figure4.2. FIgure 4. 2 Flyback or Blanking Area The gray area in Figure 4.2 is called Blanking or Flyback area and the area in the middle is named the Display or Active area. The display area s specifications declare the resolution of the 15

25 image. As each frame has the same number of pixels, the time between consecutive pulses is a constant value. The display times the frequency of the pulses, then based on that it indicates at what time the color data should be sent to what position on the screen. The beam starts forming the lines or rows from the first until it forms the last line, at the bottom of the screen. The number of rows in the screen affects the resolution of the picture. When the beam reaches the bottom right-hand corner of the screen it undergoes vertical flyback, in which its intensity is reduced, it flies back up the screen to return to its original position in the upper left-hand corner, and the whole process starts again. (Figure 4.3) CRTs have improved a lot since then, and are replaced by the highly intelligent LCD display. Nevertheless, the standard for signaling hasn't changed since. LCD displays decode a CRT signal and then restructure it to fit their own screen grid under analog signaling methods. FIgure 4. 3 Raster Scanning and Horizontal and Vertical Flyback In raster scan method a single screen scan creates a complete frame. The screen refreshes 60 frames per second and the process begins at pixel (0, 0) located at the top left corner of the screen and changes the color of 1 pixel at every clock cycle from left to right side of the display. X and Y are the values indicating the resolution of the image, for example for a 640x480 resolution there are 640 columns and 480 rows and total of 307,200 pixels on the display. At the end of each line the line number is incremented and the column number is set to 0. Once the line counter reaches Y-1 and the column counter reaches X-1 entire screen is scanned the refresh process begins again. The signals controlling the refresh time and the time between scanning lines are the timing signals. 16

26 A VGA video signal includes the following five active signals: - Vertical sync - Horizontal sync - Red - Green - Blue Both horizontally and vertically, there are 6 states, and hence, 6 sizes. Each area is measured in pixels. Most of the released data is part of the active display. All frames of a video signal have a specific layout. In order for Display to be able to derive all the sizes data some information is required. These signals are connected to 15-pin D- subminiature connector. The monitor will receive these digital signals and will convert them to analog signals, Analog signals are used to generate different colors. Different analog levels produce all other colors. FPGA generates the horizontal and vertical synchronization pulses to control the raster scan of the display. The vertical sync represents the start of a frame and it brings the beam back to the top left corner of the display, and once it is high the monitor starts the scan in the upper left corner with pixel (0, 0). The horizontal pulse triggers the horizontal scanning of the next row. FIgure 4. 4 VGA Waveforms [3] 17

27 Parameter Description A One full row B Horizontal Sync C Horizontal Back Porch D RGB Data E Horizontal Front Porch O One Full Frame P Vertical Sync Q Vertical Back Porch R All the rows in one frame S Vertical Front Porch Table 4. 2 VGA Signal Description [3] The RGB data can be designed in different width, 8, 10, 12 bits. The wider width provides more variety of colors. If the video is represented by N bits, 2 N analog levels can be generated which will give 2 N different colors. Consider a RGB system where each color is represented by 2 bits then for each color we will have 2 2 analog levels and we will have total of 2 3x2 color combinations. In this project in order to display the pattern using VGA port 12-bit video is used which includes 4-bits of Red 4-bits of Green and 4-bits of Blue. In today s flat-screen, liquid crystal displays (LCDs) technologies, we don t actually need to worry about horizontal and vertical sync times. Thus, anything driving a VGA output generates the timing signals required to drive CRT display, and other forms of display simply make allowances for any specifications associated with these VGA signals. In this design Synchronization signals are generated in Pattern Generator blocks to verify functionality of the design using the VGA port of the FPGA to display a 640x480 image. The last pattern is generated by the Dynamic Generator which is a green bouncing ball. The motion help with debugging timing issues with the design or frozen images. 18

28 4.3 Pattern Generation In order to generate the timing signals two different counters are used. The pixel counter and line counter, the pixel counter counts the number of pixels in each row. And is used to generate the H_sync, it also is used to generate the patterns. As an Example for pattern generation consider the color bars in X.Y resolution. If X=1280 and Y=730 then the image resolution will be 1280x720 where the total line length is 1650 and the active display width is 1280 pixels. To generate bars with equal width we will have: 1280/8 which is 160 pixels for each bar. For this resolution the horizontal backporch value or the horizontal flyback equals 370 pixels. If the number 0 is assigned to the first pixel on the row, then first bar starts on pixel 370-1= 369 and the next bar starts at =529 the third bar starts at = 689 and so on. The last bar will start at 1489 and will end at These values are pre-calculated and declared as constants in the design. In table1.3 the values for 1280x720 resolution are provided as an example Bar location Bar1 Bar2 Bar3 Bar4 Bar5 Bar6 Bar7 Bar8 Pixel number Table 4. 3 Color Borders Every time the pixel_count reaches one of above values a specific RGB value is assigned to RED, GREEN, BLUE signals. Values in table 1.3 are used to generate three of the patterns in this system which are Color bars, Color bars and swapped of color bars and Gray scale color bars. In order to generate gray scale bars starting from black and changing to white, 6 different tones of gray are required. Let us consider 12-bit system. Knowing that white is generated when all the bit values are high then the signal values for each color is as follows: RED = , GREEN = , BLUE = And black will be generated when RED = , GREEN = , BLUE = To generate 8 bars, we need 8 different tones. One of the colors used in this pattern in black which takes the value low for all the bits in all three colors. As a result, we will need 7 more tones. ( )2= 4096 => = 4095 By dividing the maximum decimal value for first color we will have: 4095/7 =

29 By subtracting 585 from 4095 and continuing the operation we will have the 7 values we are looking for. Other tons of gray are generated by assigning the following values to RED, GREEN and BLUE signals for different bars = 3510, = 2925, = =1755, = 1170, = Resolution constants resolution. The table below includes the timing values for each resolution, consider the 1280x720 V freq H H H H H V V V V V Resolution (Hz) Total Front Sync Back Active Total Front Sync Back Active 640x480 / x x1080/ x Table 4. 4 Resolution Constants If we consider the backporch and frontporch as pixels in the same line then H_Total represents the total number of pixels in a row including backpporch, frontporch, and the active pixels in that row. In 720 resolution the H_Total= 1650, = 370 which is the blanking period for one row in this resolution. By adding H_Back=220, H_sync=40 and H_front= 110 We will get the same value which is 370. V_total = 750 represents the total number of rows in one frame in 1280x720 resolution, and as expected the difference between total number of lines and active lines is equal to addition of V_front, V_sync and V_back. The inactive pixels create the flyback area. 4.5 Applications In industry generating duel and quad pixels at time will speed up the processing time. When the output of the pattern generator is connected to other blocks such as Packetizer or CODEC (a code for encoding or decoding a digital data signal) that block may be expecting the data in a specific format. 8-bit, 10-bit, 12bit or Single, Duel or Quad Pixels and etc. according to specification of the block expecting the data the generator is designed. For example, in the static 20

30 pattern generator in generate Dual or Quad pixels at a time and at the same time keep the ability of the divoce to process all types of the data the clock running the generator should be modified. Keep in mind that the data_valid signal for all cases will be high for the same amont of time but the system clock for duel pixel should be half single pixel clock rate. Same rule applies the quad pixel system where the system clock is one forth of the single pixel sysem. In this design the pattern is generated in signle pixel mode. FIgure 4. 5 Single TDMS [1] As an example consider the Single TDMS (transition-minimized differential signaling) system below. The 8-bit data generated and the sync signals are processed by going through the encoder unit which can be a CODEC used in many companies, the date will be encoded, compressed, the color space of the date will be converted to YCbCr and the data signals will be packetized to be send to the link for transfer. The color bar generator can be used and an input to this design to test the functionality of all the blocks. Inside the encoder block there are multiple components which can be tested one by one and using SignalTap feature in Intel devices and the Chipscope in Xilinx devices gives us the ability to test the functionality of the design on hardware and to be able to see and image and locate the erroneous blocks of the data. After spotting them we can SignalTap the name location and identify the reason for the error. 21

31 Chapter 5: Analysis of Results 5.1 Simulations Pattern Verification The Clk_period in test bench equals to 10ns. It starts from clk= 0 after clk_priod/2 the clock signal toggles. (Figure: 5.1) Figure 5. 1 Clock Generation White background is generated for the screen savor pattern, all video signals are high. Video signals are 0 during blanking time. (Figure: 5.2) Figure 5. 2 White Background Active low Hsync is generated. Hsync indicates start of a new line. (Figure 5.3) Figure 5. 3 Hsync Signal 22

32 Vsync represents start of a new frame. (Figure 5.4) Figure 5. 4 Vsync Signal For res_sel (7 downto 0) = , Blue flat screen is generated. Ash shown in Figure 5.5 during active video time vga_red and vga_green video signals are low and blue is high. Figure 5. 5 Blue Flat Screen When res_sel (7 downto 0) = , Red flat screen is generated as shown in Figure 5.6 vga_red is high and the other video signals are 0. Figure 5. 6 Red Flat Screen When res_sel (7 downto 0) = , Green flat screen is generated (Figure 5.7) vga_green is high and the other two video signals are 0. 23

33 Figure 5. 7 Green Flat Screen For res_sel (7 downto 0) = , Ramp is generated.(figure: 5.8). According to Figrue 3.2 Red, Green and Blue signals take euqal values to generate differnet shades of gray. Figure 5. 8 Ramp When res_sel (7 downto 0) = , color bars are generated. In Figure 5.9 the signal representation of color bars discussed in Chapter 3 is visible. Figure 5. 9 Color Bars If res_sel (7 downto 0) = , the pattern generated is similar to color bars, the only differnec is that in this pattern the image is split into 2 part horizontally and the top part is a difernet color bar than the bottom part of the image. 24

34 If res_sel (7 downto 0) = , differnet shades of gray are generated in 8 bars, starting from white to black. Figure Gray bars When res_sel (7 downto 0) = , checkered pattern is generated, as expected we can see that alternating sets of white and black pixels are generated in a row. After 32 rows the colors will be swapped. Which will create back and white squares. Figure Checkered For res_sel (7 downto 0) = , alternating pixels are genrated. When the first bit of pixel counter is 0 the pixel is white else the pixel is black. When res_sel (7 downto 0) = vertical stripes are generated, each bar is 15 pixels wide. Figure Stripes 25

35 5.1.2 Timing Verification Figure 5.13 shows the period of vsync signal = 16.8 ms, with refresh rate of 60Hz the total time to refresh 60 frame is approximately 1 second x 60 = 1008 sec Figure Vsync Period Hsync Period I shown in figure 5.14 which is equal to 32.4 micro sec. by dividing the V total time over Hsync period we will get the V_total constant / = which is the same value from Table 4.4 Figure Hsync Period 26

36 Chapter 6: Screenshots of Display Screenshots of the patterns are included to help visualize the patterns generated in this project. Figure 6. 1 White Flat Screen Flat Screen Green generated when r_sig= low, g_sig= high, b_sig= low in all pixel values. Counters are not used in the pattern generation. Figure 6. 2 Green flat screen Flat Screen Blue generated by assigning r_sig= low, g_sig= low, b_sig= high for all pixels. And the counters are not used in generating the patterns, they are only used for generations of timing signals. 27

37 Figure 6. 3 Blue flat screen Red flat screen generated by assigning r_sig= high, g_sig= low, b_sig= low for all pixels. Figure 6. 4 Red flat screen Horizontal Stripes are generated using the row counter, when the row_count (3)= 1 the r_sig, g_sig and b_sig signals are set to high and when the row_count(3)= 0 they are set to low, which gives us the black and white stripes. Figure 6. 5 Horizontal bars Vertical Stripes are generated using the pixel counter, when the pixel_count (5)= 1 the r_sig, g_sig and b_sig signals are set to high and when the row_count(5)= 0 they are set to low, which gives us the black and white bars below. 28

38 Figure 6. 6 Vertical bars This pattern is generated using both pixel and row counters if row_count(3)= 1 and pixel_count(3)= 1 the r_sig, g_sig and b_sig signals are set low. If the pixel_count(3)= 0 then the r_sig, g_sig and b_sig signals are set high. Figure 6. 7 Mesh Grayscale bars are generated by using the pixel_count value, when the pixel_count is equal to bar1 the gray scale value is assigned to the pixels in that area. The gray shade changes by moving from bar1 to bar2 and so on, bar1 to bar 8 values are constants which are assinged to this signals when the resolution is selected, for display purposes only the 640x480 resolution is chosen. Figure 6. 8 Grayscale bars 29

39 Color bars are generated by using the pixel_count value, when the pixel_count is equal to bar1 the color value is assigned to the pixels in that area. The color changes by moving from bar1 to bar2 and so on, as it was explaianed for grayscale bars the same logic is used for color bars also, bar1 to bar 8 values are constants values for specific resolution. They are assinged to bar1 to bar8 signals when the resolution is selected, for display purposes only the 640x480 resolution is chosen. Figure 6. 9 Color bars This pattern is generated by using the pixel_count and row_count values, the first half of the pattern is generated the same as color bars, when the row_count is half the Vertical resolution value which for this pattern in 640x480 resolution is 240 pixels, where rown_count = 239 then the colors are swapped and a new color bar is generated(figure: 6.9). Figure Horizontally Split Color Bars Using pixel_count and row_count values 32x32 pixel squares are generated, when row_count(5)=0 the pixel_count is counting from 0 to 31 and assigning white to first square and black to next, the same order is followed until the end of row 32. When row_count(5) = 1 then color order changes to black first then white(figure: 6.10). 30

40 Figure Checkered Alternating pixels are generated using pixel_count signal. When the first bit of pixel_count is 0 the pixel color is white and when it is 1 the pixel color is black. In other words odd pixels are black and even pixels are white. Figure Alternating pixels 31

41 A green square is generated in a separate component and is moving vertically, 5 pixels at a time. (1) (2) Figure Vertically moving square 32

42 7.1 Design Runs Chapter 7: Conclusion Figure 7. 1 Design Runs 7.2 Summery Figure 7. 2 Summery 7.3 Timing Summery Figure 7. 3 Timing Summery 33

43 7.4 Schematic Figure 7. 4 Schematic of the design 34

44 Chapter 8: VHDL Code 8.1 Top Level Wrapper library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity vid_top is Port ( ---- INPUTS clk : in STD_LOGIC; rst : in STD_LOGIC; resolution_sel : in STD_LOGIC_VECTOR(7 downto 0); ); end vid_top; ---- OUTPUTS vga_red : out STD_LOGIC_VECTOR (3 downto 0); vga_green : out STD_LOGIC_VECTOR (3 downto 0); vga_blue : out STD_LOGIC_VECTOR (3 downto 0); vga_hsync : out STD_LOGIC; vga_vsync : out STD_LOGIC architecture Behavioral of vid_top is ---- Component Declaration component vid_test_ball is Port ( ---- INPUTS sys_clk : in STD_LOGIC; rst : in STD_LOGIC; resolution_sel : in STD_LOGIC_VECTOR(1 downto 0); ---- OUTPUTS vga_red : out STD_LOGIC_VECTOR (3 downto 0); vga_green : out STD_LOGIC_VECTOR (3 downto 0); vga_blue : out STD_LOGIC_VECTOR (3 downto 0); vga_hsync : out STD_LOGIC; vga_vsync : out STD_LOGIC); end component; signal vga_red_ball : STD_LOGIC_VECTOR(3 downto 0); signal vga_green_ball : STD_LOGIC_VECTOR(3 downto 0); signal vga_blue_ball : STD_LOGIC_VECTOR(3 downto 0); signal vga_hsync_ball : STD_LOGIC; 35

45 signal vga_vsync_ball: STD_LOGIC; component vid_test_pat_gen IS PORT( --- INPUT DECLARATIONS rst : IN std_logic; sys_clk : IN std_logic; pattern_sel : IN std_logic_vector (3 DOWNTO 0); resolution_sel : IN std_logic_vector (2 DOWNTO 0); --- OUTPUT DECLARATIONS hsync_out : OUT std_logic; vsync_out : OUT std_logic; video_r : OUT std_logic_vector (11 DOWNTO 0); video_g : OUT std_logic_vector (11 DOWNTO 0); video_b : OUT std_logic_vector (11 DOWNTO 0) ); END component; signal vga_red_pat : STD_LOGIC_VECTOR(11 downto 0); signal vga_green_pat : STD_LOGIC_VECTOR(11 downto 0); signal vga_blue_pat : STD_LOGIC_VECTOR(11 downto 0); signal vga_hsync_pat : STD_LOGIC; signal vga_vsync_pat : STD_LOGIC; signal sys_clk : STD_LOGIC; begin vid_test_ball_inst:vid_test_ball Port map( ---- INPUTS sys_clk => sys_clk, rst => rst, resolution_sel => resolution_sel(5 downto 4), ); ---- OUTPUTS vga_red => vga_red_ball, vga_green => vga_green_ball, vga_blue => vga_blue_ball, vga_hsync => vga_hsync_ball, vga_vsync => vga_vsync_ball vid_test_pat_gen_inst :vid_test_pat_gen Port map( 36

46 ); --- INPUT DECLARATIONS rst => rst, sys_clk => sys_clk, pattern_sel => resolution_sel(3 downto 0), resolution_sel => resolution_sel(6 downto 4), --- OUTPUT DECLARATIONS hsync_out => vga_hsync_pat, vsync_out => vga_vsync_pat, video_r => vga_red_pat, video_g => vga_green_pat, video_b => vga_blue_pat vga_red <= vga_red_ball when resolution_sel(7) = '0' else vga_red_pat(3 downto 0); vga_green <= vga_green_ball when resolution_sel(7) = '0' else vga_green_pat(3 downto 0); vga_blue <= vga_blue_ball when resolution_sel(7) = '0' else vga_blue_pat(3 downto 0); vga_hsync <= vga_hsync_ball when resolution_sel(7) = '0' else vga_hsync_pat; vga_vsync <= vga_vsync_ball when resolution_sel(7) = '0' else vga_vsync_pat; end Behavioral; 8.2 Ball Top Level, vid_test_ball library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity vid_test_ball is Port ( ---- INPUTS sys_clk : in STD_LOGIC; rst : in STD_LOGIC; resolution_sel : in STD_LOGIC_VECTOR(1 downto 0); ---- OUTPUTS vga_red : out STD_LOGIC_VECTOR (3 downto 0); vga_green : out STD_LOGIC_VECTOR (3 downto 0); vga_blue : out STD_LOGIC_VECTOR (3 downto 0); vga_hsync : out STD_LOGIC; vga_vsync : out STD_LOGIC); end vid_test_ball; 37

47 ---- SIGNAL DECLARATION signal red_sig : STD_LOGIC; signal green_sig : STD_LOGIC; signal blue_sig : STD_LOGIC; signal vsync_sig : STD_LOGIC; signal row_sig : STD_LOGIC_VECTOR (11 downto 0); signal column_sig : STD_LOGIC_VECTOR (11 downto 0); ---- COMPONENT DECLARATION component ball is Port ( vsync : in STD_LOGIC; row : in STD_LOGIC_VECTOR(11 downto 0); column : in STD_LOGIC_VECTOR(11 downto 0); red : out STD_LOGIC; green : out STD_LOGIC; blue : out STD_LOGIC); end component; component vga_sync is Port ( sys_clk : in STD_LOGIC; rst : in STD_LOGIC; resolution_sel : in STD_LOGIC_VECTOR(1 downto 0); red : in STD_LOGIC; green : in STD_LOGIC; blue : in STD_LOGIC; red_out : out STD_LOGIC; green_out : out STD_LOGIC; blue_out : out STD_LOGIC; hsync : out STD_LOGIC; vsync : out STD_LOGIC; row : out STD_LOGIC_VECTOR (11 downto 0); column : out STD_LOGIC_VECTOR (11 downto 0)); end component; signal r,g,b: std_logic; begin vga_red <= r & r & r & r; vga_green <= g & g & g & g; vga_blue <= b & b & b & b; ---- INSTNTIATE BALL COMPONENT 38

48 add_ball: ball port map( vsync => vsync_sig, row => row_sig, column => column_sig, red => red_sig, green => green_sig, blue => blue_sig); ---- INSTANTIATE VGA_SYNC COMPONENT vga_driver: vga_sync port map( sys_clk rst resolution_sel red green ---- Connecting up the outputs vga_vsync <= vsync_sig; end Behavioral; => sys_clk, => rst, => resolution_sel, => red_sig, => green_sig, => blue_sig, blue red_out => r, green_out => g, blue_out => b, row column hsync vsync => row_sig, => column_sig, => vga_hsync, => vsync_sig); 8.3 Ball Sync Generator library IEEE; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.all; entity vga_sync is Port ( ---- INPUTS sys_clk rst : in STD_LOGIC; : in STD_LOGIC; resolution_sel : in STD_LOGIC_VECTOR(1 downto 0); red : in STD_LOGIC; 39