Traversing Digital Design. EECS Components and Design Techniques for Digital Systems. Lec 22 Sequential Logic - Advanced

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1 Traversing igital esign EEC 5 - Components and esign Techniques for igital ystems EEC5 wks 6-5 Lec 22 equential Logic - Advanced avid Culler Electrical Engineering and Computer ciences University of California, Berkeley equential Circuit esign and Timing EEC5 wks -6 EE 4 C6C TL & IA Types of Latches We have focused on -flips latch => FlipFlop => egisters (ld, clr) Most commonly used today (CMO, FPGA) Many other types of latches, JK, T hould be familiar with these too Opportunity to look much more closely at timing behavior Latch vs Flip Flops Timing Methodology

2 ecall: Forms of equential Logic Asynchronous sequential logic state changes occur whenever state inputs change (elements may be simple wires or delay elements) ynchronous sequential logic state changes occur in lock step across all storage elements (using a periodic waveform - the ) Example ring oscillator A B C E X Period of epeating Waveform ( tp) Gate elay ( td) A (=X) B C E (b) Timing waveform ecall: General Model of ynchronous Circuit Circuits with Feedback input How to control feedback? What stops values from cycling around endlessly input CL reg CL reg output option feedback output Our methodology so far: registers as flipflops with common control ingle-phase, edge triggered design input T su T h X X2 Xn switching network Z Z2 Zn Assumptions underlying the clean abstraction Input to FF valid a setup time before edge Outputs don t change too quickly after edge (hold time)» Clk-to- => hold time

3 implest Circuits with Feedback Latches Two inverters form a static memory cell Will hold value as long as it has power applied "data" "load" "" "" "remember" "stored value" How to get a new value into the memory cell? electively break feedback path Load new value into cell "stored value" Level-sensitive latch holds value when is low Transparent when is high What does it take to build a consistent timing methodology with only latches? Very hard! All stages transparent at same time. equire that minimum propagation delay is greater than high phase of the (duty period) in a b a b s Two-phase non-overlapping s Used to keep time Wait long enough for inputs (' and ') to settle Then allow to have effect on value stored s are regular periodic signals Period (time between ticks) uty-cycle (time is high between ticks - expressed as % of period) period duty cycle (in this case, 5%) equential elements partition into two classes phase ele ts feed phase phase ele ts feed phase Approximate single phase: each register replaced by a pair of latches on two phases Can push logic across (retiming) Can always slow down the s to meet all timing constraints in a b a b c/l -

4 Master-lave tructure Latches vs FlipFlips Level sensitive vs edge triggered Very different design methodologies for correct use Both are ed, but latch is asynchronous Output can change while is high setup time to delay Construct flipflop from two latches Clk FF Latch Asynchronous - Latch Cross-coupled NO gates imilar to inverter pair, with capability to force output to (reset=) or (set=) ' ' ' ' Cross-coupled NAN gates imilar to inverter pair, with capability to force output to (reset=) or (set=) ' ' tate Behavior of - latch Transition Table (t) (t) (t) (t+δ) hold reset set X not allowed X equential (output depends on history when inputs =, =) but asynchronous (t) characteristic equation (t+δ) = + (t) X X '

5 Theoretical - Latch Behavior Timing Behavior ' = = ' = = = = ' = = ' tate iagram tates: possible values Transitions: changes based on inputs possible oscillation between states and = = = = ' ' = = = = \ eset Hold et eset et ace Observed - Latch Behavior - Latch Analysis Very difficult to observe - latch in the - state One of or usually changes first Ambiguously returns to state - or - A so-called "race condition" Or non-deterministic transition Break feedback path ' (t) (t+δ) = = = ' = = = = = ' = = ' = = = (t) (t+δ) X X hold reset set not allowed (t) X X characteristic equation (t+δ) = + (t)

6 Gated - Latch Towards a ynchronous esign Control when and inputs matter Otherwise, the slightest glitch on or while enable is low could cause change in value stored Ensure & stable before utilized (to avoid transient =, =) ' ' enable' ' et ' enable' ' eset ' Controlling an - latch with a Can't let and change while is active (allowing and to pass) Only have half of period for signal changes to propagate ignals must be stable for the other half of period ' ' ' ' and ' ' stable changing stable changing stable Cascading Latches Announcements Connect output of one latch to input of another How to stop changes from racing through chain? Need to control flow of data from one latch to the next Advance from one latch per period Worry about logic between latches (arrows) that is too fast» hortest paths, not critical paths ' ' Guest Lecture, Nov 29, r. obert Iannucci, CTO Nokia arah Lecture on Testing Methodology Thurs. HW out tonight, due before Break Lab lecture covers final point Wireless CP this week Next week TAs will do extended office hours M-W rather than formal lab. Final Check off week 4 No Class ec 6. Final report Friday ec. 7. ign up for min slots 5 min presentation, 5 min &A Arrive 2 mins before scheduled slot to set up

7 Master-lave tructure Break flow by alternating s (like an air-lock) Use positive to latch inputs into one - latch Use negative to change outputs with another - latch View pair as one basic unit master-slave flip-flop twice as much logic output changes a few gate delays after the falling edge of but does not affect any cascaded flip-flops master stage P' ' P slave stage ' P P' ' The s Catching Problem In first - stage of master-slave FF -- glitch on or while is high "caught" by master stage Leads to constraints on logic (feeding the latch) to be hazardfree et eset s catch Master Outputs lave Outputs master stage P' ' P slave stage ' Flip-Flop JK Flip Flops Make and complements of each other in Master stage Eliminates s catching problem» Input only needs to settle by edge Can't just hold previous value (must have new value ready every period) Value of just before goes low is what is stored in flipflop Can make - flip-flop by adding logic to make = + ' master stage slave stage J(t) K(t) (t) (t+δ) hold reset set toggle K J - master/slave P' ' ' ' P gates

8 (neg) Edge-Triggered Flip-Flops Edge-Triggered Flip-Flops (cont d) Clk= More efficient solution: only 6 gates sensitive to inputs only near edge of signal (not while high) holds ' when goes low holds when goes low negative edge-triggered flip-flop (-FF) 4-5 gate delays must respect setup and hold time constraints to successfully capture input characteristic equation (t+) = =, Clk High Clk= Act as inverters Hold state Edge-Triggered Flip-Flops (cont d) -FF Behavior when = =, Clk High Clk= u -> -> u Clk= l u =u =l -> -> Change in propagate through lower and upper latch, but ==, isolating slave

9 Behavior when -> -FF; behavior when == Clk= -> u u l -> -> u -> =u Clk= ->~ = ==old Lower output Upper latch retains old unchanged =l new new old -> Falling edge allows latched to propagate to output latch when is low data is held Edge-Triggered Flip-Flops (cont d) Timing Methodologies Positive edge-triggered Inputs sampled on rising edge; outputs change after rising edge Negative edge-triggered flip-flops Inputs sampled on falling edge; outputs change after falling edge pos pos' neg neg' positive edge-triggered FF negative edge-triggered FF ules for interconnecting components and s Guarantee proper operation of system when strictly followed Approach depends on building blocks used for memory elements Focus on systems with edge-triggered flip-flops» Found in programmable logic devices Many custom integrated circuits focus on level-sensitive latches Basic rules for correct timing: () Correct inputs, with respect to time, are provided to the flip-flops (2) No flip-flop changes state more than once per ing event

10 Timing Methodologies (cont d) efinition of terms : periodic event, causes state of memory element to change; can be rising or falling edge, or high or low level setup time: minimum time before the ing event by which the input must be stable (Tsu) hold time: minimum time after the ing event until which the input must remain stable (Th) input T su T h there is a timing "window" around the ing event during which the input must remain stable and unchanged in order to be recognized data data stable changing Comparison of Latches and Flip- Flops (cont d) Type When inputs are sampled When output is valid uned always propagation delay from input change latch level-sensitive high propagation delay from input change latch (Tsu/Th around falling or edge (whichever is later) edge of ) master-slave high propagation delay from falling edge flip-flop (Tsu/Th around falling of edge of ) negative hi-to-lo transition propagation delay from falling edge edge-triggered (Tsu/Th around falling of flip-flop edge of ) Typical Timing pecifications Positive edge-triggered flip-flop etup and hold times Minimum width Propagation delays (low to high, high to low, max and typical) Cascading Edge-triggered Flip-Flops hift register New value goes into first stage While previous value of first stage goes into second stage Consider setup/hold/propagation delays (prop must be > hold) Tsu 2ns Th 5ns Tsu 2ns Th 5ns IN OUT Tw 25ns Tplh 25ns 3ns Tphl 4ns 25ns IN all measurements are made from the ing event that is, the rising edge of the

11 Cascading Edge-triggered Flip-Flops (cont d) Why this works Propagation delays exceed hold times width constraint exceeds setup time This guarantees following stage will latch current value before it changes to new value kew The problem Correct behavior assumes next state of all storage elements determined by all storage elements at the same time This is difficult in high-performance systems because time for to arrive at flip-flop is comparable to delays through logic Effect of skew on cascaded flip-flops: In T su 4ns T p 3ns T su 4ns T p 3ns timing constraints guarantee proper operation of cascaded components assumes infinitely fast distribution of the In original state: IN =, =, = due to skew, next state becomes: =, =, and not =, = is a delayed version of T h 2ns T h 2ns Need Propagation kew > Hold Time ummary of Latches and Flip-Flops evelopment of -FF Level-sensitive used in custom integrated circuits» can be made with 4 pairs of gates» Usually follows multiphase non-overlapping discipline Edge-triggered used in programmable logic devices Good choice for data storage register Historically J-K FF was popular but now never used imilar to - but with - being used to toggle output (complement state) Good in days of TTL/I (more complex input function: = J' + K' Not a good choice for PALs/PLAs as it requires 2 inputs Can always be implemented using -FF Preset and clear inputs are highly desirable on flip-flops Used at start-up or to reset system to a known state Flip-Flop Features eset (set state to ) ynchronous: new = ' old (when next edge arrives) Asynchronous: doesn't wait for, quick but dangerous Preset or set (set state to ) (or sometimes P) ynchronous: new = old + (when next edge arrives) Asynchronous: doesn't wait for, quick but dangerous Both reset and preset new = ' old + (set-dominant) new = ' old + ' (reset-dominant) elective input capability (input enable/load) L or EN Multiplexer at input: new = L' + L old Load may/may not override reset/set (usually / have priority) Complementary outputs and '

12 Maintaining the igital Abstraction (in an analog world) Circuit design with very sharp transitions Noise margin for logical values Carefully esign torage Elements (E) Internal feedback tructured ystem esign E + CL, cycles must cross E Timing Methodology All E advance state together All inputs stable across state change V dd V out V in V dd Where does this breakdown? Interfacing to the physical world Can t tell it not to change near the edge igital Abstraction input input CL reg CL reg output option feedback output Example Problems Metastability Async Input ed ynchronous ystem Async Input ynchronizer In worst cast, cannot bound time for FF to decide if inputs can change right on the edge Circuit has a metastable balance point horrible example In? In In is asynchronous and fans out to and one FF catches the signal, one does not inconsistent state may be reached! logic logic

13 Practical olution Metastability throughout the ages Async Input ynchronizer eries of synchronizers each reduces the chance of getting stuck (exponentially) Make P(metastability) < P(device failure) Oversample and then low pass Buridan, Jean (3-58), French cholastic philosopher, who held a theory of determinism, contending that the will must choose the greater good. Born in Bethune, he was educated at the University of Paris, where he studied with the English cholastic philosopher William of Ocham. After his studies were completed, he was appointed professor of philosophy, and later rector, at the same university. Buridan is traditionally but probably incorrectly associated with a philosophical dilemma of moral choice called "Buridan's ass." In the problem an ass starves to death between two alluring bundles of hay because it does not have the will to decide which one to eat. idn t take EEC 5