CHAPTER 6 COUNTERS & REGISTERS
|
|
|
- Allyson Jones
- 6 years ago
- Views:
Transcription
1 CHAPTER 6 COUNTERS & REGISTERS 6.1 Asynchronous Counter 6.2 Synchronous Counter 6.3 State Machine 6.4 Basic Shift Register 6.5 Serial In/Serial Out Shift Register 6.6 Serial In/Parallel Out Shift Register 6.7 Parallel In/Serial Out Shift Register 6.8 Parallel In/Parallel Out Shift Register
2 Lecture Outcomes At the end of this chapter student should be able to:- Differentiate the different type of counters Understanding the basic design steps to design any type of counters Differentiate between Moore & Mealy Machine (FSM) Understanding the FSM design steps (Moore/Mealy) Differentiate between various type of registers available (SISO/SIPO/PISO/PIPO) Understanding the registers design steps
3 6.1 Asynchronous Counter Revision: The rule to determine the number of FF is Example: Design a MOD-8 asynchronous counter. No of JK flip-flop = antilog 2 8 = 3 To build this counter, two ICs (contains 2 JK flipflops) are used.
4 The circuit connection for MOD-8 using ICs is J,K = 1 for toggle operation PRE, CLR = 1 for synchronisation
5 Counter with MOD number other than 2 n Example : Design a MOD-10 Counter There are 4 steps involved: 1. Determine the number of JK flip-flops needed 2. Determine the reset logic 3. Draw the block diagram 4. Circuit implementation.
6 Step 1 :Determine the number of JK flip-flops needed For MOD 10 (a.k.a. Decade Counter) Number 10 (decimal) in binary is there are 4 bits It requires 4 JK flip-flops
7 Step 2 :Determine the reset We know that 4 JK flip-flops is actually used in building MOD 16 (i.e. from 0000 to 1111). Thus, to make these 4 flip-flops to act as a MOD 10 (i.e. counting from 0000 to 1001), a reset circuitry is added. after it reaches 1001, the reset circuit is ON and JK flip-flops are cleared using CLR.
8 Maximum number of MOD-10 counter is 9. After 9 10 (1001) is number (1010) QB and QD are 1 s. RESET happens only when both QB and QD are HIGH AND configuration however, CLR is an active-low input, invert AND configuration NAND gate
9 Step 3 :Draw the block diagram The block diagram of MOD 10 counter is reset part
10 The waveform of MOD 10 counter is The glitch is due to the output is becoming 1010 for a short period of time before CLR. The delay in setting CLR is due to propagation delay of the NAND gate.
11 Step 4 :Circuit Implementation Circuit is implemented using 2 ICs of 74112
12 We could also implement a MOD-10 counter using IC (contains 4 JK flip-flops) Need to be connected externally
13 MOD 10 circuit implementation using IC 74293
14 Count-down Asynchronous Counter So far, all the counters are count-up counter. To implement count-down counter, the connection needs to be modified. 1. CLK pulses are supplied by Q 2. The Q A, Q B etc are taken from Q output. Example: MOD 8 count-down type counter
15 The waveform for MOD 8 count down counter is
16 6.2 Synchronous Counter Main problem of asynchronous counter is delay Due to the signals are rippled from one flip-flop into another Synchronous counter (a.k.a Parallel Counter) This synchronous counter has a common clock signal outputs change at the same time The inputs J & K need to be controlled so that they are toggled at specific time only. To do this, need to examine the counting steps table.
17 Example : MOD 16 Synchronous Counter COUNT Q D (MSB) Q C Q B Q A (LSB) Q A always toggle J1,K1 = 1 Q B always toggle at triggering edge when Q A =1 J2,K2 = Q A. Q C always toggle at triggering edge when Q A & Q B = 1 J3,K3 = Q A Q B. Q D always toggle at triggering edge when Q A & Q B & Q C = 1 J4,K4 = Q A Q B Q C.
18 Therefore, the circuit for MOD 16 synchronous counter is Q A Q A Q B Q C 1 Q A Q B
19 Synchronous Counter with MOD number other than 2 n Use asynchronous input CLR to reset the counter. Example: MOD 10 synchronous counter Same as MOD 10 asynchronous counter, i.e. Q D & Q B are 1 s.
20 Presettable Synchronous Counter Many synchronous counters (ICs) are presettable they can be preset to any desired starting count either asynchronously or synchronously. this operation is also called PARALLEL LOADING To load the counter with any desired count at one time: 1. Apply the desired count to the parallel inputs 2. Apply a LOW pulse to the PARALLEL LOAD input, PE
21 Example: 4-bit Presettable Synchronous Counter is Parallel inputs are P0, P1, P2 & P3. The NAND gates connected to them act as enable gate. What would be the counter s output if the PE is hold at low and the values of P0, P1, P2 & P3 are 1, 1, 0 & 0 respectively?
22 Count-down Synchronous Counter In section 6.1, the count-down counter is modified from the count-up counter. From these, we can design an up/down counter
23 6.3 State Machine State machine (also called as a sequential circuit) can be viewed as a synchronous counter with irregular sequence. There two types of state machines: 1. Moore machine Next state (output) depends on the present internal state only. 2. Mealy machine Next state (output) depends on the present internal state and also input at that particular of time.
24 Design of a state machine 1. State diagram A diagram that shows all the transition of states when clock is triggered. Number of FF = number of bits 2. Next state table Listing of all the present state along with its next state. 3. Excitation table Listing of all the JK connections of all FFs for the next state transition to occur. 4. K-map Determine the simplified logic expression for all J & K 5. Circuit implementation
25 Moore Machine Example: Design a 3-bit counter with this sequence,000,001,011,010,110,111,101,100,000, Solution STEP 1: State diagram Since this is a 3-bit counter 3 JK flip-flops are needed.
26 STEP 2: Next state table The present state is arranged in incremental binary counting order although the sequence of the counter is not.
27 STEP 3: Excitation table By referring to JK flip-flop transition table The excitation table is:
28 STEP 4: K-map
29 STEP 5: Circuit Implementation
30 Mealy Machine The present output from Mealy state machine depends on both the present input and the previous output. Thus, the present input needs to be considered too. Example: Design an up/down 3-bit Gray code counter. If input Y is low, the counter will perform count down operation else the counter will perform count up operation.
31 Solution STEP 1: State diagram Since this is a 3-bit counter 3 JK flip-flops are needed.
32 STEP 2: Next state table The present state is arranged in incremental binary counting order although the sequence of the counter is not.
33 STEP 3: Excitation table The excitation table is: (refer to JK FF transition table) Present State Input Next state C FF B FF A FF QC QB QA Y QC QB QA JC KC JB KB JA KA X 0 X 0 X X 0 X 1 X X 0 X X X 1 X X X X 0 1 X X X 0 0 X X X 1 X X X 0 X X 0 0 X 1 X X 1 0 X 0 X X 0 1 X X X 0 0 X X X 1 X 0 0 X X 0 X 0 1 X X 0 X 0 X X 0 X 1 X 0
34 STEP 4: K-map For C flip-flop J C = Q B Q A Y + Q B Q A Y =Q A (Q B Y) K C Q C Q B Q A Y 00 X X X X X X X X 0 0 J C Q B Q A Y Q B Q A Y Q C Q B Q A Y X X Q B Q A Y X X X X X X Q B Q A Y K C = Q B Q A Y + Q B Q A Y =Q A (Q B Y)
35 STEP 4: K-map (cont.) For B flip-flop J B = Q C Q A Y + Q C Q A Y =Q A (Q C Y) K B Q C Q B Q A Y 00 X 0 0 X Q C Q A Y Q C Q A Y J B Q C Q B Q A Y 00 0 X X X X X X X X 1 01 X 0 0 X 11 X 0 1 X 10 X 1 0 X Q C Q A Y Q C Q A Y K B = Q C Q A Y + Q C Q A Y =Q A (Q C Y)
36 STEP 4: K-map (cont.) For A flip-flop J A = Q C Q B Y + Q C Q B Y + Q C Q B Y + Q C Q B Y = Q C Q B Y J A Q C Q B Q A Y X X X X K A Q C Q B Q A Y 00 X X X X 01 X X X X X X X X K A = Q C Q B Y + Q C Q B Y + Q C Q B Y + Q C Q B Y = Q C Q B Y
37 STEP 5: Circuit Implementation
38 Register A register is a digital circuit with two basic functions: data storage } memory device data movement. } shift capability in transferring data The concept of data storing in D flip-flop When a 1 is on D, Q becomes a 1 at the rising edge of CLK. When the 1 on D is removed, Q still remains high (1). The storage capacity of a register is the total number of bits of data it can retain.
39 6.4 Basic Shift Register A shift register is a register in which the stored data can be shifted to the left or right. or a group of flip-flops arranged so that the binary numbers stored in the flip-flops are shifted from one flip-flop to the next for every clock cycle (ref: Tocci). Important in applications involving the storage and transfer of data.
40 There are several types of data movement in shift registers Serial In/Serial Out SISO Rotate left Rotate right
41 More on types of data movement in shift registers Parallel In/Serial Out PISO Serial In/ Parallel Out SIPO Parallel In/ Parallel Out PIPO
42 6.5 Serial In/Serial Out (SISO) Shift Register SISO register receives data serially, shift it and then output the data serially. The shift operation may be a shift right or left or both depending on the design.
43 4-bit SISO register (right shift) 4-bit register 4 D flip-flops (with PGT edge trigger) A FF B FF C FF D FF The first data is input to the A FF. Then, the data is moved to B FF followed by C FF before it finally reach D FF meaning 4-bit register takes 4 clock cycles to store 4-bits data.
44 4-bit SISO (right shift): storing operation Say, binary data of 1001 are to be stored in the SISO. Initially, the register is cleared (i.e. it contains 0000) At the FIRST rising edge of clock pulse, The LSB (1) is entered first because this is a right shift SISO.
45 At the SECOND rising edge of clock pulse, At the THIRD rising edge of clock pulse, At the FOURTH rising edge of clock pulse,
46 Now, all the bits are stored in this register. They are stored for any length of time as long as the flip-flops have dc power.
47 4-bit SISO (right shift): getting back the data Previously, binary data of 1001 are stored in the SISO. To get these data out, new 4-bit data (say, 0000 to clear the register) need to be entered. Data is read at Q D. The LSB is already at Q D.
48 At the FIRST (or FIFTH) rising edge of clock pulse, At the SECOND (or SIXTH) rising edge of clock pulse, At the THIRD (or SEVENTH) rising edge of clock pulse, Now, a complete set of data has been retrieved
49 Though the data have been completely retrieved, the register is not completely cleared yet. Q D still retains the MSB of the data. At the FOURTH (or EIGHTH) rising edge of clock pulse, Now, all the flip-flops are cleared. From here, we can see that it takes 8 clock cycles to completely clear the register.
50 6.6 Serial In/Parallel Out (SIPO) Shift Register SIPO register receives data serially, shift it and then output the data in parallel manner. In parallel output register, the output of each stage is externally accessible. Once the data are stored, each bit appears on its respective output line.
51 4-bit SIPO register 4-bit register 4 D flip-flops (with PGT edge trigger) A FF B FF C FF D FF The first data is input to the A FF. Then, the data is moved to B FF followed by C FF before it finally reach D FF meaning 4-bit register takes 4 clock cycles to store 4- bits data.
52 Operation of SIPO In storing operation, refer to SISO (as the data are stored in the same manner) Initially, the register is cleared (i.e. it contains 0000) At the FIRST rising edge of clock pulse, Here, LSB (1) is entered first.
53 At the SECOND rising edge of clock pulse, At the THIRD rising edge of clock pulse,
54 At the FOURTH rising edge of clock pulse, Now, a complete set of data has been stored. It will remain in this register until a dc power is turned off or the clock pulse is applied. At the same time, the data stored in this register can be retrieved.
55 74LS164: 8-bit SIPO shift register
56 The internal circuitry of the IC is: Questions: 1. If MSB is entered first, which of the output is the MSB after the 8 th clock cycle? 2. How to use this IC as a SISO?
57 6.7 Parallel In/Serial Out (PISO) Shift Register Parallel in allows a complete set of data to be entered at one time. PISO register receives data in parallel manner and then output the data in serial manner (shifting operation is done in between). PISO has a SHIFT/LOAD to set the operation mode.
58 4-bit PISO register 4-bit register 4 D flip-flops (with PGT edge trigger) A FF B FF C FF D FF The data are loaded to the A, B, C and D FFs simultaneously. SHIFT/LOAD input line is used to select the mode of the register.
59 Operation of PISO When SHIFT/LOAD is LOW Data are loaded into the respective FFs at the triggering edge (as AND gates of 1,3,5 & 7 are enabled). HIGH Data are shifted from one FF to the next at a triggering edge (as AND gates of 2,4 & 6 are enabled).
60 74LS165: 8-bit PISO shift register Clocking is provided through 2-input OR gate, where one input is used as a clock-inhibit function. The function of this IC is Inputs SH/LD CP CP INH Operation L X X Parallel load H H X No change H X H No change H L Shifting H L Shifting
61 The internal circuitry of the IC is: Question: How to use this IC as a SISO?
62 6.8 Parallel In/Parallel Out (PIPO) Shift Register PIPO allows a complete set of data to be entered simultaneously and after a triggering edge, these data are ready to be read out. If you refer back to Chapter 1, parallel data transmission is faster than serial data transmission.
63 4-bit PIPO register 4-bit register 4 D flip-flops (with PGT edge trigger) A FF B FF C FF D FF The data are loaded to the A, B, C and D FFs simultaneously. The data are retrieved at Q A, Q B, Q C and Q D respectively.
64 74LS195: 4-bit PIPO shift register SHIFT/LOAD input line LOW the data on the parallel inputs are entered synchronously on PGT of the clock pulse HIGH the stored data will shift right (Q0 Q3) synchronously on PGT of the clock pulse Active-low CLR is asynchronous.
65 The internal circuitry of the IC is: Question: How to use JK inputs as a Serial Data In?
66
DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS
COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) COUNTERS One common requirement in digital circuits is counting, both forward and backward. Digital clocks and
Module -5 Sequential Logic Design
Module -5 Sequential Logic Design 5.1. Motivation: In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on
Counters
Counters A counter is the most versatile and useful subsystems in the digital system. A counter driven by a clock can be used to count the number of clock cycles. Since clock pulses occur at known intervals,
Chapter 7 Counters and Registers
Chapter 7 Counters and Registers Chapter 7 Objectives Selected areas covered in this chapter: Operation & characteristics of synchronous and asynchronous counters. Analyzing and evaluating various types
Scanned by CamScanner
NAVEEN RAJA VELCHURI DSD & Digital IC Applications Example: 2-bit asynchronous up counter: The 2-bit Asynchronous counter requires two flip-flops. Both flip-flop inputs are connected to logic 1, and initially
SEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur
SEQUENTIAL LOGIC Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur www.satish0402.weebly.com OSCILLATORS Oscillators is an amplifier which derives its input from output. Oscillators
VTU NOTES QUESTION PAPERS NEWS RESULTS FORUMS Registers
Registers Registers are a very important digital building block. A data register is used to store binary information appearing at the output of an encoding matrix.shift registers are a type of sequential
UNIT-3: SEQUENTIAL LOGIC CIRCUITS
UNIT-3: SEQUENTIAL LOGIC CIRCUITS STRUCTURE 3. Objectives 3. Introduction 3.2 Sequential Logic Circuits 3.2. NAND Latch 3.2.2 RS Flip-Flop 3.2.3 D Flip-Flop 3.2.4 JK Flip-Flop 3.2.5 Edge Triggered RS Flip-Flop
Sequential Logic Basics
Sequential Logic Basics Unlike Combinational Logic circuits that change state depending upon the actual signals being applied to their inputs at that time, Sequential Logic circuits have some form of inherent
EET2411 DIGITAL ELECTRONICS
5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input
Universal Asynchronous Receiver- Transmitter (UART)
Universal Asynchronous Receiver- Transmitter (UART) (UART) Block Diagram Four-Bit Bidirectional Shift Register Shift Register Counters Shift registers can form useful counters by recirculating a pattern
Analysis of Sequential Circuits
NOTE: Explanation Refer lass Notes Digital ircuits(15ee23) Analysis of Sequential ircuits by Nagaraj Vannal, Asst.Professor, School of Electronics Engineering,.L.E. Technological University, Hubballi.
Experiment 8 Introduction to Latches and Flip-Flops and registers
Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends
Asynchronous (Ripple) Counters
Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced
EKT 121/4 ELEKTRONIK DIGIT 1
EKT 2/4 ELEKTRONIK DIGIT Kolej Universiti Kejuruteraan Utara Malaysia Sequential Logic Circuits - COUNTERS - LATCHES (review) S-R R Latch S-R R Latch Active-LOW input INPUTS OUTPUTS S R Q Q COMMENTS Q
Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1
2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The
Sequential Digital Design. Laboratory Manual. Experiment #7. Counters
The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #7 Counters Objectives
DIGITAL REGISTERS. Serial Input Serial Output. Block Diagram. Operation
DIGITAL REGISTERS http://www.tutorialspoint.com/computer_logical_organization/digital_registers.htm Copyright tutorialspoint.com Flip-flop is a 1 bit memory cell which can be used for storing the digital
Digital Fundamentals: A Systems Approach
Digital Fundamentals: A Systems Approach Counters Chapter 8 A System: Digital Clock Digital Clock: Counter Logic Diagram Digital Clock: Hours Counter & Decoders Finite State Machines Moore machine: One
Serial In/Serial Left/Serial Out Operation
Shift Registers The need to storage binary data was discussed earlier. In digital circuits multi-bit data has to be stored temporarily until it is processed. A flip-flop is able to store a single binary
Flip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari
Sequential Circuits The combinational circuit does not use any memory. Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory
EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP
EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications
RS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
UNIVERSITI TEKNOLOGI MALAYSIA
SULIT Faculty of Computing UNIVERSITI TEKNOLOGI MALAYSIA FINAL EXAMINATION SEMESTER I, 2016 / 2017 SUBJECT CODE : SUBJECT NAME : SECTION : TIME : DATE/DAY : VENUES : INSTRUCTIONS : Answer all questions
Review of digital electronics. Storage units Sequential circuits Counters Shifters
Review of digital electronics Storage units Sequential circuits ounters Shifters ounting in Binary A counter can form the same pattern of 0 s and 1 s with logic levels. The first stage in the counter represents
Chapter 4. Logic Design
Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table
LATCHES & FLIP-FLOP. Chapter 7
LATCHES & FLIP-FLOP Chapter 7 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely
Logic and Computer Design Fundamentals. Chapter 7. Registers and Counters
Logic and Computer Design Fundamentals Chapter 7 Registers and Counters Registers Register a collection of binary storage elements In theory, a register is sequential logic which can be defined by a state
ASYNCHRONOUS COUNTER CIRCUITS
ASYNCHRONOUS COUNTER CIRCUITS Asynchronous counters do not have a common clock that controls all the Hipflop stages. The control clock is input into the first stage, or the LSB stage of the counter. The
Counter dan Register
Counter dan Register Introduction Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory.
Asynchronous Counter
Asynchronous Counter Contents: Asynchronous/Ripple Counter Propagation Delay in Ripple Counter MOD Number Synchronous/Parallel Counter 10101010101010101010101010101010101010101010101010101010101010101010101010101010
Slide 1. Flip-Flops. Cross-NOR SR flip-flop S R Q Q. hold reset set not used. Cross-NAND SR flip-flop S R Q Q. not used reset set hold 1 Q.
Slide Flip-Flops Cross-NOR SR flip-flop Reset Set Cross-NAND SR flip-flop Reset Set S R reset set not used S R not used reset set 6.7 Digital ogic Slide 2 Clocked evel-triggered NAND SR Flip-Flop S R SR
TMEL53, DIGITALTEKNIK. INTRODUCTION TO SYNCHRONOUS CIRCUITS, FLIP-FLOPS and COUNTERS
LINKÖPING UNIVERSITY Department of Electrical Engineering TMEL53, DIGITALTEKNIK INTRODUCTION TO SYNCHRONOUS CIRCUITS, FLIP-FLOPS and COUNTERS Mario Garrido Gálvez mario.garrido.galvez@liu.se Linköping,
Digital Logic Design ENEE x. Lecture 19
Digital Logic Design ENEE 244-010x Lecture 19 Announcements Homework 8 due on Monday, 11/23. Agenda Last time: Timing Considerations (6.3) Master-Slave Flip-Flops (6.4) This time: Edge-Triggered Flip-Flops
RS flip-flop using NOR gate
RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two
Lecture 12. Amirali Baniasadi
CENG 24 Digital Design Lecture 2 Amirali Baniasadi amirali@ece.uvic.ca This Lecture Chapter 6: Registers and Counters 2 Registers Sequential circuits are classified based in their function, e.g., registers.
2. Counter Stages or Bits output bits least significant bit (LSB) most significant bit (MSB) 3. Frequency Division 4. Asynchronous Counters
2. Counter Stages or Bits The number of output bits of a counter is equal to the flip-flop stages of the counter. A MOD-2 n counter requires n stages or flip-flops in order to produce a count sequence
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall
YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in
Introduction. Serial In - Serial Out Shift Registers (SISO)
Introduction Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
Flip-Flops and Sequential Circuit Design
Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6
Chapter 2. Digital Circuits
Chapter 2. Digital Circuits Logic gates Flip-flops FF registers IC registers Data bus Encoders/Decoders Multiplexers Troubleshooting digital circuits Most contents of this chapter were covered in 88-217
Sequential circuits. Same input can produce different output. Logic circuit. William Sandqvist
Sequential circuits Same input can produce different output Logic circuit If the same input may produce different output signal, we have a sequential logic circuit. It must then have an internal memory
Decade Counters Mod-5 counter: Decade Counter:
Decade Counters We can design a decade counter using cascade of mod-5 and mod-2 counters. Mod-2 counter is just a single flip-flop with the two stable states as 0 and 1. Mod-5 counter: A typical mod-5
Chapter 6. Flip-Flops and Simple Flip-Flop Applications
Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic
Other Flip-Flops. Lecture 27 1
Other Flip-Flops Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two flip-flops less widely used in the design of digital systems are the JK and T flip-flops.
Digital Systems Laboratory 3 Counters & Registers Time 4 hours
Digital Systems Laboratory 3 Counters & Registers Time 4 hours Aim: To investigate the counters and registers constructed from flip-flops. Introduction: In the previous module, you have learnt D, S-R,
Sequential Logic Counters and Registers
Sequential Logic ounters and Registers ounters Introduction: ounters Asynchronous (Ripple) ounters Asynchronous ounters with MOD number < 2 n Asynchronous Down ounters ascading Asynchronous ounters svbitec.wordpress.com
Lecture 8: Sequential Logic
Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs
MODULE 3. Combinational & Sequential logic
MODULE 3 Combinational & Sequential logic Combinational Logic Introduction Logic circuit may be classified into two categories. Combinational logic circuits 2. Sequential logic circuits A combinational
Logic Design. Flip Flops, Registers and Counters
Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and
(Refer Slide Time: 2:00)
Digital Circuits and Systems Prof. Dr. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology, Madras Lecture #21 Shift Registers (Refer Slide Time: 2:00) We were discussing
Vignana Bharathi Institute of Technology UNIT 4 DLD
DLD UNIT IV Synchronous Sequential Circuits, Latches, Flip-flops, analysis of clocked sequential circuits, Registers, Shift registers, Ripple counters, Synchronous counters, other counters. Asynchronous
Chapter 3 Unit Combinational
EE 200: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Chapter 3 Unit Combinational 5 Registers Logic and Design Counters Part Implementation Technology
Registers and Counters
Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of
Flip-Flops and Related Devices. Wen-Hung Liao, Ph.D. 4/11/2001
Flip-Flops and Related Devices Wen-Hung Liao, Ph.D. 4/11/2001 Objectives Recognize the various IEEE/ANSI flip-flop symbols. Use state transition diagrams to describe counter operation. Use flip-flops in
IT T35 Digital system desigm y - ii /s - iii
UNIT - III Sequential Logic I Sequential circuits: latches flip flops analysis of clocked sequential circuits state reduction and assignments Registers and Counters: Registers shift registers ripple counters
Name: Date: Suggested Reading Chapter 7, Digital Systems, Principals and Applications; Tocci
Richland College Engineering Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Digital Fundamentals CETT 1425 Lab 7 Asynchronous Ripple Counters Name: Date: Objectives: To
NH 67, Karur Trichy Highways, Puliyur C.F, Karur District UNIT-III SEQUENTIAL CIRCUITS
NH 67, Karur Trichy Highways, Puliyur C.F, 639 114 Karur District DEPARTMENT OF ELETRONICS AND COMMUNICATION ENGINEERING COURSE NOTES SUBJECT: DIGITAL ELECTRONICS CLASS: II YEAR ECE SUBJECT CODE: EC2203
UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram
UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational
Logic Design Viva Question Bank Compiled By Channveer Patil
Logic Design Viva Question Bank Compiled By Channveer Patil Title of the Practical: Verify the truth table of logic gates AND, OR, NOT, NAND and NOR gates/ Design Basic Gates Using NAND/NOR gates. Q.1
Chapter 5: Synchronous Sequential Logic
Chapter 5: Synchronous Sequential Logic NCNU_2016_DD_5_1 Digital systems may contain memory for storing information. Combinational circuits contains no memory elements the outputs depends only on the inputs
Solution to Digital Logic )What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it,
Solution to Digital Logic -2067 Solution to digital logic 2067 1.)What is the magnitude comparator? Design a logic circuit for 4 bit magnitude comparator and explain it, A Magnitude comparator is a combinational
EKT 121/4 ELEKTRONIK DIGIT 1
EKT 121/4 ELEKTRONIK DIGIT 1 Kolej Universiti Kejuruteraan Utara Malaysia Bistable Storage Devices and Related Devices Introduction Latches and flip-flops are the basic single-bit memory elements used
Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers
EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and
Figure 30.1a Timing diagram of the divide by 60 minutes/seconds counter
Digital Clock The timing diagram figure 30.1a shows the time interval t 6 to t 11 and t 19 to t 21. At time interval t 9 the units counter counts to 1001 (9) which is the terminal count of the 74x160 decade
DIGITAL TECHNICS. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute
DIGITAL TECHNICS Dr. Bálint Pődör Óbuda University, Microelectronics and Technology Institute 7. LECTURE: REGISTERS, COUNTERS AND SERIAL ARITHMETIC CIRCUITS st (Autumn) term 208/209 7. LECTURE: REGISTERS,
Registers and Counters
Registers and Counters Clocked sequential circuit = F/Fs and combinational gates Register Group of flip-flops (share a common clock and capable of storing one bit of information) Consist of a group of
Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany
Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs
(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement
Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 7 (07 Feb 2008) 1 Announcement 2 1 Combinational vs. Sequential Logic Combinational Logic Memoryless Outputs
CHAPTER1: Digital Logic Circuits
CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback
CHAPTER 1 LATCHES & FLIP-FLOPS
CHAPTER 1 LATCHES & FLIP-FLOPS 1 Outcome After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output
Switching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS
Switching Theory And Logic Design UNIT-IV SEQUENTIAL LOGIC CIRCUITS Sequential circuits Classification of sequential circuits: Sequential circuits may be classified as two types. 1. Synchronous sequential
Digital Logic Design I
Digital Logic Design I Synchronous Sequential Logic Mustafa Kemal Uyguroğlu Sequential Circuits Asynchronous Inputs Combinational Circuit Memory Elements Outputs Synchronous Inputs Combinational Circuit
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Lab Manual for Computer Organization Lab
Digital Circuits ECS 371
igital Circuits ECS 371 r. Prapun Suksompong prapun@siit.tu.ac.th Lecture 17 Office Hours: BK 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,
Unit 11. Latches and Flip-Flops
Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,
Digital Circuit And Logic Design I. Lecture 8
Digital Circuit And Logic Design I Lecture 8 Outline Sequential Logic Design Principles (1) 1. Introduction 2. Latch and Flip-flops 3. Clocked Synchronous State-Machine Analysis Panupong Sornkhom, 2005/2
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter
Digital Circuit And Logic Design I
Digital Circuit And Logic Design I Lecture 8 Outline Sequential Logic Design Principles (1) 1. Introduction 2. Latch and Flip-flops 3. Clocked Synchronous State-Machine Panupong Sornkhom, 2005/2 2 1 Sequential
Counters. ENT 263 Digital Electronics
Counters ENT 263 Digital Electronics Objectives Describe the difference between an asynchronous and a synchronous counter Analyze counter timing diagram Analyze counter circuits Determine the sequence
The NOR latch is similar to the NAND latch
5-2 NOR Gate Latch The NOR latch is similar to the NAND latch except that the Q and Q outputs are reversed. The set and clear inputs are active high, that is, the output will change when the input is pulsed
1. Convert the decimal number to binary, octal, and hexadecimal.
1. Convert the decimal number 435.64 to binary, octal, and hexadecimal. 2. Part A. Convert the circuit below into NAND gates. Insert or remove inverters as necessary. Part B. What is the propagation delay
Sri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering
Sri Vidya College of Engineering And Technology Virudhunagar 626 005 Department of Electrical and Electronics Engineering Year/ Semester/ Class : II/ III/ EEE Academic Year: 2017-2018 Subject Code/ Name:
More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98
More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 98 Review: Bit Storage SR latch S (set) Q R (reset) Level-sensitive SR latch S S1 C R R1 Q D C S R D latch Q
ESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS. Kenneth R. Laker, University of Pennsylvania, updated 25Mar15
ESE 570 STATIC SEQUENTIAL CMOS LOGIC CELLS 1 Classes of Logic Circuits two stable op. pts. Latch level triggered. Flip-Flop edge triggered. one stable op. pt. One-shot single pulse output no stable op.
Introduction to Microprocessor & Digital Logic
ME262 Introduction to Microprocessor & Digital Logic (Sequential Logic) Summer 2 Sequential Logic Definition The output(s) of a sequential circuit depends d on the current and past states of the inputs,
LSN 12 Shift Registers
LSN 12 Shift Registers Department of Engineering Technology LSN 12 Shift Registers Digital circuits with data storage and data movement functions Storage capacity is the total number of bits of digital
Advanced Devices. Registers Counters Multiplexers Decoders Adders. CSC258 Lecture Slides Steve Engels, 2006 Slide 1 of 20
Advanced Devices Using a combination of gates and flip-flops, we can construct more sophisticated logical devices. These devices, while more complex, are still considered fundamental to basic logic design.
Final Exam review: chapter 4 and 5. Supplement 3 and 4
Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much
MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified)
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
WWW.STUDENTSFOCUS.COM + Class Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to Unit III 2. SKILLS ADDRESSED: Listening I year, 02 sem CS6201 Digital Principles
ELCT201: DIGITAL LOGIC DESIGN
ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter
Chapter 9 Counters. Clock Edge Output Q 2 Q 1 Q
hapter 9 ounters 9. Introduction ounters are devices which have a LOK input and produce n outputs. ounters consist of flip-flops connected together in specific ways such that on each clock edge the output
0 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 1 1 Stop bits. 11-bit Serial Data format
Applications of Shift Registers The major application of a shift register is to convert between parallel and serial data. Shift registers are also used as keyboard encoders. The two applications of the
Digital Fundamentals: A Systems Approach
Digital Fundamentals: A Systems Approach Latches, Flip-Flops, and Timers Chapter 6 Traffic Signal Control Traffic Signal Control: State Diagram Traffic Signal Control: Block Diagram Traffic Signal Control:
Objectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:
Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Rev. 3 (7/2015) J. Bradbury Digital Fundamentals CETT 1425 Lab 5 Latches & Flip-Flops
Chapter 5 Flip-Flops and Related Devices
Chapter 5 Flip-Flops and Related Devices Chapter 5 Objectives Selected areas covered in this chapter: Constructing/analyzing operation of latch flip-flops made from NAND or NOR gates. Differences of synchronous/asynchronous
Experiment # 9. Clock generator circuits & Counters. Digital Design LAB
Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 9 Clock generator circuits & Counters
MC9211 Computer Organization
MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the