Introduction to SystemVerilog Assertions (SVA)

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1 1 Verification of Digital Systems, Sring 2018 Introduction to SystemVerilog Assertions (SVA) Harry D. Foster Chief Scientist Verification IC Verification Solutions Division February 2018 Lecture Overview In this lecture, you will... Learn the structure of the SVA language Learn how to construct sequence Learn how to construct roerties Aly SVA on real examles 2 2 Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

2 2 Verification of Digital Systems, Sring 2018 LINEAR FORMALISM Brief Review of LTL and Introduction of Regular Exressions SystemVerilog Assertions SVA is based on linear temoral logic (LTL) built over sublanguages of regular exressions. Most engineers will find SVA sufficient to exress most common assertions required for hardware design. 4 4 Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

3 Verification of Digital Systems, Sring 2018 What We can Exress in LTL All Boolean logic roositions - Process 2 is in the critical section X holds in the next state.

3 3 Verification of Digital Systems, Sring 2018 What We can Exress in LTL All Boolean logic roositions - Process 2 is in the critical section X holds in the next state. Process 2 will be in the critical section in the next state X 5 5 What We can Exress in LTL F sometimes (i.e., eventually) holds. eventually rocess 2 will enter the critical section F G always (i.e., globally) holds. rocess 1 and 2 are always mutually exclusive G 6 6 Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

4 4 Verification of Digital Systems, Sring 2018 What We can Exress in LTL [ U q] q holds now or sometime in the future and holds from now until q holds (strong) U q q [ W q] holds from now until q holds (weak) W q 7 7 What We can Exress in LTL Weak oerators X, G, W Used to exress safety roerties, i.e. something bad never haens Strong oerators F, U Used to exress liveness roerties, i.e. something good eventually haens Safety roerties ut no obligation on the future, liveness roerties do! 8 8 Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

5 5 Verification of Digital Systems, Sring 2018 What We can Exress in LTL LTL formulas can be combined using the,,, logic connectors (negation, conjunction, disjunction, imlication) For examle. G ( request F grant ) request grant 9 9 What We can Exress in LTL LTL formulas can be combined using the,,, logic connectors (negation, conjunction, disjunction, imlication) For examle. G ( request F grant ) Temoral oerators can be combined too FG Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

6 6 Verification of Digital Systems, Sring 2018 What We Cannot Exress in LTL Counting examle: is asserted in every even cycle All the following traces satisfy this roerty!,,!,,,,,.,,!,,, No LTL formula can exress this roerty Regular Exressions Regular exressions describe sets of finite words w=a1,a2,,an. a1,a2, are letters in an alhabet. Regular exressions can exress counting modulo n. The * oerator enables counting modulo n. (ab)* - a regular exression describing the set of words: ε - (the emty word) ab abab ababab Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

7 Verification of Digital Systems, Sring 2018 Regular Exressions For reactive systems a letter in the alhabet is a Boolean exression The set of comutations satisfying is asserted in every even cycle

7 7 Verification of Digital Systems, Sring 2018 Regular Exressions For reactive systems a letter in the alhabet is a Boolean exression The set of comutations satisfying is asserted in every even cycle is described by the SVA regular exression (1`b1 ## )[*] A regular exression by itself is not a roerty Later: building roerties from regular exressions in SVA What Regular Exressions Cannot Exress The behavior, eventually holds forever cannot be exressed by a regular exression It can be exressed in LTL as : F G Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

8 8 Verification of Digital Systems, Sring 2018 Linear Formalisms LTL and regular exressions are linear formalisms Linear formalisms can be used to exress mainly roerties that are intended to hold on all comutations (i.e., executions of a design model). Most roerties required for the secification of digital designs can be exressed using linear formalism What cannot exress in linear formalisms: There exists a comutation in which eventually holds forever LTL imlicitly quantifies universally over aths SVA LANGUAGE STRUCTURE Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

9 9 Verification of Digital Systems, Sring 2018 Assertion Units Checker ackaging Directives (assert, cover) assert, assume, cover Proerties Sequences (Sequential Exressions) Boolean Exressions Secification of behavior; desired or undesired How Boolean events are related over time True or false assert roerty ) disable iff (~rst_n)!(grant0 & grant1)); Assertion Units Directives (assert, cover) Proerties Sequences (Sequential Exressions) Boolean Exressions rst_n!(grant0 & grant1) error Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

10 10 Verification of Digital Systems, Sring 2018 SVA rovides a mechanism to asynchronously disable a roerty during a reset using the SVA disable iff clause assert roerty (@(osedge ) disable iff (~rst_n)!(grant0 & grant1)); Note: rst_n is an active low reset in this examle MAPPING SVA INTO LTL Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

11 11 Verification of Digital Systems, Sring 2018 LTL Oerators in SVA All Boolean logic roositions - Process 2 is in the critical section LTL: X holds in the next state. SVA: nexttime [n] holds in the next state. Process 2 will be in the critical section in the next state nexttime LTL Oerators in SVA LTL: F eventually holds. SVA: eventually eventually holds (weak). eventually rocess 2 will enter the critical section eventually Note: s_eventually is a strong version of this oerator in SVA Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

12 12 Verification of Digital Systems, Sring 2018 LTL Oerators in SVA LTL: G always (i.e., globally) holds. SVA: always always (i.e., globally) holds. rocess 1 and 2 are always mutually exclusive always Note: there is an imlicit always when asserting a roerty: assert roerty(); LTL Oerators in SVA LTL: [ U q] q holds now or sometime in the future and holds from now until q holds (strong) SVA: s_until q s_until q q LTL: [ W q] holds from now until q holds (weak) SVA: until q until q Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

13 13 Verification of Digital Systems, Sring 2018 SVA with LTL Oerator Examle assert roerty disable iff (reset) $rose(req) imlies!done s_until grnt); SEQUENCES Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

14 Verification of Digital Systems, Sring 2018 Sequences So far we have examined LTL-based assertions We now we introduce SVA sequences Multile Boolean exressions are evaluated in a linear order of

14 14 Verification of Digital Systems, Sring 2018 Sequences So far we have examined LTL-based assertions We now we introduce SVA sequences Multile Boolean exressions are evaluated in a linear order of increasing time Assertion Units Directives (assert, cover) Proerties Sequences (Sequential Exressions) Boolean Exressions Sequence Temoral delay ##n with an integer n. start ##1 transfer start transfer Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

15 15 Verification of Digital Systems, Sring 2018 Sequence Temoral delay ##n with an integer n. start ##2 transfer start transfer Sequence Temoral delay ##[m:n] with range [m:n] start ##[0:2] transfer start transfer Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

16 16 Verification of Digital Systems, Sring 2018 Sequence Consecutive reetition [*m] or range [*m:n] - Use $ to reresent infinity start[*2] ##1 transfer start transfer Sequence Consecutive reetition [*m] or range [*m:n] - Use $ to reresent infinity start[*1:2] ##1 transfer start transfer Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

17 17 Verification of Digital Systems, Sring 2018 Sequence Consecutive reetition [*m] or range [*m:n] - Use $ to reresent infinity start[*1:2] ##1 transfer start transfer Sequence Consecutive reetition [*m] or range [*m:n] - Use $ to reresent infinity start[*1:2] ##1 transfer start transfer Note: This also matches the sequence secification!!!! Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

18 18 Verification of Digital Systems, Sring 2018 Sequence Non-consecutive reetition [=m] or [=m:n] start[=2] ##1 transfer start transfer [*] reresents zero to infinity start[=2]!start[*] ##1 start ##1!start[*] ##1 start ##1!start[*] Sequence Goto non-consecutive reetition [->m] or [->m:n] start[->2] ##1 transfer start transfer [*] reresents zero to infinity start[->2]!start[*] ##1 start ##1!start[*] ##1 start Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

19 19 Verification of Digital Systems, Sring 2018 Proerties Assertion Units Directives (assert, cover) Proerties Sequences (Sequential Exressions) Boolean Exressions Proerties Overlaing sequence imlication oerator -> ready ##1 start -> go ##1 done ready start go done assertion roerty ) ready ##1 start -> go ##1 done ); Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

20 Verification of Digital Systems, Sring 2018 Proerties Non-overlaing sequence imlication oerator => ready ##1 start => go ##1 done ready start go done NOTE: A => B is the same as A -> ##1 B 39 39

20 20 Verification of Digital Systems, Sring 2018 Proerties Non-overlaing sequence imlication oerator => ready ##1 start => go ##1 done ready start go done NOTE: A => B is the same as A -> ##1 B Fair Arbitration Scheme Examle Asserting that an arbiter is fair To be fair, a ending request for a articular client should never have to wait more than two arbitration cycles Otherwise, the arbiter unfairly issued multile grants to a different client req[0] req[1] Arbiter gnt[0] gnt[1] Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

21 21 Verification of Digital Systems, Sring 2018 Fair Arbitration Scheme Examle a_0_fair: assert roerty ) disable iff (reset) $rose(req[0]) -> not (!gnt[0] throughout (gnt[1])[->2])); req[0] req[0] req[1] Arbiter gnt[0] gnt[1] gnt[0] gnt[1] Fair Arbitration Scheme Examle a_0_fair: assert roerty ) disable iff (reset) req[0] -> not (!gnt[0] throughout (gnt[1])[->2])); req[0] req[0] req[1] Arbiter gnt[0] gnt[1] gnt[0] gnt[1] Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

22 22 Verification of Digital Systems, Sring 2018 Fair Arbitration Scheme Examle a_0_fair: assert roerty ) disable iff (reset) $rose(req[0]) -> not (!gnt[0] throughout (gnt[1])[->2])); req[0] req[0] req[1] Arbiter gnt[0] gnt[1] gnt[0] gnt[1] Fair Arbitration Scheme Examle a_1_fair: assert roerty ) disable iff (reset) $rose(req[1] -> not (!gnt[1] throughout (gnt[0])[->2])); req[0] req[0] req[1] Arbiter gnt[0] gnt[1] gnt[0] gnt[1] Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

23 23 Verification of Digital Systems, Sring 2018 Named sequences and roerties To facilitate reuse, roerties and sequences can be declared and then referenced by name Can be declared with or without arameters sequence s_o_retry; (req ##1 retry); endsequence sequence s_cache_fill(req, done, fill); (req ##1 done [=1] ##1 fill); endsequence Named roerties and sequences sequence s_o_retry; (req ##1 retry); endsequence sequence s_cache_fill(rdy, done, fill); (rdy ##1 done [=1] ##1 fill); endsequence assert roerty ) disable iff (reset) s_o_retry => s_cache_fill (my_rdy,my_done,my_fill)); Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

24 24 Verification of Digital Systems, Sring 2018 Named roerties and sequences roerty _en_mutex(en0, ) disable iff (reset) ~(en0 & en1); endroerty assert roerty (_en_mutex(bus_en0, bus_en1)); Action blocks An SVA action block secifies the actions that are taken uon success or failure of the assertion The action block, if secified, is executed immediately after the evaluation of the assert exression assert roerty ) disable iff (reset)!(grant0 & grant1) ) else begin // action block fail statement $error( Mutex violation with grants. ); end Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

25 25 Verification of Digital Systems, Sring 2018 System functions $rose( exression ) $fell( exression ) $stable( exression ) $ast( exression [, number_of_ticks] ) The need for $rose system function You must be recise when secifying! assertion roerty ) start -> ##2 Transfer); start transfer Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

26 26 Verification of Digital Systems, Sring 2018 Eliminates multile matches You must be recise when secifying! assertion roerty ) $rose(start) -> ##2 Transfer); start transfer $rose(start) is a short cut for the sequence!start ##1 start System functions $onehot (<exression>) - Returns true if only one bit of the exression is high $onehot0 (<exression>) - Returns true if at most one bit of the exression is high $isunknown (<exression>) - Returns true if any bit of the exression is X or Z - This is equivalent to ^<exression> === bx Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

27 Verification of Digital Systems, Sring 2018 Introduction to SVA Some assertions require additional modeling code In addition to the assertion constructs FIFO rst_n Controller ut get rst_n data_in

27 27 Verification of Digital Systems, Sring 2018 Introduction to SVA Some assertions require additional modeling code In addition to the assertion constructs FIFO rst_n Controller ut get rst_n data_in A A full emty data_out // Assert that the FIFO controller cannot overflow nor underflow Introduction to SVA // assertion modeling code not art of the design `ifdef ASSERT_ON int cnt = 0; ) if (!rst_n) cnt <= 0; else cnt <= cnt + ut get; // assert no overflow assert roerty (@osedge disable iff (~rst_n)!((cnt + ut get) > `DEPTH)); // assert no underflow assert roerty (@osedge disable iff (!rst_n)!((cnt + ut) < get)); `endif Note: rst_n is an active low reset in this examle Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

28 28 Verification of Digital Systems, Sring 2018 SVA Does and Don ts Never assert a sequence! assert roerty (@osedge ) (req ##1 grnt ##1 done)); This says every clock we see req, followed by gnt, followed by done The correct way to do this is with an imlication oerator: assert roerty (@osedge ) (req => grnt ##1 done)); It s ok to cover a sequence It s ok to assert a forbidden sequence using not assert roerty (@osedge ) not (req ##1 done ##1 grant)); BUS-BASED DESIGN EXAMPLE Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

29 29 Verification of Digital Systems, Sring 2018 Bus-Based Design Examle CPU 1 CPU 2 Bridge Dataath Control UART Arbiter Bus A I/F FIFO I/F Bus B Dataath Memory Controller Grahics Controller FIFO Timer Nonielined Bus Interface rst_n sel[0] en I/F addr write I/F rdata Master wdata Slave Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

30 30 Verification of Digital Systems, Sring 2018 Non-Burst Write Transaction addr Addr 1 write sel[0] en wdata Data 1 BUS STATE INACTIVE START ACTIVE INACTIVE Non-Burst Read Transaction addr Addr 1 write sel[0] en rdata Data 1 BUS STATE INACTIVE START ACTIVE INACTIVE Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

31 Verification of Digital Systems, Sring 2018 Concetual Bus States INACTIVE sel[0] == 0 en == 0 no transfer setu no transfer START sel[0] == 1 en == 0 transfer setu ACTIVE sel[0] == 1 en == 1 61 61

31 31 Verification of Digital Systems, Sring 2018 Concetual Bus States INACTIVE sel[0] == 0 en == 0 no transfer setu no transfer START sel[0] == 1 en == 0 transfer setu ACTIVE sel[0] == 1 en == Interface Requirements Proerty Name Bus legal treansitions Descrition _state_reset_inactive Initial state after reset is INACTIVE _valid_inactive_transition ACTIVE state does not follow INACTIVE _valid_start_transition Only ACTIVE state follows START _valid_active_transition ACTIVE state does not follow ACTIVE _no_error_state Bus state must be valid:!(se==0 & en==1) Bus stable signals no transfer INACTIVE sel[0] == 0 en == 0 setu START sel[0] == 1 en == 0 transfer setu ACTIVE sel[0] == 1 en == 1 _sel_stable _addr_stable _write_stable _wdata_stable Slave select signals remain stable from START to ACTIVE Address remains stable from START to ACTIVE Control remains stable from START to ACTIVE Data remains stable from START to ACTIVE Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

32 32 Verification of Digital Systems, Sring 2018 Use Modeling Code to Simlify Coding `ifdef ASSERTION_ON //Ma bus control values to concetual states if (rst_n) begin bus_reset = 1; bus_inactive = 1; bus_start = 0; bus_active = 0; bus_error = 0; end else begin bus_reset = 0; bus_inactive = ~sel & ~en; bus_start = sel & ~en; bus_active = sel & en; bus_error = ~sel & en; end `endif no transfer INACTIVE sel[0] == 0 en == 0 setu START sel[0] == 1 en == 0 transfer ACTIVE sel[0] == 1 en == 1 setu SVA Examles roerty ) disable iff (bus_reset) ( bus_inactive) => ((bus_inactive) (bus_start)); endroerty a_valid_inactive_transition: assert roerty (_valid_inactive_transition); INACTIVE sel[0] == 0 en == 0 setu roerty ) disable iff (bus_reset) (bus_start) => (bus_active); endroerty a_valid_start_transition: assert roerty (_valid_start_transition); no transfer START sel[0] == 1 en == 0 transfer ACTIVE sel[0] == 1 en == 1 setu Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

33 33 Verification of Digital Systems, Sring 2018 Instantiating Assertions within Modules module bus_controller (...);... always ) begin.... end always ) begin.... end Imlicit always assert roerty (_valid_start_transition); endmodule CHECKER PACKAGING Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

34 Verification of Digital Systems, Sring 2018 Assertion Units Checker ackaging Directives (assert, cover) assert, assume, cover Proerties Sequences (Sequential Exressions) Boolean Exressions

34 34 Verification of Digital Systems, Sring 2018 Assertion Units Checker ackaging Directives (assert, cover) assert, assume, cover Proerties Sequences (Sequential Exressions) Boolean Exressions Secification of behavior; desired or undesired How Boolean events are related over time True or false SVA Checker Source: Dmitry Korchemny, SystemVerilog Assertions for Formal Verification, HVC Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

35 35 Verification of Digital Systems, Sring 2018 Binding Checkers Source: Dmitry Korchemny, SystemVerilog Assertions for Formal Verification, HVC SUMMARY Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

36 Verification of Digital Systems, Sring 2018 Lecture Reca

.. Discussed the structure of the SVA language Discussed how

Demonstrate SVA on real examles Discussed Checkers and Bind

36 36 Verification of Digital Systems, Sring 2018 Lecture Reca In this lecture, I discussed... Discussed the structure of the SVA language Discussed how to construct sequence Discussed how to construct roerties Demonstrate SVA on real examles Discussed Checkers and Bind Deartment of Electrical and Comuter Engineering, The University of Texas at Austin

EECS 578 SVA mini-project Assigned: 10/08/15 Due: 10/27/15

EECS578 Prof. Bertacco Fall 2015 EECS 578 SVA mini-project Assigned: 10/08/15 Due: 10/27/15 1. Overview This project focuses on designing a test plan and a set of test programs for a digital reverberation