Binary Translation Using Peephole Superoptimizers. Sorav Bansal and Alex Aiken Stanford University
|
|
- Morris Cameron
- 5 years ago
- Views:
Transcription
1 Binary Translation Using Peephole Superoptimizers Sorav Bansal and Alex Aiken Stanford University 1
2 TALK OUTLINE What is Binary Translation? What are Peephole Superoptimizers? Why Binary Translation Using Peephole Superoptimizers? Challenges and Solutions Experiments and Results TALK OUTLINE 2
3 BINARY TRANSLATION The ability to run code written for one architecture on another without access to source code Applications Portability of Applications (eg. Apple) Backward/Forward Compatibility of Architecture Generations (eg. Intel) Virtualization (eg. IBM s PAVE) Get the Best-of-Both-Worlds (eg. itunes on x86/linux) Running Legacy Code Instrumentation (Machine X Machine X) BINARY TRANSLATION 3
4 BINARY TRANSLATION De-compile Intermediate Code Re-compile Machine X Binary Machine Y Binary BINARY TRANSLATION 4
5 PEEPHOLE SUPEROPTIMIZERS PEEPHOLE SUPEROPTIMIZERS 5
6 PEEPHOLE SUPEROPTIMIZERS Source Code Binary Code Harvest Binary Code to build Target Set of Instruction Sequences PEEPHOLE SUPEROPTIMIZERS 5-A
7 PEEPHOLE SUPEROPTIMIZERS Target Instruction Sequences Superoptimizer Table of Peephole Rules Input Peephole Rules Output ÑÓÚ ± Ô ± Ô ÑÓÚ ± Ô ± Ô ÑÓÚ ± Ô ± Ô PEEPHOLE SUPEROPTIMIZERS 6
8 PEEPHOLE SUPEROPTIMIZERS Source Code Intermediate Binary Code Optimized Code Apply Peephole Rules Input Peephole Rules Output ÑÓÚ ± Ô ± Ô ÑÓÚ ± Ô ± Ô ÑÓÚ ± Ô ± Ô PEEPHOLE SUPEROPTIMIZERS 7
9 PEEPHOLE TRANSLATORS Source Code Machine X Assembly Optimized Machine Y Assembly Apply Peephole Rules Peephole Rules Input Map Output Machine X Assembly rx 1 ry 1 rx 2 ry 2 Machine Y Assembly PEEPHOLE TRANSLATORS 8
10 PEEPHOLE TRANSLATORS Source Code Machine PowerPCX Assembly Optimized Machine x86 Y Assembly Peephole Rules Input Map Output Apply Peephole Rules Machine X Assembly ÑÖ Ö½ Ö¾ ÑÖ Ö¾ Ö½ r1 %ebp rx 1 ry 1 r2 %esp rx 2 ry 2 Machine Y ÑÓÚ ± Ô ± Ô Assembly PEEPHOLE TRANSLATORS 8-A
11 CHALLENGES CHALLENGES 9
12 CHALLENGES Register Mapping Dynamic/Static? CHALLENGES 9-A
13 CHALLENGES Register Mapping Dynamic/Static? Control Flow Transfers Direct/Indirect Jumps Function Call/Return CHALLENGES 9-B
14 CHALLENGES Register Mapping Dynamic/Static? Control Flow Transfers Direct/Indirect Jumps Function Call/Return Endian-ness CHALLENGES 9-C
15 REGISTER MAPPING PowerPC : 32 GPRs, 3 SPRs, 8 flag registers x86 : 8 GPRs and other SIMD-support registers REGISTER MAPPING 10
16 REGISTER MAPPING Dynamic Register Mapping Use dynamic programming considering all possible register maps. Account for Switching cost Cost of the peephole rule Make decisions at function return points REGISTER MAPPING 11
17 EXPERIMENTAL SETUP gcc <options> -arch=ppc.c source file gcc <options> -arch=x86 PowerPC Executable x86 Executable Peephole Binary Translation Compare x86 Executable EXPERIMENTAL SETUP 12
18 EXPERIMENTAL SETUP gcc <options> -arch=ppc.c source file gcc <options> -arch=x86 PowerPC Executable x86 Executable Peephole Binary Translation Compare x86 Executable Qemu (Freely available) : 10-20% Apple Rosetta (Commercial) : 70-80% (claim) Transitive (Commercial) : 70-80% (claim) EXPERIMENTAL SETUP 12-A
19 BENCHMARKS Name Description fibo64 Compute the first n fibonacci numbers bubsort64 Bubble-sort a large array of 64-bit integers hanoi1 Kolar s Hanoi Tower algorithm no. 1 hanoi2 Er s LLHanoi Hanoi Tower loop less algorithm hanoi3 Kolar s Hanoi Tower algorithm no. 3 BENCHMARKS 13
20 RESULTS fibo64 bubsort64 hanoi1 hanoi2 hanoi3 RESULTS 14
21 RESULTS O0 fibo64 110% bubsort64 84% hanoi1 97% hanoi2 103% hanoi3 90% RESULTS 14-A
22 RESULTS O0 O2 fibo64 110% 311% bubsort64 84% 55% hanoi1 97% 59% hanoi2 103% 159% hanoi3 90% 90.5% RESULTS 14-B
23 RESULTS O0 O2 O2+ fibo64 110% 311% 121% bubsort64 84% 55% 61.4% hanoi1 97% 59% 59% hanoi2 103% 159% 158% hanoi3 90% 90.5% 67.2% O2+ = -O2 -fomit-frame-pointer RESULTS 14-C
24 RESULTS O0 O2 O2+ fibo64 110% 311% 121% bubsort64 84% 55% 61.4% hanoi1 97% 59% 59% hanoi2 103% 159% 158% hanoi3 90% 90.5% 67.2% O2+ = -O2 -fomit-frame-pointer RESULTS 14-D
25 RESULTS O0 O2 O2+ fibo64 110% 311% 121% bubsort64 84% 55% 61.4% hanoi1 97% 59% 59% hanoi2 103% 159% 158% hanoi3 90% 90.5% 67.2% O2+ = -O2 -fomit-frame-pointer RESULTS 14-E
26 CONCLUSIONS AND FUTURE WORK Conclusions Peephole Superoptimization is a good fit for the problem of Binary Translation Ongoing Work Improve performance Support all system calls (run larger benchmarks) Look at other source-target architecture pairs CONCLUSIONS AND FUTURE WORK 15
Outline. 1 Reiteration. 2 Dynamic scheduling - Tomasulo. 3 Superscalar, VLIW. 4 Speculation. 5 ILP limitations. 6 What we have done so far.
Outline 1 Reiteration Lecture 5: EIT090 Computer Architecture 2 Dynamic scheduling - Tomasulo Anders Ardö 3 Superscalar, VLIW EIT Electrical and Information Technology, Lund University Sept. 30, 2009 4
More informationInstruction Level Parallelism Part III
Course on: Advanced Computer Architectures Instruction Level Parallelism Part III Prof. Cristina Silvano Politecnico di Milano email: cristina.silvano@polimi.it 1 Outline of Part III Dynamic Scheduling
More informationInstruction Level Parallelism Part III
Course on: Advanced Computer Architectures Instruction Level Parallelism Part III Prof. Cristina Silvano Politecnico di Milano email: cristina.silvano@polimi.it 1 Outline of Part III Tomasulo Dynamic Scheduling
More informationAdvanced Pipelining and Instruction-Level Paralelism (2)
Advanced Pipelining and Instruction-Level Paralelism (2) Riferimenti bibliografici Computer architecture, a quantitative approach, Hennessy & Patterson: (Morgan Kaufmann eds.) Tomasulo s Algorithm For
More informationFor an alphabet, we can make do with just { s, 0, 1 }, in which for typographic simplicity, s stands for the blank space.
Problem 1 (A&B 1.1): =================== We get to specify a few things here that are left unstated to begin with. I assume that numbers refers to nonnegative integers. I assume that the input is guaranteed
More informationInstruction Level Parallelism and Its. (Part II) ECE 154B
Instruction Level Parallelism and Its Exploitation (Part II) ECE 154B Dmitri Strukov ILP techniques not covered last week this week next week Scoreboard Technique Review Allow for out of order execution
More informationOptimization of Multi-Channel BCH Error Decoding for Common Cases. Russell Dill Master's Thesis Defense April 20, 2015
Optimization of Multi-Channel BCH Error Decoding for Common Cases Russell Dill Master's Thesis Defense April 20, 2015 Bose-Chaudhuri-Hocquenghem (BCH) BCH is an Error Correcting Code (ECC) and is used
More informationMauricio Álvarez-Mesa ; Chi Ching Chi ; Ben Juurlink ; Valeri George ; Thomas Schierl Parallel video decoding in the emerging HEVC standard
Mauricio Álvarez-Mesa ; Chi Ching Chi ; Ben Juurlink ; Valeri George ; Thomas Schierl Parallel video decoding in the emerging HEVC standard Conference object, Postprint version This version is available
More informationSlide Set 8. for ENCM 501 in Winter Term, Steve Norman, PhD, PEng
Slide Set 8 for ENCM 501 in Winter Term, 2017 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Winter Term, 2017 ENCM 501 W17 Lectures: Slide
More informationAmdahl s Law in the Multicore Era
Amdahl s Law in the Multicore Era Mark D. Hill and Michael R. Marty University of Wisconsin Madison August 2008 @ Semiahmoo Workshop IBM s Dr. Thomas Puzak: Everyone knows Amdahl s Law 2008 Multifacet
More informationTomasulo Algorithm. Developed at IBM and first implemented in IBM s 360/91
Tomasulo Algorithm Developed at IBM and first implemented in IBM s 360/91 IBM wanted to use the existing compiler instead of a specialized compiler for high end machines. Tracks when operands are available
More informationCS152 Computer Architecture and Engineering Lecture 17 Advanced Pipelining: Tomasulo Algorithm
CS152 Computer Architecture and Engineering Lecture 17 Advanced Pipelining: Tomasulo Algorithm 2003-10-23 Dave Patterson (www.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs152/ CS 152 L17 Adv.
More informationPredicting the immediate future with Recurrent Neural Networks: Pre-training and Applications
Predicting the immediate future with Recurrent Neural Networks: Pre-training and Applications Introduction Brandon Richardson December 16, 2011 Research preformed from the last 5 years has shown that the
More informationMulti-Frame Matrix Capture Common File Format (MFMC- CFF) Requirements Capture
University of Bristol NDT Laboratory Multi-Frame Matrix Capture Common File Format (MFMC- CFF) Requirements Capture Martin Mienczakowski, September 2014 OVERVIEW A project has been launched at the University
More informationHiPAcc-LTE: An Integrated High Performance Accelerator for 3GPP LTE Stream Ciphers
HiPAcc-LTE: An Integrated High Performance Accelerator for 3GPP LTE Stream Ciphers Sourav Sen Gupta1, Anupam Chattopadhyay2, Ayesha Khalid2 1. Applied Statistics Unit, Indian Statistical Institute, Kolkata,
More informationAsynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton*, Mark R. Greenstreet, Steven J.E. Wilton*, *Dept. of Electrical and Computer Engineering, Dept.
More informationMilestone Solution Partner IT Infrastructure Components Certification Report
Milestone Solution Partner IT Infrastructure Components Certification Report Infortrend Technologies 5000 Series NVR 12-15-2015 Table of Contents Executive Summary:... 4 Introduction... 4 Certified Products...
More informationLecture 16: Instruction Level Parallelism -- Dynamic Scheduling (OOO) via Tomasulo s Approach
Lecture 16: Instruction Level Parallelism -- Dynamic Scheduling (OOO) via Tomasulo s Approach CSE 564 Computer Architecture Summer 2017 Department of Computer Science and Engineering Yonghong Yan yan@oakland.edu
More informationWiBench: An Open Source Kernel Suite for Benchmarking Wireless Systems
1 WiBench: An Open Source Kernel Suite for Benchmarking Wireless Systems Qi Zheng*, Yajing Chen*, Ronald Dreslinski*, Chaitali Chakrabarti +, Achilleas Anastasopoulos*, Scott Mahlke*, Trevor Mudge* *,
More informationMicroprocessor Design
Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004 To my wife and children Windy, Jonathan and Michelle Contents 1. Designing a Microprocessor... 2 1.1 Overview
More informationA. To tell the time of the day 1. To build a mod-19 counter the number of. B. To tell how much time has elapsed flip-flops required is
JAIHINDPURAM, MADURAI 11. Mobile: 9080035050 Computer Science TRB Unit Test 31 (Digital Logic) A. To tell the time of the day 1. To build a mod-19 counter the number of B. To tell how much time has elapsed
More informationA High-Performance Parallel CAVLC Encoder on a Fine-Grained Many-core System
A High-Performance Parallel CAVLC Encoder on a Fine-Grained Many-core System Zhibin Xiao and Bevan M. Baas VLSI Computation Lab, ECE Department University of California, Davis Outline Introduction to H.264
More informationSetup Guide. SpectraCal MobileForge. Pattern Generator App. Rev. 1.6
Setup Guide SpectraCal MobileForge Pattern Generator App Rev. 1.6 Introduction MobileForge is a free pattern generator app for ios, Android, and Fire TV devices. MobileForge generates accurate test patterns
More informationCP316 Screencast mini-project
CP316 Screencast mini-project Wilfrid Laurier University January 23, 2013 Some MPLABX features are easier to show than to explain Some MPLABX features are easier to show than to explain screencast, about
More informationSlide Set 9. for ENCM 501 in Winter Steve Norman, PhD, PEng
Slide Set 9 for ENCM 501 in Winter 2018 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary March 2018 ENCM 501 Winter 2018 Slide Set 9 slide
More informationFINALTERM EXAMINATION Fall 2008 CS101- Introduction to Computing (Session - 4)
FINALTERM EXAMINATION Fall 2008 CS101- Introduction to Computing (Session - 4) Question No: 1 ( Marks: 1 ) - Please choose one Using Java Script you can write a character at random location on screen By
More informationSlide Set 6. for ENCM 369 Winter 2018 Section 01. Steve Norman, PhD, PEng
Slide Set 6 for ENCM 369 Winter 2018 Section 01 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary February 2018 ENCM 369 Winter 2018 Section
More informationDIMACS Implementation Challenges 1 Network Flows and Matching, Clique, Coloring, and Satisability, Parallel Computing on Trees and
8th DIMACS Implementation Challenge: The Traveling Salesman Problem http://wwwresearchattcom/dsj/chtsp/ David S Johnson AT&T Labs { Research Florham Park, NJ 07932-0971 dsj@researchattcom http://wwwresearchattcom/dsj/
More informationVLSI Design: 3) Explain the various MOSFET Capacitances & their significance. 4) Draw a CMOS Inverter. Explain its transfer characteristics
1) Explain why & how a MOSFET works VLSI Design: 2) Draw Vds-Ids curve for a MOSFET. Now, show how this curve changes (a) with increasing Vgs (b) with increasing transistor width (c) considering Channel
More informationDynamic Scheduling. Differences between Tomasulo. Tomasulo Algorithm. CDC 6600 scoreboard. Or ydanicm ceshuldngi
Dynamic Scheduling (or out-of-order execution) Dynamic Scheduling Or ydanicm ceshuldngi CDC 6600 scoreboard Instruction storage added to each functional execution unit Instructions issue to FU when no
More informationFPGA based Satellite Set Top Box prototype design
9 th International conference on Sciences and Techniques of Automatic control & computer engineering FPGA based Satellite Set Top Box prototype design Mohamed Frad 1,2, Lamjed Touil 1, Néji Gabsi 2, Abdessalem
More informationContents Slide Set 6. Introduction to Chapter 7 of the textbook. Outline of Slide Set 6. An outline of the first part of Chapter 7
CM 69 W4 Section Slide Set 6 slide 2/9 Contents Slide Set 6 for CM 69 Winter 24 Lecture Section Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary
More informationDeveloping multitrack audio e ect plugins for music production research
Developing multitrack audio e ect plugins for music production research Brecht De Man Correspondence: Centre for Digital Music School of Electronic Engineering and Computer Science
More informationDifferences between Tomasulo. Another Dynamic Algorithm: Tomasulo Organization. Reservation Station Components
Another Dynamic Algorithm: Tomasulo Algorithm Differences between Tomasulo Algorithm & Scoreboard For IBM 360/9 about 3 years after CDC 6600 Goal: High Performance without special compilers Differences
More informationTransparent low-overhead checkpoint for GPU-accelerated clusters
Transparent low-overhead checkpoint for GPU-accelerated clusters Leonardo BAUTISTA GOMEZ 1,3, Akira NUKADA 1, Naoya MARUYAMA 1, Franck CAPPELLO 3,4, Satoshi MATSUOKA 1,2 1 Tokyo Institute of Technology,
More informationECSE-323 Digital System Design. Datapath/Controller Lecture #1
1 ECSE-323 Digital System Design Datapath/Controller Lecture #1 2 Synchronous Digital Systems are often designed in a modular hierarchical fashion. The system consists of modular subsystems, each of which
More informationGo BEARS~ What are Machine Structures? Lecture #15 Intro to Synchronous Digital Systems, State Elements I C
CS6C L5 Intro to SDS, State Elements I () inst.eecs.berkeley.edu/~cs6c CS6C : Machine Structures Lecture #5 Intro to Synchronous Digital Systems, State Elements I 28-7-6 Go BEARS~ Albert Chae, Instructor
More informationPoloidal Current Anti-Saturation Control Routine with DPCS Multi-processor Architecture
Poloidal Current Anti-Saturation Control Routine with DPCS Multi-processor Architecture M. Ferrara, I.H. Hutchinson, S.M. Wolfe, J.A. Stillerman, T.W. Fredian Abstract: Ohmic and equilibrium field currents
More informationDRAFT. Sign Language Video Encoding for Digital Cinema
Sign Language Video Encoding for Digital Cinema ISDCF Document 13 October 24, 2017 Version 0.10 ISDCF Document 13 Page 1 of 6 October 19, 2017 1. Introduction This document describes a method for the encoding
More information18-551, Spring Group #4 Final Report. Get in the Game. Nick Lahr (nlahr) Bryan Murawski (bmurawsk) Chris Schnieder (cschneid)
18-551, Spring 2005 Group #4 Final Report Get in the Game Nick Lahr (nlahr) Bryan Murawski (bmurawsk) Chris Schnieder (cschneid) Group #4, Get in the Game Page 1 18-551, Spring 2005 Table of Contents 1.
More informationExplorer Edition FUZZY LOGIC DEVELOPMENT TOOL FOR ST6
fuzzytech ST6 Explorer Edition FUZZY LOGIC DEVELOPMENT TOOL FOR ST6 DESIGN: System: up to 4 inputs and one output Variables: up to 7 labels per input/output Rules: up to 125 rules ON-LINE OPTIMISATION:
More informationH.264/AVC Baseline Profile Decoder Complexity Analysis
704 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 13, NO. 7, JULY 2003 H.264/AVC Baseline Profile Decoder Complexity Analysis Michael Horowitz, Anthony Joch, Faouzi Kossentini, Senior
More information1ms Column Parallel Vision System and It's Application of High Speed Target Tracking
Proceedings of the 2(X)0 IEEE International Conference on Robotics & Automation San Francisco, CA April 2000 1ms Column Parallel Vision System and It's Application of High Speed Target Tracking Y. Nakabo,
More informationDesign of an Area-Efficient Interpolated FIR Filter Based on LUT Partitioning
Design of an Area-Efficient Interpolated FIR Filter Based on LUT Partitioning This paper describes the design of an area-efficient interpolation FIR filter with partitioned lookup table (LUT) structure.
More information10 Gb/s Duobinary Signaling over Electrical Backplanes Experimental Results and Discussion
10 Gb/s Duobinary Signaling over Electrical Backplanes Experimental Results and Discussion J. Sinsky, A. Adamiecki, M. Duelk, H. Walter, H. J. Goetz, M. Mandich contact: sinsky@lucent.com Supporters John
More informationquickstart guide AC-FxHd-kit or
quickstart guide AC-FxHd-kit Thank you for purchasing the Fox & Hound HDMI Testing Kit. This will be your quickstart guide for testing distributed audio/ video systems and products. This testing and troubleshooting
More informationCS 498 Hot Topics in High Performance Computing. Networks and Fault Tolerance. 3. A Network-Centric View on HPC
CS 498 Hot Topics in High Performance Computing Networks and Fault Tolerance 3. A Network-Centric View on HPC Intro What did we learn in the last lecture SMM vs. DMM architecture and programming Systolic
More informationThe Panels are packaged with everything necessary to support either PC or Macintosh systems and it is all contained in a hard, padded carrying case.
Product Overview Polaview LCD Panels Project the power of your computer or video source directly onto the meeting room screen with Polaroid s Polaview LCD Panels. With the Polaroid Polaview line of LCD
More informationThe PeRIPLO Propositional Interpolator
The PeRIPLO Propositional Interpolator N. Sharygina Formal Verification and Security Group University of Lugano joint work with Leo Alt, Antti Hyvarinen, Grisha Fedyukovich and Simone Rollini October 2,
More informationReview C program: foo.c Compiler Assembly program: foo.s Assembler Object(mach lang module): foo.o. Lecture #14
CS61C L14 Introduction to Synchronous Digital Systems (1) inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #14 Introduction to Synchronous Digital Systems 2007-7-18 Scott Beamer, Instructor
More informationCS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #14 Introduction to Synchronous Digital Systems 2007-7-18 Scott Beamer, Instructor CS61C L14 Introduction to Synchronous Digital Systems
More informationRedMere s Chip in Ultra Thin Cables.for the New Video Life Style. Dec 2 nd 2009
RedMere s Chip in Ultra Thin Cables.for the New Video Life Style Dec 2 nd 2009 About RedMere Established in 2005 under fabless model Locations: Dublin (HQ) and Cork (R&D) Sales: Tokyo, Hong Kong and San
More informationTechnical Note PowerPC Embedded Processors Video Security with PowerPC
Introduction For many reasons, digital platforms are becoming increasingly popular for video security applications. In comparison to traditional analog support, a digital solution can more effectively
More informationSequential Logic Notes
Sequential Logic Notes Andrew H. Fagg igital logic circuits composed of components such as AN, OR and NOT gates and that do not contain loops are what we refer to as stateless. In other words, the output
More informationICCOPS. Intuitive Cursor Control by Optical Processing Software. Contents. London, 03 February Authors: I. Mariggis P. Ruetten A.
ICCOPS Intuitive Cursor Control by Optical Processing Software London, 03 February 2013 Authors: I. Mariggis P. Ruetten A. Tamciuc Contents 1. Introduction... 2 2. Problem description and our solution...
More informationOverview. Using DISE to Protect Return Addresses from Attack. Stack-Smashing is a Problem. Stack-Smashing Attacks. stack
Using DISE to Protect Return Addresses from Attack Overview Prevent stack-smashing attacks Old approach, new implementation Dynamic Instruction Stream Editing (DISE) Marc L. Corliss, E Christopher Lewis,
More informationA low-power portable H.264/AVC decoder using elastic pipeline
Chapter 3 A low-power portable H.64/AVC decoder using elastic pipeline Yoshinori Sakata, Kentaro Kawakami, Hiroshi Kawaguchi, Masahiko Graduate School, Kobe University, Kobe, Hyogo, 657-8507 Japan Email:
More informationLOCAL DECODING OF WALSH CODES TO REDUCE CDMA DESPREADING COMPUTATION. Matt Doherty Introductory Digital Systems Laboratory.
LOCAL DECODING OF WALSH CODES TO REDUCE CDMA DESPREADING COMPUTATION Matt Doherty 6.111 Introductory Digital Systems Laboratory May 18, 2006 Abstract As field-programmable gate arrays (FPGAs) continue
More informationAn MFA Binary Counter for Low Power Application
Volume 118 No. 20 2018, 4947-4954 ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu ijpam.eu An MFA Binary Counter for Low Power Application Sneha P Department of ECE PSNA CET, Dindigul, India
More informationComputer Architecture Spring 2016
Computer Architecture Spring 2016 Lecture 12: Dynamic Scheduling: Tomasulo s Algorithm Shuai Wang Department of Computer Science and Technology Nanjing University [Slides adapted from CS252, UC Berkeley
More informationElectrical and Telecommunications Engineering Technology_TCET3122/TC520. NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York
NEW YORK CITY COLLEGE OF TECHNOLOGY The City University of New York DEPARTMENT: SUBJECT CODE AND TITLE: COURSE DESCRIPTION: REQUIRED: Electrical and Telecommunications Engineering Technology TCET 3122/TC
More informationSlack Redistribution for Graceful Degradation Under Voltage Overscaling
Slack Redistribution for Graceful Degradation Under Voltage Overscaling Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar and John Sartori VLSI CAD LABORATORY, UCSD PASSAT GROUP, UIUC UCSD VLSI CAD Laboratory
More informationFRONT PANEL FUNCTIONAL SPECIFICATIONS
FRONT PANEL FUNCTIONAL SPECIFICATIONS 1- On-Off Switch : for use to turn on and turn off of the device 2- Sat Select Button : for use transition to the satellite receivers 3- Sat Select Indicator : Shows
More informationMore Digital Circuits
More Digital Circuits 1 Signals and Waveforms: Showing Time & Grouping 2 Signals and Waveforms: Circuit Delay 2 3 4 5 3 10 0 1 5 13 4 6 3 Sample Debugging Waveform 4 Type of Circuits Synchronous Digital
More informationfor Digital IC's Design-for-Test and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ
Design-for-Test for Digital IC's and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ 07458 www.phptr.com ISBN D-13-DflMfla7-l : Ml H Contents Preface Acknowledgments Introduction
More informationMusic Composition with RNN
Music Composition with RNN Jason Wang Department of Statistics Stanford University zwang01@stanford.edu Abstract Music composition is an interesting problem that tests the creativity capacities of artificial
More informationD Latch (Transparent Latch)
D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done
More informationA Low Power Delay Buffer Using Gated Driver Tree
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) ISSN: 2319 4200, ISBN No. : 2319 4197 Volume 1, Issue 4 (Nov. - Dec. 2012), PP 26-30 A Low Power Delay Buffer Using Gated Driver Tree Kokkilagadda
More informationDesign of Fault Coverage Test Pattern Generator Using LFSR
Design of Fault Coverage Test Pattern Generator Using LFSR B.Saritha M.Tech Student, Department of ECE, Dhruva Institue of Engineering & Technology. Abstract: A new fault coverage test pattern generator
More informationParallelization of Multimedia Applications by Compiler on Multicores for Consumer Electronics
Vol. 0 No. 0 1959 TV MPEG2 MP3 JPEG 2000 OSCAR API VLIW 4 FR1000 SH-4A 4 RP1 FR1000 4 1 4 3.27 RP1 4 1 4 3.31 Parallelization of Multimedia Applications by Compiler on Multicores for Consumer Electronics
More informationAn Improved Hardware Implementation of the Grain-128a Stream Cipher
An Improved Hardware Implementation of the Grain-128a Stream Cipher Shohreh Sharif Mansouri and Elena Dubrova Department of Electronic Systems Royal Institute of Technology (KTH), Stockholm Email:{shsm,dubrova}@kth.se
More informationENGR 1000, Introduction to Engineering Design
ENGR 1000, Introduction to Engineering Design Unit 2: Data Acquisition and Control Technology Lesson 2.4: Programming Digital Ports Hardware: 12 VDC power supply Several lengths of wire NI-USB 6008 Device
More informationTesting of Cryptographic Hardware
Testing of Cryptographic Hardware Presented by: Debdeep Mukhopadhyay Dept of Computer Science and Engineering, Indian Institute of Technology Madras Motivation Behind the Work VLSI of Cryptosystems have
More informationHardware Verification after Installation. D0 Run IIB L1Cal Technical Readiness Review. Presented by Dan Edmunds August 2005
Hardware Verification after Installation D0 Run IIB L1Cal Technical Readiness Review Presented by Dan Edmunds 26-27 August 2005 The purpose of this talk is to describe to the committee how various aspects
More informationBell. Program of Study. Accelerated Digital Electronics. Dave Bell TJHSST
Program of Study Accelerated Digital Electronics TJHSST Dave Bell Course Selection Guide Description: Students learn the basics of digital electronics technology as they engineer a complex electronic system.
More informationPhysical Modelling of Musical Instruments Using Digital Waveguides: History, Theory, Practice
Physical Modelling of Musical Instruments Using Digital Waveguides: History, Theory, Practice Introduction Why Physical Modelling? History of Waveguide Physical Models Mathematics of Waveguide Physical
More informationThis draft is superseded. Please refer to the updated version:
This draft is superseded. Please refer to the updated version: https://people.csail.mit.edu/jgross/personal-website/papers/2019-fiat-crypto-ieee-sp.pdf 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
More informationFLIP-5: Only send data to each taskmanager once for broadcasts
FLIP-5: Only send data to each taskmanager once for broadcasts Status Current state: Under Discussion Discussion thread: https://mail-archives.apache.org/mod_mbox/flink-dev/201606.mbox/%3c1465386300767.94345@tu-berlin.de%3e
More informationObjectives. Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath
Objectives Combinational logics Sequential logics Finite state machine Arithmetic circuits Datapath In the previous chapters we have studied how to develop a specification from a given application, and
More informationHybrid Discrete-Continuous Computer Architectures for Post-Moore s-law Era
Hybrid Discrete-Continuous Computer Architectures for Post-Moore s-law Era Keynote at the Bi annual HiPEAC Compu6ng Systems Week Mee6ng Barcelona, Spain October 19 th 2010 Prof. Simha Sethumadhavan Columbia
More informationEnhancing Performance in Multiple Execution Unit Architecture using Tomasulo Algorithm
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 6.017 IJCSMC,
More informationPut your sound where it belongs: Numerical optimization of sound systems. Stefan Feistel, Bruce C. Olson, Ana M. Jaramillo AFMG Technologies GmbH
Put your sound where it belongs: Stefan Feistel, Bruce C. Olson, Ana M. Jaramillo Technologies GmbH 166th ASA, San Francisco, 2013 Sound System Design Typical Goals: Complete Coverage High Level and Signal/Noise-Ratio
More informationLab 2: Hardware/Software Co-design with the Wimp51
Lab 2: Hardware/Software Co-design with the Wimp51 CpE 214: Digital Engineering Lab II Last revised: February 26, 2013 (CAC) Hardware software co-design, now standard in industry, is an approach that brings
More informationNON-UNIFORM KERNEL SAMPLING IN AUDIO SIGNAL RESAMPLER
NON-UNIFORM KERNEL SAMPLING IN AUDIO SIGNAL RESAMPLER Grzegorz Kraszewski Białystok Technical University, Electrical Engineering Faculty, ul. Wiejska 45D, 15-351 Białystok, Poland, e-mail: krashan@teleinfo.pb.bialystok.pl
More informationL11/12: Reconfigurable Logic Architectures
L11/12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of California, Berkeley,
More informationSoftware architecture and larger system design issues
Software architecture and larger system design issues ecture 3: Monitor synchonization Topics: Programming language specifics (ACE) More on monitor synchronization More problems with concurrent software
More informationAN2056 APPLICATION NOTE
APPLICATION NOTE Extension of the SRC DiSEcQ 1 standard for control of Satellite Channel Router based one-cable LNBs 1 System overview 1.1 Description ST Microelectronics has introduced a new device that
More informationRetiming Sequential Circuits for Low Power
Retiming Sequential Circuits for Low Power José Monteiro, Srinivas Devadas Department of EECS MIT, Cambridge, MA Abhijit Ghosh Mitsubishi Electric Research Laboratories Sunnyvale, CA Abstract Switching
More informationFilm Grain Technology
Film Grain Technology Hollywood Post Alliance February 2006 Jeff Cooper jeff.cooper@thomson.net What is Film Grain? Film grain results from the physical granularity of the photographic emulsion Film grain
More informationAcoustic Measurements Using Common Computer Accessories: Do Try This at Home. Dale H. Litwhiler, Terrance D. Lovell
Abstract Acoustic Measurements Using Common Computer Accessories: Do Try This at Home Dale H. Litwhiler, Terrance D. Lovell Penn State Berks-LehighValley College This paper presents some simple techniques
More informationNote Gate 2 Audio Unit
Note Gate 2 Audio Unit User Manual Copyright 2007 2012, Audiowish Table of Contents Preface 4 About this manual 4 About Audiowish 4 Note Gate 2 Audio Unit 5 Introduction 5 System requirements 5 Installation
More informationAlgorithms, Lecture 3 on NP : Nondeterministic Polynomial Time
Algorithms, Lecture 3 on NP : Nondeterministic Polynomial Time Last week: Defined Polynomial Time Reductions: Problem X is poly time reducible to Y X P Y if can solve X using poly computation and a poly
More informationExperiment 3: Basic Embedded System Analysis and Design
University of Jordan Faculty of Engineering and Technology Department of Computer Engineering Embedded Systems Laboratory 0907334 3 Experiment 3: Basic Embedded System Analysis and Design Objectives Empowering
More informationPRODUCT GUIDE CEL5500 LIGHT ENGINE. World Leader in DLP Light Exploration. A TyRex Technology Family Company
A TyRex Technology Family Company CEL5500 LIGHT ENGINE PRODUCT GUIDE World Leader in DLP Light Exploration Digital Light Innovations (512) 617-4700 dlinnovations.com CEL5500 Light Engine The CEL5500 Compact
More informationModernized Day Sensor Assembly (M-DSA)
Modernized Assembly (M-DSA) October 22, 2013 Matt Hoffman Director, M-TADS/PNVS Missiles and Fire Control LTC Van Riper Apache Sensors Product Manager U.S. Army 2013 Lockheed Martin Corporation. All Rights
More informationILDA Image Data Transfer Format
INTERNATIONAL LASER DISPLAY ASSOCIATION Technical Committee Revision 006, April 2004 REVISED STANDARD EVALUATION COPY EXPIRES Oct 1 st, 2005 This document is intended to replace the existing versions of
More informationEnsemble. Multi-Axis Motion Controller Software. Up to 10 axes of coordinated motion
Ensemble Multi-Axis Motion Controller Software Up to 10 axes of coordinated motion Multiple 10-axis systems can be controlled by a single PC via Ethernet or USB Controller architecture capable of coordinating
More informationLow-Power Scan Testing and Test Data Compression for System-on-a-Chip
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 5, MAY 2002 597 Low-Power Scan Testing and Test Data Compression for System-on-a-Chip Anshuman Chandra, Student
More information400GBASE-SR16 Cabling
400GBASE-SR16 Cabling Paul Kolesar, CommScope Robert Lingle, OFS Alan Ugolini, USConec IEEE P802.3bs September 2014 Supporters John Abbott, Corning Gary Bernstein, Leviton Mabud Choudhury, CommScope Chris
More informationUpdate on HPC Use for Weather and Climate. Steve Finn Emagine IT Steve Conway IDC
Update on HPC Use for Weather and Climate Steve Finn Emagine IT Steve Conway IDC Introduction See Slides from our September meeting https://hpcuserforum.com/presentations.html See videos at http://insidehpc.com/tag/hpc-user-forum/
More information