Microprocessor Design

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Barnaby Horton
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1 Microprocessor Design Principles and Practices With VHDL Enoch O. Hwang Brooks / Cole 2004

3 To my wife and children Windy, Jonathan and Michelle

5 Contents 1. Designing a Microprocessor Overview of a Microprocessor Design Abstraction Levels Examples for a 2-input Multiplexer Behavioral Level Gate Level Transistor Level VHDL Synthesis Going Forward Summary Checklist... 9 Index Digital Circuits Binary Numbers Binary Switch Basic Logic Operators and Logic Expressions Truth Tables Boolean Algebra and Boolean Function Boolean Algebra Duality Principle Boolean Function and the Inverse Minterms and Maxterms Minterms Maxterms Canonical, Standard, and non-standard Forms Logic Gates and Circuit Diagrams Example: Designing a Car Security System Introduction to VHDL VHDL code for a 2-input NAND gate VHDL code for a 3-input NOR gate VHDL code for a function Summary Checklist Exercises Index 27 3 Combinational Circuits Analysis of Combinational Circuits With a Truth Table With a Boolean Function Synthesis of Combinational Circuits Technology Mapping Minimization of Combinational Circuits Karnaugh (K) Maps Don t-cares * Quine-McCluskey (Tabulation) Method * Timing Hazards and Glitches Segment Decoder Example VHDL Code for Combinational Circuits Structural BCD to 7-Segment Decoder Dataflow BCD to 7-Segment Decoder Behavioral BCD to 7-Segment Decoder Summary Checklist v -

6 3.9 Exercises Index Combinational Components Signal Naming Conventions Adder Full Adder Ripple-Carry Adder Carry-Lookahead Adder Two s-complement Representation for Negative Numbers Subtractor Adder-Subtractor Combination Arithmetic Logic Unit Decoder Encoder Priority Encoder Multiplexer Using Multiplexers to Implement a Function Tri-state Buffer Comparators Shifter-Rotator Multiplier Summary Checklist Exercises Index Implementation Technologies Physical Abstraction Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) CMOS Logic CMOS Circuits CMOS Inverter CMOS NAND gate CMOS AND gate CMOS NOR and OR Gates Transmission Gate input Multiplexer CMOS Circuit CMOS XOR and XNOR Gates Analysis of CMOS Circuits Using ROMs to Implement a Function Using PLAs to Implement a Function Using PALs to Implement a Function Complex Programmable Logic Device (CPLD) Field-Programmable Gate Array (FPGA) Summary Checklist References Exercises Index Latches and Flip-Flops Bistable Element SR Latch SR Latch with Enable D Latch D Latch with Enable Clock vi -

7 6.7 D Flip-Flop D Flip-Flop with Enable Asynchronus Inputs Description of a Flip-Flop Characteristic Table Characteristic Equation State Diagram Excitation Table Timing Issues Example: Car Security System Version VHDL for Latches and Flip-Flops Implied Memory Element VHDL Code for a D Latch with Enable VHDL Code for a D Flip-Flop VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear * Flip-Flop Types SR Flip-Flop JK Flip-Flop T Flip-Flop Summary Checklist Exercises Index Sequential Circuits Finite-State-Machine (FSM) Model Analysis of Sequential Circuits Excitation Equation Next-state Equation Next-state Table Output Equation Output Table State Diagram Example: Analysis of a Moore FSM Example: Analysis of a Mealy FSM Synthesis of Sequential Circuits State Diagram Next-state Table Implementation Table Excitation Equation and Next-state Circuit Output Table and Equation FSM Circuit Examples: Synthesis of Moore FSMs Example: Synthesis of a Mealy FSM Unused State Encodings Example: Car Security System Version VHDL for Sequential Circuits * Optimization for Sequential Circuits State Reduction State Encoding Choice of Flip-Flops Exercises Selected Answers Index Sequential Components Registers vii -

8 8.2 Shift Registers Serial to Parallel Shift Register Serial-to-Parallel and Parallel-to-Serial Shift Register Counters Binary Up Counter Binary Up-Down Counter Binary Up-Down Counter with Parallel Load BCD Up-Down Counter Register Files Static Random Access Memory Larger Memories More Memory Locations Wider Bit Width Index Datapaths General Datapath Using a General Datapath Timing Issues A More Complex General Datapath VHDL for the Complex General Datapath Dedicated Datapath Selecting Registers Selecting Functional Units Data Transfer Methods Examples: Designing Dedicated Datapaths Using a Dedicated Datapath VHDL for a Dedicated Datapath * Optimization for Datapaths Functional Unit Sharing Register Sharing Bus Sharing Summary Checklist Index Control Units Constructing the Control Unit Generating Status Signals Timing Issues ASM Charts and State Action Tables ASM Charts State Action Tables Summary Checklist Exercises Index Dedicated Microprocessors Manual Construction of a Dedicated Microprocessor FSM + D Model Using VHDL FSMD Model Behavioral Model Examples Index General-Purpose Microprocessors Overview of the CPU Design viii -

9 12.2 Instruction Set Two Operand Instructions One Operand Instructions Instructions Using a Memory Address Jump Instructions Datapath Input multiplexer Conditional Flags Accumulator Register File ALU Shifter / Rotator Output Buffer Control Word VHDL Code for the Datapath Control Unit Reset Fetch Decode Execute VHDL Code for the Control Unit CPU Top-level Computer Input Output Memory Clock VHDL Code for the Complete Computer Examples Appendix A VHDLSummary... 2 A.1 Basic Language Elements... 2 A.1.1 Comments... 2 A.1.2 Identifiers... 2 A.1.3 Data Objects... 2 A.1.4 Data Types... 2 A.1.5 Data Operators... 5 A.1.6 ENTITY... 5 A.1.7 ARCHITECTURE... 6 A.1.8 GENERIC... 7 A.1.9 PACKAGE... 8 A.2 Dataflow Model Concurrent Statements... 9 A.2.1 Concurrent Signal Assignment... 9 A.2.2 Conditional Signal Assignment... 9 A.2.3 Selected Signal Assignment A.2.4 Dataflow Model Example A.3 Behavioral Model Sequential Statements A.3.1 PROCESS A.3.2 Sequential Signal Assignment A.3.3 Variable Assignment A.3.4 WAIT A.3.5 IF THEN ELSE A.3.6 CASE A.3.7 NULL A.3.8 FOR A.3.9 WHILE ix -

10 A.3.10 LOOP A.3.11 EXIT A.3.12 NEXT A.3.13 FUNCTION A.3.14 PROCEDURE A.3.15 Behavioral Model Example A.4 Structural Model Statements A.4.1 COMPONENT Declaration A.4.2 PORT MAP A.4.3 OPEN A.4.4 GENERATE A.4.5 Structural Model Example A.5 Conversion Routines A.5.1 CONV_INTEGER() A.5.2 CONV_STD_LOGIC_VECTOR(,) Index Appendix B MAX+plus II Tutorial B.1 Getting Started... 2 B.1.1 Preparing a Folder for the Project... 2 B.1.2 Starting MAX+plus II... 2 B.1.3 Creating a Project... 3 B.1.4 Editing the VHDL Source Code... 4 B.2 Synthesis for Functional Simulation... 4 B.3 Circuit Simulation... 5 B.3.1 Selecting Input Test Signals... 5 B.3.2 Customizing the Waveform Editor... 6 B.3.3 Assigning Values to the Input Signals... 7 B.3.4 Saving the Waveform File... 7 B.3.5 Starting the Simulator... 8 Appendix C MAX+plus II Tutorial C.1 Getting Started... 2 C.1.1 Preparing a Folder for the Project... 2 C.1.2 Creating a Project... 2 C.1.3 Editing the VHDL Source Code... 2 C.2 Synthesis for Functional Simulation... 3 C.3 Circuit Simulation... 3 C.4 Using the Floorplan Editor... 4 C.4.1 Selecting the Target Device... 4 C.4.2 Maping the I/O Pins with the Floorplan Editor... 5 C.5 Synthesis for Programming the PLD... 6 C.5.1 Bringing Up the Compiler Window... 6 C.6 Programming the FPGA... 7 C.6.1 Connecting and Configuring the UP2 Board... 7 C.6.2 I/O Connections for the Circuit... 8 C.6.3 Programming the PLD... 8 C.7 Testing the Hardware x -

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS)

DIGITAL SYSTEM DESIGN UNIT I (2 MARKS) 1. Convert Binary number (111101100) 2 to Octal equivalent. 2. Convert Binary (1101100010011011) 2 to Hexadecimal equivalent. 3. Simplify the following Boolean function