DDR3 SDRAM REGISTERED DIMM MODULE,1.5V 8GByte - 1GX72 AVF721GR64F7066G7-BP

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1 REGISTERED DIMM,1.5 8GByte AF721GR64F7066G7BP FEATURES JEDEC DDR2 PC MT/s, Lead Free, RoHS compliant, Clock frequency: 533MHz with CAS latency byte serial EEPROM Data input and output masking Programmable burst length: 4, 8 Programmable burst type: sequential and interleave Programmable CAS latency: 7 Bidirectional Differential DataStrobe Gold card edge fingers 8K refresh per 64ms Low active and standby current coumption On Die Termination (ODT) Auto refresh and self refresh capability Doublesided module 30mm (1.18 inch) height DESCRIPTION The AF721GR64F7066G7BP is a Registered DIMM module. This module is JEDEC MO269 R/C H Registered DIMM. The module has all the addresses and control signals buffered to reduce capacitive loading. The module utilizes a phase lock loop to reduce the capacitive loading on the clock signals and to synchronize all SDRAM input clocks with the system clock. A 256 byte Temp Seor serial EEPROM on board can be used to store module information such as timing, configuration, deity, etc. as well as to monitor the module temperature and prevent the module from exceeding the maximum operating temperature. The AF721GR64F7066G7BP memory module is 8GByte and organized as ECC array using (36) 256MX8 s in leadfree FBGA packages. The module PCB is fabricated using the latest technology design, tenlayer printed circuit board substrate cotruction with low ESR decoupling capacitors onboard for high reliability and low noise. PHYSICAL DIMENSIONS (5.25) 1.27 (0.050) SPD REG 17.3 (0.681) 30 (1.181) 3.81 (0.15) SIDE SIDE NOTES: All dimeio are in milimeters (inches) and for reference only Refer to the JEDEC document for additional information. Copyright 2010 Ph (512) Fax (512) Rev B (Apr 2010) Page 1 of 7 AF721GR64F7066G7BP.vsd

2 REGISTERED DIMM,1.5 AF721GR64F7066G7BP FUNCTIONAL BLOCK DIAGRAM RS3# RS2# RS1# RS0# S0 S0# S1 S1# S2 S2# S3 S3# S4 S4# S5 S5# S6 S6# S7 S7# S8 S8# CB0 CB1 CB2 CB3 DM CS# S S# U1b ZQ DM CS# S S# U2b ZQ DM CS# S S# U3b ZQ DM CS# S S# U4b ZQ DM CS# S S# U8b ZQ DM CS# S S# U9b ZQ DM CS# S S# U10b ZQ DM CS# S S# U11b ZQ DM CS# S S# U5b ZQ DM CS# S S# U1t ZQ DM CS# S S# U2t ZQ DM CS# S S# U3t ZQ DM CS# S S# U4t ZQ DM CS# S S# U8t ZQ DM CS# S S# U9t ZQ DM CS# S S# U10t ZQ DM CS# S S# U11t ZQ DM CS# S S# U5t ZQ DM CS# S S# U30b ZQ DM CS# S S# U29b ZQ DM CS# S S# U28b ZQ DM CS# S S# U27b ZQ DM CS# S S# U24b ZQ DM CS# S S# U23b ZQ DM CS# S S# U22b ZQ DM CS# S S# U21b ZQ DM CS# S S# U26b ZQ DM CS# S S# U30t ZQ DM CS# S S# U29t ZQ DM CS# S S# U28t ZQ DM CS# S S# U27t ZQ DM CS# S S# U24t ZQ DM CS# S S# U23t ZQ DM CS# S S# U22t ZQ DM CS# S S# U21t ZQ DM CS# S S# U26t ZQ S9 S9# S10 S10# S11 S11# S12 S12# S13 S13# S14 S14# S15 S15# S16 S16# S17 S17# CB4 CB5 CB6 CB7 DM CS# S S# U12b ZQ DM CS# S S# U13b ZQ DM CS# S S# U14b ZQ DM CS# S S# U15b ZQ DM CS# S S# U17b ZQ DM CS# S S# U18b ZQ DM CS# S S# U19b ZQ DM CS# S S# U20b ZQ DM CS# S S# U16b ZQ DM CS# S S# U12t ZQ DM CS# S S# U13t ZQ DM CS# S S# U14t ZQ DM CS# S S# U15t ZQ DM CS# S S# U17t ZQ DM CS# S S# U18t ZQ DM CS# S S# U19t ZQ DM CS# S S# U20t ZQ DM CS# S S# U16t ZQ DM CS# S S# U39b ZQ DM CS# S S# U38b ZQ DM CS# S S# U37b ZQ DM CS# S S# U36b ZQ DM CS# S S# U34b ZQ DM CS# S S# U33b ZQ DM CS# S S# U32b ZQ DM CS# S S# U31b ZQ DM CS# S S# U35b ZQ DM CS# S S# U39t ZQ DM CS# S S# U38t ZQ DM CS# S S# U37t ZQ DM CS# S S# U36t ZQ DM CS# S S# U34t ZQ DM CS# S S# U33t ZQ DM CS# S S# U32t ZQ DM CS# S S# U31t ZQ DM CS# S S# U35t ZQ S0# S1# S2# S3# BA0BA2 A0A15 RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 PAR_IN RESET# CK0 CK0# R E G I S T E R S & P L L RS0#: Rank 0 RS1#: Rank 1 RS2#: Rank 2 RS3#: Rank 3 RBA0RBA2: RA0RA13: RRAS#: RCAS#: RWE#: RCKE0: Rank 0, Rank 2 RCKE1: Rank 1, Rank 3 RODT0: Rank 0, Rank 2 RODT1: Rank 1, Rank 3 tied to at SDRAM ERR_OUT# Rank 0 = U1bU11b, U12bU20b Rank 1 = U1tU11t, U12tU20t Rank 2 = U21bU30b, U31bU39b Rank 3 = U21tU30t, U31tU39t SCL TEMP SENSOR SPD EEPROM WP A0 A1 A2 SA0 SA1 SA2 SDA DDSPD DD TT REFCA REF TEMP SENSOR SPD EEPROM Copyright 2010 Ph (512) Fax (512) Rev B (Apr 2010) Page 2 of 7 AF721GR64F7066G7BP.vsd

3 REGISTERED DIMM,1.5 AF721GR64F7066G7BP CONFIGURATIONS 1 REF A A DD S DD 212 S S3# 63 NF 93 S5# S12# 183 DD 213 S14# S3 64 NF 94 S CK DD S CK0# S0# DD S9# DD S REFCA EENT# Par_In CB4 188 A CB0 69 DD CB5 189 DD CB1 70 A BA BA DD S8# 72 DD 102 S6# # 192 RAS# # S8 73 WE# 103 S S0# CAS# S CB6 194 DD S1# 45 CB2 75 DD S10# 165 CB7 195 ODT S1 46 CB3 76 S1# A ODT NC 197 DD TT 78 DD RESET# 198 NC TT 79 NC CKE CKE DD S DD S7# A S16# BA S A NC/Err_Out# S DD 203 S S2# 54 DD 84 S4# S11# 174 A S13# S2 55 A11 85 S A A DD DDSPD DD SA # 177 A SA A SCL A SDA A SA DD DD TT A TT Pin Names Description Pin Names Description CK0 Clock Inputs, positive line ODT0~ODT1 On Die Termination CK0# Clock Inputs, negative line 0~63 Data Input/Output CKE0, CKE1 Clock Enables CB0~CB7 Data check bits Input/Output RAS# Row Address Strobe S0~DSQ17 Data Strobes CAS# Column Address Strobe S0#~S17# Data Strobes, negative line WE# Write Enable NF No Function S0#~S3# Chip Selects NC No Connect A0~A15 Address Inputs NC No Connect A10/AP Address Input/Auto Recharge DD Core Power BA0~BA2 DDR2 SDRAM Bank Address D I/O Power SCL Serial Presence Detect (SPD) Clock Input Ground SDA SPD Data Input/Output REFCA, REF Reference oltage SA0~SA2 SPD Address DDSPD SPD Power Par_In Parity bit for the Address and Control bus TT Termination oltage Err_Out# Parity error found in the Address & Control bus RESET# Force all registered outputs LOW Copyright 2010 Ph (512) Fax (512) Rev B (Apr 2010) Page 3 of 7 AF721GR64F7066G7BP.vsd

4 REGISTERED DIMM,1.5 AF721GR64F7066G7BP SPD TABLE A B C D E F 0 OF SPD BYTES USED SPD REISON DRAM DEICE TYPE TYPE (FORM FACTOR) SDR DEICE DENSITY & BANKS SDR DEICE ROW & COLUMN COUNT NOMINAL DD RANKS & DEICE COUNT ECC TAG & MEMORY BUS WIDTH FINE TIMEBASE DIIDEND/ DIISOR MEDIUM TIMEBASE DIIDEND MEDIUM TIMEBASE DIISOR MIN SDRAM CYCLE TIME (min ) BYTE 13 CAS LATENCIES SUPPORTED (CL4CL11) CAS LATENCIES SUPPORTED (CL12CL18) 0x92 0x10 0x0B 0x01 0x02 0x12 0x18 0x0B 0x52 0x01 0x08 0x0F 0x1C 1 MIN CAS LATENCY TIME (t AAmin ) MIN WRITE RECOERY TIME (t WRmin ) MIN RAS# TO CAS# DELAY (t RCDmin ) MIN ROW ACTIE TO ROW ACTIE DELAY MIN ROW UPPER NIBBLE MIN ACTIE TO MIN ACTIE TO MIN REFRESH PRECHARGE FOR PRECHARGE ACTIE/ RECOERY DELAY (t t RAS & t DELAY REFRESH DELAY RPmin ) RC (t RASmin ) DELAY (t RCmin ) (t RFCmin ) LSB MIN REFRESH MIN INTERNAL MIN INTERNAL RECOERY WRITE TO READ TO DELAY READ CMD PRECHARGE (t DELAY CMD DELAY RFCmin ) MSB MIN FOUR ACTIE WINDOW DELAY MIN FOUR ACTIE WINDOW DELAY SDR DEICE OUTPUT DRIERS SUPPORTED SDRAM DEICE THERMAL & REFRESH (t RRDmin ) (t WTRmin ) (t RTPmin ) (t FAWmin ) MSB (t FAWmin ) LSB OPTIONS 0x69 0x78 0x69 0x3C 0x69 0x11 0x2C 0x95 0x70 0x03 0x3C 0x3C 0x01 0x2C 0x83 0x8D SDRAM 2 THERMAL SENSOR DEICE TYPE 0x80 0x80 REFERENCE ADDRESS 3 HEIGHT (NOMINAL) THICKNESS (MAX) RAW CARD ID MAPG/ ATTRIBUTES 0x0F 0x11 0x05 0x0A CRC CRC 7 MFR ID (LSB) MFR ID (MSB) MFR LOCATION ID MFR YEAR MFR WEEK 0x80 0xCE 0xAA 0x A B C D E F Copyright 2010 Ph (512) Fax (512) Rev B (Apr 2010) Page 4 of 7 AF721GR64F7066G7BP.vsd

5 REGISTERED DIMM,1.5 AF721GR64F7066G7BP ABSOLUTE MAXIMUM RATINGS (I) Item oltage on power supply or any input pin relative to SS oltage on power supply or any input pin relative to SS Storage temperature Operating temperature Symbol Rating Unit DDL, D, IN, OUT 0.4 ~ (I) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditio as detailed in the operational sectio of this data sheet. All voltages are referenced to SS that ties to ground. DD t STG t OPER 1.0 ~ 2.3 O C 55 to to 95 O C DC OPERATING CONDITIONS (II) Item Symbol Min. Typical Max. Unit Supply voltage DD Supply voltage for DLL DLL Supply voltage for Output D Input Reference oltage REF 0.49* D 0.5* D 0.51* D m Termination oltage TT REF 0.04 REF REF (II) Recommended operating conditio unless otherwise noted. All voltages are referenced to SS or ground. DC CHARACTERISTICS (III) ( DD = 1.5 ± 0.1, SS = 0) SYMBOL 8K 64ms DDR31066 with CL = 7 CONFIG. TYPICAL MAX UNIT Operating one bank active precharge current t RC t RC (IDD) I DD Precharge Powerdown Current All banks idle,powerdown mode,cke IL (max) I DD2P 288 Precharge Standby Current (All bank idle); (CKE is high, CS# is high), = (IDD) I DD2N 954 Active powerdown Current All banks active (CKE is low) I DD3P 684 Active Standby Current (Non Power Down Mode) All banks active;cke is high I DD3N 1044 Burst Mode Operating Current All banks Active ( (min), I OL = 0 READ WRITE I DD Auto Refresh Current All banks Active t RC = t RFC (min) I DD Self Refresh Current CKE 0.2 Normal Low Power I DD6 324 * Copyright 2010 Ph (512) Fax (512) Rev B (Apr 2010) Page 5 of 7 AF721GR64F7066G7BP.vsd

6 REGISTERED DIMM,1.5 AF721GR64F7066G7BP CAPACITANCE (I) PARAMETER CONFIG. SYMBOL MIN TYP MAX UNIT Input capacitance (A[15:0], BA[2:0], RAS#, CAS#, WE#) C I2 TBD pf Input capacitance (CKE, CS#) C IN3 TBD pf Input capacitance (CK, CK#) Data Input capacitance (, S, S#, DM) C CK TBD pf C I0 TBD pf OPERATING AC CHARACTERISTICS () PARAMETER SYM MIN MAX CAS Latency 7 Clock cycle time CAS Latency 6 Row cycle time Row active time RAS# to CAS# delay Row precharge time Row active to row active delay Write recovery time CAS# to CAS# command delay Clock high level width Clock low level width Sout access time from CK or CK# Output data access time from CK or CK# S skew for S & associated signals Read preamble Read postamble Data out high impedance time from CK or CK# Write command to first S latching traition Sin high level width Sin low level width Address and control input setup time Address and control input hold time Mode register set cycle time & DM set up time to S & DM hold time to S & DM input pulse width Write Preamble Write Postamble hold skew factor Control & Address input pulse width for each input < t RC t RAS *t REF t RCD t RP t RRD 7.5 t WR 15 t CCD 4 t CH 0.43 t CL 0.43 t SCK t AC t SQ 150 t RPRE 0.90 t RPST 0.30 t HZQ 300 t SS WL0.25 WL+0.25 t SH t SL t IS 125 t IH 200 t MRD 4 t DS 30 t DH t DIPW t WPRE t WPST t QHS t IPW UNIT n CK. alues in this table are based on SDRAM component data sheet and may vary from one DRAM manufacturer to another. Copyright 2010 Ph (512) Fax (512) Rev B (Apr 2010) Page 6 of 7 AF721GR64F7066G7BP.vsd

7 REGISTERED DIMM,1.5 AF721GR64F7066G7BP Avant Ordering Guides A F 72 1G R 64 F G 7 INENTORY MOD. TYPE ORG. DENSITY PARITY TYPE OLT. FEATURE SPEED MODE RE A=AANT F = 240 DDR3 DIMM 72=X72 1G= 1024M R=REGISTERED 64 = 32Mx8x8 F =1.5 7 = CAS LATENCY MT/s G=DDR3 RE=7 () SDRAM Other optio may be available. Call for specific part number information on optio not listed. Copyright 2010, reserves the right to change products or specificatio without notice. Ph (512) Fax (512) Rev B (Apr 2010) Page 7 of 7 AF721GR64F7066G7BP.vsd

V6118 EM MICROELECTRONIC - MARIN SA. 2, 4 and 8 Mutiplex LCD Driver

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