V54C3128(16/80/40)4VB*I 128Mbit SDRAM, INDUSTRIAL TEMPERATURE 3.3 VOLT, TSOP II / FBGA 8M X 16, 16M X 8, 32M X 4

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1 128Mbit SDRAM, INDUSTRIA TEMPERATURE 3.3 VOT, TSOP II / FBGA 8M 16, 16M 8, 32M 4 6 7PC 7 System Frequency (f CK ) 166 Mz 143 Mz 143 Mz Clock Cycle Time (t CK3 ) 6 ns 7 ns 7 ns Clock Access Time (t AC3 ) atency = ns 5.4 ns 5.4 ns Clock Access Time (t AC2 ) atency = ns 5.4 ns 6 ns Features 4 banks x 2Mbit x 16 organization 4 banks x 4Mbit x 8 organization 4 banks x 8Mbit x 4 organization igh speed data transfer rates up to 166 Mz Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge Single Pulsed Interface Data Mask for Read/Write Control Four Banks controlled by BA0 & BA1 Programmable atency: 2, 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst ength: 1, 2, 4, 8, and full page for Sequential Type 1, 2, 4, 8 for Interleave Type Multiple Burst Read with Single Write Operation Automatic and Controlled Random Column Address every CK (1-N Rule) Power Down Mode Auto Refresh and Self Refresh Refresh Interval: 4096 cycles/64 ms Available in 54-ball FBGA, 60-ball FBGA and 54-Pin TSOPII VTT Interface Single (+3.0 V ~3.3V)±0.3 V Power Supply Industrial Temperature (TA): -40C to +85C Description The is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4. The achieves high speed data transfer rates up to 166 Mz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166 Mz is possible depending on burst length, latency and speed grade of the device. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Power C/S/T 6 7PC 7 Std. Temperature Mark -40 C to +85 C I Rev. 1.5 June

2 ProMOS TECNOOGIES Part Number Information V 5 4 C V B T 7 5 I PC ProMOS ORGANIZATION & REFRES 1Mx16, 2K : Mx16, 4K : 6516 PC : C2 TYPE 32Mx4, 4K : Mx16, 4K : BANK: C3 54 : SDRAM 16Mx8, 4K : : MOBIE SDRAM 64Mx4, 8K : Mx16, 8K : TEMPERATURE 32Mx8, 8K : BANK: 0-70C 128Mx4, 8K : Mx16, 8K : I : C 64Mx8, 8K : E : C CMOS BANKS SPEED VOTAGE 2 : 2 BANKS I/O 10 : 100Mz 7 : 143Mz 4 : 3.0V 3 : 3.3 V 2 : 2.5 V 1 : 1.8 V OTER 4 : 4 BANKS V: VTT 8 : 125Mz 6 : 166Mz 8 : 8 BANKS 75 : 133Mz 5 : 200Mz REV EVE A: 1st C: 3rd PACKAGE B: 2nd D: 4th EAD GREEN PACKAGE PATING DESCRIPTION SPECIA FEATURE T I TSOP : OW POR GRADE S J 60-Ball FBGA U : UTRA OW POR GRADE C K 54-Ball FBGA B M BGA D N Die-stacked TSOP Z P Die-stacked FBGA * RoS: Restriction of azardous Substances * Green: RoS-compliant and alogen-free Rev.1.5 June

3 ProMOS TECNOOGIES 128Mb SDRAM Ball Assignment (54-Ball FBGA) 16 devices VSS DQ15 VSSQ A VDDQ DQ0 VDD DQ14 DQ13 VDDQ B VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ C VDDQ DQ4 DQ3 Description Pkg. Pin Count FBGA C / K 54 DQ10 DQ9 VDDQ D VSSQ DQ6 DQ5 DQ8 VSS E VDD DQ7 U CK F A11 A9 G BA0 BA1 A8 A7 A6 A0 A1 A10 VSS A5 A4 J A3 A2 VDD 8 devices VSS DQ7 VSSQ A VDDQ DQ0 VDD 4 devices VSS VSSQ A VDDQ VDD DQ6 VDDQ B VSSQ DQ1 DQ3 VDDQ B VSSQ DQ0 DQ5 VSSQ C VDDQ DQ2 VSSQ C VDDQ DQ4 VDDQ D VSSQ DQ3 DQ2 VDDQ D VSSQ DQ1 VSS E VDD VSS E VDD CK F CK F A11 A9 G BA0 BA1 A8 A7 A6 A0 A1 A10 VSS A5 A4 J A3 A2 VDD A11 A9 G BA0 BA1 A8 A7 A6 A0 A1 A10 VSS A5 A4 J A3 A2 VDD Rev. 1.5 June

4 ProMOS TECNOOGIES 128Mb SDRAM Ball Assignment (60-Ball FBGA) Description Pkg. Pin Count FBGA S / J 60 A B C D E F G J K M N P R DQ15 VSS DQ7 DQ14 VDDQ DQ11 DQ10 VDDQ A11 VSSQ DQ13 DQ12 VSSQ DQ9 DQ8 VSS U CK A9 VDDQ DQ5 VDDQ A11 A8 A6 A4 A7 A5 VSS A8 A6 A4 VSS VSSQ DQ6 VSSQ DQ4 VSS CK A9 A7 A5 VSS 60 Pin WBGA PIN CONFIGURATION 128 Mb SDRAM Top View Ball Assignment 4 (60-Ball TrueP) PIN A1 index 7 8 VSS VDD VDDQ VDDQ A11 VSSQ DQ3 VSSQ DQ2 VSS CK A9 VDDQ DQ0 VDDQ DQ1 VDD # # BA1 VSSQ VSSQ # # BA0 A8 A6 A4 A7 A5 VSS A0 A2 VDD A10 A1 A VDD DQ0 VDDQ DQ1 VSSQ DQ2 VDDQ DQ3 VSSQ VDD # # # # BA1 BA0 A0 A10 A2 A1 VDD A VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD # # # # BA1 BA0 A0 A10 A2 A1 VDD A3 A B C D E F G J K M N P R TOP VIEW Rev. 1.5 June

5 ProMOS TECNOOGIES 128Mb SDRAM Ball Assignment (54-Pin TSOP II) Description Pkg. Pin Count TSOP-II T / I 54 x16 Configuration Pin Names Top View CK Clock Input Clock Enable V CC I/O 1 V CCQ I/O 2 I/O 3 V SSQ I/O 4 I/O 5 V CCQ I/O 6 I/O 7 V SSQ I/O 8 V CC BA0 BA1 A 10 A 0 A 1 A 2 A 3 V CC V SS I/O 16 V SSQ I/O 15 I/O 14 V CCQ I/O 13 I/O 12 V SSQ I/O 11 I/O 10 V CCQ I/O 9 V SS U CK A 11 A 9 A 8 A 7 A 6 A 5 A 4 V SS A 0 A 11 BA0, BA1 I/O 1 I/O 16, U V CC V SS V CCQ V SSQ Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.0V~3.3V) Ground Power for I/O s (+3.0V~3.3V) Ground for I/O s Not connected Rev. 1.5 June

6 ProMOS TECNOOGIES 128Mb SDRAM Ball Assignment (54-Pin TSOP II) Description Pkg. Pin Count TSOP-II T / I 54 x8 Configuration Pin Names Top View CK Clock Input Clock Enable V CC I/O 1 V CCQ I/O 2 V SSQ I/O 3 V CCQ I/O 4 V SSQ V CC BA0 BA1 A 10 A 0 A 1 A 2 A 3 V CC V SS I/O 8 V SSQ I/O 7 V CCQ I/O 6 V SSQ I/O 5 V CCQ V SS CK A 11 A 9 A 8 A 7 A 6 A 5 A 4 V SS A 0 A 11 BA0, BA1 I/O 1 I/O 8 V CC V SS V CCQ V SSQ Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.0V~3.3V) Ground Power for I/O s (+3.0V~3.3V) Ground for I/O s Not connected Rev.1.5 June

7 ProMOS TECNOOGIES 128Mb SDRAM Ball Assignment (54-Pin TSOP II) Description Pkg. Pin Count TSOP-II T / I 54 x4 Configuration Pin Names Top View CK Clock Input Clock Enable V CC V CCQ I/O 1 V SSQ V CCQ I/O 2 V SSQ V CC BA0 BA1 A 10 A 0 A 1 A 2 A 3 V CC V SS V SSQ I/O 4 V CCQ V SSQ I/O 3 V CCQ V SS CK A 11 A 9 A 8 A 7 A 6 A 5 A 4 V SS A 0 A 11 BA0, BA1 I/O 1 I/O 4 V CC V SS V CCQ V SSQ Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select Data Input/Output Data Mask Power (+3.0V~3.3V) Ground Power for I/O s (+3.0V~3.3V) Ground for I/O s Not connected Rev. 1.5 June

8 ProMOS TECNOOGIES Capacitance* T A = -40 to +85 C, V CC = (3.0V~3.3 V) ± 0.3 V, f = 1 Mhz Symbol Parameter Max. Unit C I1 Input Capacitance (A0 to A11) 3.8 pf C I2 Input Capacitance,,,, CK,, 3.8 pf C IO Output Capacitance (I/O) 6 pf C CK Input Capacitance (CK) 3.5 pf Absolute Maximum Ratings* Operating temperature range to +85 C Storage temperature range to 150 C Input/output voltage to (V CC +0.3) V Power supply voltage to 4.6 V Power dissipation...1 W Data out current (short circuit)...50 ma *Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. *Note:Capacitance is sampled and not 100% tested. Block Diagram x16 Configuration Column Addresses Row Addresses A0 - A8,, BA0, BA1 A0 - A11, BA0, BA1 Column address counter Column address buffer Row address buffer Refresh Counter Row decoder Row decoder Row decoder Row decoder Column decoder Sense amplifier & I(O) bus Memory array Bank x 512 x 16 bit Column decoder Sense amplifier & I(O) bus Memory array Bank x 512 x16 bit Column decoder Sense amplifier & I(O) bus Memory array Bank x 512 x 16 bit Column decoder Sense amplifier & I(O) bus Memory array Bank x 512 x 16 bit Input buffer Output buffer Control logic & timing generator I/O 1 -I/O 16 CK U Rev. 1.5 June

9 ProMOS TECNOOGIES Block Diagram x8 Configuration Column Addresses Row Addresses A0 - A9,, BA0, BA1 A0 - A11, BA0, BA1 Column address counter Column address buffer Row address buffer Refresh Counter Row decoder Row decoder Row decoder Row decoder Column decoder Sense amplifier & I(O) bus Memory array Bank x 1024 x 8 bit Column decoder Sense amplifier & I(O) bus Memory array Bank x 1024 x 8 bit Column decoder Sense amplifier & I(O) bus Memory array Bank x 1024 x 8 bit Column decoder Sense amplifier & I(O) bus Memory array Bank x 1024 x 8 bit Input buffer Output buffer Control logic & timing generator I/O 1 -I/O 8 CK Rev. 1.5 June

10 ProMOS TECNOOGIES Block Diagram x4 Configuration Column Addresses Row Addresses A0 - A9, A11,, BA0, BA1 A0 - A11, BA0, BA1 Column address counter Column address buffer Row address buffer Refresh Counter Row decoder Row decoder Row decoder Row decoder Column decoder Sense amplifier & I(O) bus Memory array Bank x 2048 x 4 bit Column decoder Sense amplifier & I(O) bus Memory array Bank x 2048 x 4 bit Column decoder Sense amplifier & I(O) bus Memory array Bank x 2048 x 4 bit Column decoder Sense amplifier & I(O) bus Memory array Bank x 2048 x 4 bit Input buffer Output buffer Control logic & timing generator I/O 1 -I/O 4 CK Rev.1.5 June

11 ProMOS TECNOOGIES Signal Pin Description Pin Type Signal Polarity Function CK Input Pulse Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Input evel Active igh s the CK signal when high and deactivates the CK signal when low, thereby initiates either the Power Down mode or the Self Refresh mode. Input Pulse Active ow enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue., Input Pulse Active ow When sampled at the positive rising edge of the clock,,, and define the command to be executed by the SDRAM. A0 - A11 Input evel During a ctivate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-An defines the column address (CA0-CAn) when sampled at the rising clock edge.can depends from the SDRAM organization: 32M x 4 SDRAM CA0 CA9, CA11. 16M x 8 SDRAM CA0 CA9. 8M x 16 SDRAM CA0 CA8. In addition to the column address, A10(=) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a command cycle, A10(=) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input evel Selects which bank is to be active. DQx Input Output evel Data Input/Output pins operate in the same manner as on conventional DRAMs. U Input Pulse Active igh The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if is high. VCC, VSS Supply Power and ground for the input buffers and the core logic. VCCQ VSSQ Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. Rev. 1.5 June

12 ProMOS TECNOOGIES Operation Definition All of SDRAM operations are defined by states of control signals,,,, and at the positive edge of the clock. The following list shows the thruth table for the operation commands. Operation Device State n-1 n A0-9, A11 A Row Idle 3 V V V Read Active 3 V V Read w/autoprecharge Active 3 V V Write Active 3 V V Write with Autoprecharge Active 3 V V Row Any V All Any Mode Register Set Idle V V V No Operation Any Device Deselect Any Auto Refresh Idle Self Refresh Entry Idle Self Refresh Exit Idle (Self Refr.) Power Down Entry Idle Active 4 Power Down Exit Any (Power Down) Data Write/Output Enable Active Data Write/Output Disable Active Notes: 1. V = Valid, x = Don t Care, = ow evel, = igh evel 2. n signal is input level when commands are provided, n-1 signal is input level one clock before the commands are provided. 3. These are state of bank designated by 0, 1 signals. 4. Power Down Mode can not entry in the burst cycle. Rev.1.5 June

13 ProMOS TECNOOGIES Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. ike a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VCC and VCCQ pins must be built up simultaneously to the specified voltage when the input signals are held in the NOP state. The power on voltage must not exceed VCC+0.3V on any of the input pins or VCC supplies. The CK signal must be started at the same time. After power on, an initial pause of 200 µs is required followed by a precharge of both banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the and pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.these may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst ength Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a atency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. ow signals of,, and at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. Read and Write Operation When is low and both and are high at the positive edge of the clock, a cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A cycle is triggered by setting high and low at a clock timing after a necessary delay, t RCD, from the timing. is used to define either a read ( = ) or a write ( = ) at this stage. SDRAM provides a wide variety of fast access modes. In a single cycle, serial data read or write operations are allowed at up to a 125 Mz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is 2, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using sequential burst type. Full Page burst operation does not terminate once the burst length has been reached. (At the end of the page, it will wrap to the start address and continue.) In other words, unlike burst length of 2, 4, and 8, full page burst continues until it is terminated using another command. Rev. 1.5 June

14 ProMOS TECNOOGIES Address Input for Mode Set (Mode Register Operation) BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus (Ax) Operation Mode atency BT Burst ength Mode Register Operation Mode Burst Type BA1 BA0 A11 A10 A9 A8 A7 Mode A3 Type atency Burst Read/Burst Write Burst Read/Single Write A6 A5 A4 atency Reserve Reserve Reserve Reserve Reserve Reserve 0 Sequential 1 Interleave Burst ength ength A2 A1 A0 Sequential Interleave Reserve Reserve Reserve Reserve Reserve Reserve Full Page Reserve Similar to the page mode of conventional DRAM s, burst read or write accesses on any column address are possible once the cycle latches the sense amplifiers. The maximum t or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycles is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies with an operation change from a read to a write is possible by exploiting to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be done between different pages. Rev.1.5 June

15 ProMOS TECNOOGIES Burst ength and Sequence: Burst ength Starting Address (A2 A1 A0) 2 xx0 xx1 4 x00 x01 x10 x Sequential Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, Interleave Burst Addressing (decimal) 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, Full Page nnn Cn, Cn+1, Cn+2... not supported Refresh Mode SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the -before- refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when and are held low and and are held high at a clock timing. The mode restores word line after the refresh and no external precharge command is necessary. A minimum trc time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when,, and are low and is high at a clock timing. All of external control signals including the clock are disabled. Returning to high enables the clock and initiates the refresh exit operation. After the exit command, at least one t RC delay is required prior to any access command. Function has two functions for data I/O read and write operations. During reads, when it turns to high at a clock timing, data outputs are disabled and become high impedance after two clock delay ( Data Disable atency t DQZ ). It also provides a data mask function for writes. When is activated, the write operation at the next clock is prohibited ( Write Mask atency t DQW = zero clocks). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary delay (trp) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding low, all of the receiver circuits except CK and are gated off. The Power Down mode does not perform any refresh operations, therefore the device can t remain in Power Down mode longer than the Refresh period (tref) of the device. Exit from this mode is performed by taking high. One clock delay is required for mode entry and exit. Rev. 1.5 June

16 ProMOS TECNOOGIES Auto Two methods are available to precharge SDRAMs. In an automatic precharge mode, the timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read is issued, the Read with Auto- function is initiated. The SDRAM automatically enters the precharge operation one clock before the last data out for latencies 2, two clocks for latencies 3 and three clocks for latencies 4. If CA10 is high when a Write is issued, the Write with Auto- function is initiated. The SDRAM automatically enters the precharge operation a time delay equal to t WR (Write recovery time) after the last data in. Auto- does not apply to full-page burst mode. There is also a separate precharge command available. When and are low and is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for latency = 2, two clocks before the last data out for latency = 3. Writes require a time delay twr from the last data out to apply the precharge command. A full-page burst may be truncated with a command to the same bank. Bank Selection by Address Bits: A10 BA0 BA Bank Bank Bank Bank 3 1 all Banks Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write to interrupt an existing burst operation, use a to interrupt a burst cycle and close the active bank, or using the Burst Stop to terminate the existing burst operation but leave the bank open for future Read or Write s to the same page of the active bank. When interrupting a burst with another Read or Write care must be taken to avoid I/O contention. The Burst Stop, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the I/O pins before the Burst Stop is registered will be written to the memory. The full-page burst is used in conjunction with Burst Terminate to generate arbitrary burst lengths. Rev.1.5 June

17 ProMOS TECNOOGIES Recommended Operation and Characteristics for V-TT T A = -40 to +85 C; V SS = 0 V; V CC,V CCQ = (+3.0V~3.3 V) ± 0.3 V imit Values Parameter Symbol min. max. Unit Notes Input high voltage V I 2.0 Vcc+0.3 V 1, 2 Input low voltage V I V 1, 2 Output high voltage (I OUT = 4.0 ma) V O 2.4 V Output low voltage (I OUT = 4.0 ma) V O 0.4 V Input leakage current, any input (0 V < V IN < 3.6 V, all other inputs = 0 V) Output leakage current (DQ is disabled, 0 V < V OUT < V CC ) I I() 5 5 µa I O() 5 5 µa Note: 1. All voltages are referenced to V SS. 2. V I may overshoot to V CC V for pulse width of < 4ns with 3.3V. V I may undershoot to -2.0 V for pulse width < 4.0 ns with 3.3V. Pulse width measured at 50% points with amplitude measured peak to DC reference. Operating Currents (T A = -40 to +85 C, V CC = (+3.0V~3.3V) ± 0.3V) (Recommended Operating Conditions unless otherwise noted) Max. Symbol Parameter & Test Condition -6-7 / -7PC Unit Note ICC1 Operating Current t RC = t RCMIN., t RC = t CKMIN. Active-precharge command cycling, without Burst Operation 1 bank operation ma 7 ICC2P Standby Current t CK = min. 2 2 ma 7 ICC2PS in Power Down Mode =V I, V I(max) t CK = Infinity 1 1 ma 7 ICC2N Standby Current t CK = min ma ICC2NS in Non-Power Down Mode =V I, V I(max) t CK = Infinity ma ICC3N ICC3P ICC4 ICC5 No Operating Current t CK = min, = V I(min) bank ; active state ( 4 banks) Burst Operating Current t CK = min Read/Write command cycling Auto Refresh Current t CK = min Auto Refresh command cycling V I(MIN.) ma V I(MA.) (Power down mode) 3 3 ma ma 7, ma 7 ICC6 Self Refresh Current Self Refresh Mode, 0.2V ma -version ma Notes: 7.These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t CK and t RC. Input signals are changed one time during t CK. 8.These parameter depend on output loading. Specified values are obtained with output open. Rev. 1.5 June

18 ProMOS TECNOOGIES AC Characteristics 1,2, 3 T A = -40 to +85 C; V SS = 0 V; V DD = (+3.0V~3.3 V) ± 0.3 V, t T = 1 ns imit Values -6-7PC -7 # Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Note Clock and Clock Enable 1 t CK Clock Cycle Time atency = 3 atency = s ns ns 2 t CK Clock Frequency atency = 3 atency = Mz Mz 3 t AC Access Time from Clock atency = 3 atency = 2 _ _ _ ns ns 2, 4 4 t C Clock igh Pulse Width ns 5 t C Clock ow Pulse Width ns 6 t T Transition Tim ns Setup and old Times 7 t IS Input Setup Time ns 5 8 t I Input old Time ns 5 9 t CKS Input Setup Time ns 5 10 t CK old Time ns 5 11 t RSC Mode Register Set-up Time ns 12 t SB Power Down Mode Entry Time ns 13 t DS Data-in setup time ns 14 t D Data-in hold time ns Common Parameters 15 t RCD Row to Column Delay Time ns 6 16 t RP Row Time ns 6 17 t Row Active Time K K K ns 6 18 t RC Row Cycle Time ns 6 19 t RRD (a) to (b) Period ns 6 20 t CCD (a) to (b) Period CK 21 t DP Data-in to for Manual precharge CK Refresh Cycle 22 t REF Refresh Period (4096 cycles) ms 23 t SRE Self Refresh Exit Time CK Rev.1.5 June

19 ProMOS TECNOOGIES imit Values -6-7PC -7 # Symbol Parameter Min. Max. Min. Max. Min. Max. Unit Note Read Cycle 24 t O Data Out old Time ns 2 25 t Z Data Out to ow Impedance Time ns 26 t Z Data Out to igh Impedance Time ns 7 27 t DQZ Data Out Disable atency CK Write Cycle 28 t WR Write Recovery Time for Auto precharge CK 29 t DQW Write Mask atency CK Notes for AC Parameters: 1. For proper power-up see the operation section of this data sheet. 2. AC timing tests have V I = 0.8V and V I = 2.0V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V I and V I. All AC measurements assume t T = 1ns with the AC output load circuit shown in Figure 1. tck CK VI VI V tis ti t T 50 Ohm COMMAND 1.4V Z=50 Ohm tac tz tac to I/O 50 pf OUTPUT 1.4V tz Figure If clock rising time is longer than 1 ns, a time (t T /2 0.5) ns has to be added to this parameter. 5. If t T is longer than 1 ns, a time (t T 1) ns has to be added to this parameter. 6. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after returns high. Self Refresh Exit is not complete until a time period equal to trc is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels Rev. 1.5 June

20 ProMOS TECNOOGIES Timing Diagrams 1. ctivate Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto- 7.1 Burst Write with Auto- 7.2 Burst Read with Auto- 8. Burst Termination 8.1 Termination of a Burst Write Operation 8.2 Termination of a Burst Write Operation 9. AC- Parameters 9.1 AC Parameters for a Write Timing 9.2 AC Parameters for a Read Timing 10. Mode Register Set 11. Power on Sequence and Auto Refresh (CBR) 12. Power Down Mode 13. Self Refresh (Entry and Exit) 14. Auto Refresh (CBR) Rev.1.5 June

21 ProMOS TECNOOGIES Timing Diagrams (Cont d) 15. Random Column Read ( Page within same Bank) 15.1 atency = atency = Random Column Write ( Page within same Bank) 16.1 atency = atency = Random Row Read ( Interleaving Banks) with 17.1 atency = atency = Random Row Write ( Interleaving Banks) with 18.1 atency = atency = Termination of a Burst 19.1 atency = atency = Full Page Burst Operation 20.1 Full Page Burst Read, atency = Full Page Burst Read, atency = Full Page Burst Operation 21.1 Full Page Burst Write, atency = Full Page Burst Write, atency = 3 Rev. 1.5 June

22 ProMOS TECNOOGIES 1. ctivate Cycle ( latency = 3) T0 T1 T T T T T CK ADDRESS Row Addr. Col. Addr Row Addr. Row Addr. t RCD t RRD COMMAND Write A NOP NOP with Auto NOP : or t RC 2. Burst Read Operation (Burst ength = 4, latency = 2, 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8 COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP latency = 2 t CK2, I/O s DOUT A 0 DOUT A 1 DOUT A 2 DOUT A 3 latency = 3 t CK3, I/O s DOUT A 0 DOUT A 1 DOUT A 2 DOUT A 3 Rev.1.5 June

23 ProMOS TECNOOGIES 3. Read Interrupted by a Read (Burst ength = 4, latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK t CCD COMMAND READ A READ B NOP NOP NOP NOP NOP NOP NOP latency = 2 t CK2, I/O s DOUT A 0 DOUT B 0 DOUT B 1 DOUT B 2 DOUT B 3 latency = 3 t CK3, I/O s DOUT A 0 DOUT B 0 DOUT B 1 DOUT B 2 DOUT B Read to Write Interval (Burst ength = 4, latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK Minimum delay between the Read and Write s = 4+1 = 5 cycles t DQZ t DQW COMMAND NOP READ A NOP NOP NOP NOP WRITE B NOP NOP I/O s : or DOUT A0 DIN B0 DIN B1 DIN B2 Must be i-z before the Write Rev. 1.5 June

24 ProMOS TECNOOGIES 4.2 Minimum Read to Write Interval (Burst ength = 4, latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK t DQZ t DQW 1 Clk Interval COMMAND NOP NOP BANK A ACTIVATE NOP READ A WRITE A NOP NOP NOP latency = 2 t CK2, I/O s Must be i-z before the Write DIN A0 DIN A1 DIN A2 DIN A3 : or 4.3 Non-Minimum Read to Write Interval (Burst ength = 4, latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK t DQW t DQZ COMMAND NOP READ A NOP NOP READ A NOP WRITE B NOP NOP latency = 2 t CK1, I/O s latency = 3 t CK2, I/O s DOUT A 0 DOUT A 1 DIN B 0 DIN B 1 DIN B 2 Must be i-z before the Write DOUT A 0 DIN B 0 DIN B 1 DIN B 2 : or Rev.1.5 June

25 ProMOS TECNOOGIES 5. Burst Write Operation (Burst ength = 4, latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND NOP WRITE A NOP NOP NOP NOP NOP NOP NOP I/O s DIN A 0 DIN A1 DIN A 2 DIN A 3 don t care The first data element and the Write are registered on the same clock edge. Extra data is ignored after termination of a Burst. 6.1 Write Interrupted by a Write (Burst ength = 4, latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK t CCD COMMAND NOP WRITE A WRITE B NOP NOP NOP NOP NOP NOP 1 Clk Interval I/O s DIN A 0 DIN B 0 DIN B 1 DIN B 2 DIN B 3 Rev. 1.5 June

26 ProMOS TECNOOGIES 6.2 Write Interrupted by a Read (Burst ength = 4, latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND NOP WRITE A READ B NOP NOP NOP NOP NOP NOP latency = 2 t CK2, I/O s DIN A0 don t care DOUT B 0 DOUT B 1 DOUT B 2 DOUT B 3 latency = 3 t CK3, I/O s DIN A0 don t care don t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the I/O s at least one clock cycle before the Read datapears on the outputs to avoid data contention. 7. Burst Write with Auto- Burst t ength h = 2, 2, latency = 2, 3) CK T0 T1 T2 T3 T4 T5 T6 T7 T8 BANK A WRITEA COMMAN D ACTIVE NOP NOP NOP NOP NOP NOP Auto- NOP I/O s DIN A 0 DIN A 1 t WR * * Begin Autoprecharge Bank can be reactivated after t RP t RP Rev.1.5 June

27 ProMOS TECNOOGIES 7.2 Burst Read with Auto- Burst ength = 4, latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A NOP NOP NOP NOP NOP NOP NOP NOP latency = 2 t CK2, I/O s latency = 3 t CK3, I/O s * DOUT A0 DOUT A 1 DOUT A 2 * t RP DOUT A 3 t RP DOUT A0 DOUT A 1 DOUT A 2 DOUT A 3 * Begin Autoprecharge Bank can be reactivated after t RP Rev. 1.5 June

28 ProMOS TECNOOGIES 8.1 Termination of a Burst Read Operation ( latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND READ A NOP NOP NOP Burst Stop NOP NOP NOP NOP latency = 2 t CK2, I/O s DOUT A 0 DOUT A 1 DOUT A 2 DOUT A 3 latency = 3 t CK3, I/O s DOUT A 0 DOUT A 1 DOUT A 2 DOUT A Termination of a Burst Write Operation ( latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CK COMMAND NOP WRITE A NOP NOP Burst Stop NOP NOP NOP NOP latency = 2,3 I/O s DIN A0 DIN A1 DIN A2 don t care Input data for the Write is masked. Rev.1.5 June

29 ProMOS TECNOOGIES 9.1 AC Parameters for Write Timing Burst ength = 4, atency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK t C t C t CK2 t CKS t IS t I Begin Auto Begin Auto t CK t IS t I t I RAx RBx RAy RAz RBy t IS Addr RAx CAx RBx CBx RAy RAy RAz RBy t RCD t DS t RC trp t D t DP t RRD I/O i-z Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 Write with Auto Write with Auto Write Rev. 1.5 June

30 ProMOS TECNOOGIES \ 9.2 AC Parameters for Read Timing Burst ength = 2, atency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CK t C t C t CK2 t CKS t IS t I Begin Auto t CK t I RAx RBx RAy t IS Addr RAx CAx RBx RBx RAy t RRD t t RC I/O t RCD t Z t AC2 t AC2 t O t Z i-z Ax0 Ax1 Bx0 Bx1 t RP t Z Read Read with Auto Rev.1.5 June

31 ProMOS TECNOOGIES \ 10. Mode Register Set T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK 2 Clock min. t RSC Address Key Addr All Banks Mode Register Set Any Rev. 1.5 June

32 ProMOS TECNOOGIES \ 11. Power on Sequence and Auto Refresh (CBR) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK igh level is required Minimum of 2 Refresh Cycles are required 2 Clock min. Address Key Addr i-z I/O trp t RC All Banks 1st Auto Refresh 2nd Auto Refresh Mode Register Set Any Inputs must be stable for 200 µs Rev.1.5 June

33 ProMOS TECNOOGIES \ 12. Power Down Mode Burst ength = 4, atency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tsb tcks RAx Addr RAx I/O i-z Power Down Mode Entry Power Down Mode Exit Any Rev. 1.5 June

34 ProMOS TECNOOGIES 13. Self Refresh (Entry and Exit) CK Addr I/O i-z All Banks must be idle Self Refresh Entry t CKS tsre trc Begin Self Refresh Exit Self Refresh Exit issued Self Refresh Exit Rev.1.5 June

35 ProMOS TECNOOGIES \ 14. Auto Refresh (CBR) Burst ength = 4, atency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck2 RAx Addr RAx CAx trp trc trc (Minimum Interval) i-z I/O Ax0 Ax1 Ax2 Ax3 All Banks Auto Refresh Auto Refresh Read Rev. 1.5 June

36 ProMOS TECNOOGIES \) 15.1 Random Column Read (Page within same Bank) (1 of 2) Burst ength = 4, atency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck2 RAw RAz Addr RAw CAw CAx CAy RAz CAz I/O i-z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Az0 Az1 Az2 Az3 Read Read Read Read Rev.1.5 June

37 ProMOS TECNOOGIES \) 15.2 Random Column Read (Page within same Bank) (2 of 2) Burst ength = 4, atency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck3 RAw RAz Addr RAw CAw CAx CAy RAz CAz I/O i-z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Read Read Read Read Rev. 1.5 June

38 ProMOS TECNOOGIES \) 16.1 Random Column Write (Page within same Bank) (1 of 2) Burst ength = 4, atency =2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck2 RBz RAw RBz Addr RBz CBz CBx CBy RAw RBz CAx CBz I/O i-z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 DBz2 DBz3 Write Write Write Write Rev.1.5 June

39 ProMOS TECNOOGIES \) 16.2 Random Column Write (Page within same Bank) (2 of 2) Burst ength = 4, atency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck3 RBz RBz Addr RBz CBz CBx CBy RBz CBz I/O i-z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 DBz0 DBz1 Write Write Write Write Rev. 1.5 June

40 ProMOS TECNOOGIES 17.1 Random Row Read (Interleaving Banks) (1 of 2) Burst ength = 8, atency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck2 igh RBx RAx RBy Addr RBx CBx RAx CAx RBy CBy trcd tac2 trp i-z I/O Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 Read Read Read Rev.1.5 June

41 ProMOS TECNOOGIES Random Row Read (Interleaving Banks) (2 of 2) Burst ength = 8, atency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck3 igh RBx RAx RBy Addr RBx CBx RAx CAx RBy CBy trcd tac3 trp i-z I/O Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 Read Read Read Rev. 1.5 June

42 ProMOS TECNOOGIES 18.1 Random Row Write (Interleaving Banks) (1 of 2) Burst ength = 8, atency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck2 igh RAx RBx RAy Addr RAx CAy CA RBx CBx RAy CAy trcd tdp trp tdp I/O i-z DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 Write Write Write Rev.1.5 June

43 ProMOS TECNOOGIES 18.2 Random Row Write (Interleaving Banks) (2 of 2) Burst ength = 8, atency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK t CK3 igh RAx RBx RAy Addr RAx CA RBx CBx RAy CAy t RCD t DP t RP t DP I/O i-z DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Write Write Write Rev. 1.5 June

44 ProMOS TECNOOGIES 19.1 Termination of a Burst (1 of 2) Burst ength = 8, atency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck2 igh RAx RAy RAz Addr RAx CAx RAy CAy RAz CAz trp trp trp I/O i-z DAx0 DAx1 DAx2 DAx3 Ay0 Ay1 Ay2 Az0 Az1 Az2 Write Termination of a Write Burst. Write data is masked. Read Read Termination of a Read Burst. Rev.1.5 June

45 ProMOS TECNOOGIES 19.2 Termination of a Burst (2 of 2) Burst ength = 4, 8, atency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CK tck3 igh RAx RAy RAz Addr RAx CAx RAy CAy RAz trp trp I/O i-z DAx0 Ay0 Ay1 Ay2 Write Read Write Data is masked Termination of a Write Burst. Termination of a Read Burst. Rev. 1.5 June

46 ProMOS TECNOOGIES 20.1 Full Page Read Cycle (1 of 2) Burst ength = Full Page, atency = 2 CK tck2 igh RAx RBx RBy Addr RAx CAx RBx CBx RBy t RP I/O i-z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Bx+6 Read Read The burst counter wraps from the highest order page address back to zero during this time interval. Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Burst Stop Rev.1.5 June

47 ProMOS TECNOOGIES \ 20.2 Full Page Read Cycle (2 of 2) Burst ength = Full Page, atency = 3 CK tck3 igh RAx RBx RBy Addr RAx CAx RBx CBx RBy trrd I/O i-z Ax Ax+1 Ax+2 Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Read Read The burst counter wraps from the highest order page address back to zero during this time interval. Full Page burst operation does not terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Burst Stop Rev. 1.5 June

48 ProMOS TECNOOGIES 21.1Full Page Write Cycle (1 of 2) Burst ength = Full Page, atency = 2 CK tck2 igh RAx RBx RBy Addr RAx CAx RBx CBx RBy I/O i-z DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 Write The burst counter wraps from the highest order page address back to zero Write Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues Data is ignored. during this time interval. bursting beginning with the starting address. Burst Stop Rev.1.5 June

49 ProMOS TECNOOGIES 21.2 Full Page Write Cycle (2 of 2) Burst ength = Full Page, atency = 3 CK t CK3 igh RAx RBx RBy Addr RAx CAx RBx CBx RBy I/O i-z DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 Data is ignored. Write The burst counter wraps from the highest order page address back to zero during this time interval. Write Full Page burst operation does not terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Burst Stop Rev. 1.5 June

50 ProMOS TECNOOGIES Complete ist of Operation s SDRAM Function Truth Table CURRENT STATE 1 Addr ACTION Idle Op- RA Code NOP or Power Down NOP IEGA 2 IEGA 2 Row (&Bank) Active; atch Row Address NOP 4 Auto-Refresh or Self-Refresh 5 Mode reg. Access 5 Row Active CA, CA, NOP NOP Begin Read; atch CA; Determine Begin Write; atch CA; Determine IEGA 2 IEGA Read CA, CA, NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) Burst Stop > Row Active Term Burst, New Read, Determine 3 Term Burst, Start Write, Determine 3 IEGA 2 Term Burst, IEGA Write CA, CA, NOP (Continue Burst to End;>Row Active) NOP (Continue Burst to End;>Row Active) Burst Stop > Row Active Term Burst, Start Read, Determine 3 Term Burst, New Write, Determine 3 IEGA 2 Term Burst, 3 IEGA Read with Auto NOP (Continue Burst to End;> ) NOP (Continue Burst to End;> ) IEGA 2 IEGA 2 IEGA IEGA 2 IEGA 2 IEGA Rev.1.5 June

51 ProMOS TECNOOGIES SDRAM Function Truth Table (continued) CURRENT STATE 1 Addr ACTION Write with Auto NOP (Continue Burst to End;> ) NOP (Continue Burst to End;> ) IEGA 2 IEGA 2 IEGA IEGA 2 IEGA 2 IEGA Precharging NOP;> Idle after trp NOP;> Idle after trp IEGA 2 IEGA 2 IEGA 2 NOP 4 IEGA Row Activating NOP;> Row Active after trcd NOP;> Row Active after trcd IEGA 2 IEGA 2 IEGA 2 IEGA 2 IEGA Write Recovering NOP NOP IEGA 2 IEGA 2 IEGA 2 IEGA 2 IEGA Refreshing NOP;> Idle after trc NOP;> Idle after trc IEGA IEGA IEGA IEGA Mode Register Accessing NOP NOP IEGA IEGA IEGA Rev. 1.5 June

52 ProMOS TECNOOGIES Clock Enable () Truth Table: STATE(n) Self-Refresh 6 n-1 n Addr ACTION INVAID EIT Self-Refresh, Idle after trc EIT Self-Refresh, Idle after trc IEGA IEGA IEGA NOP (Maintain Self-Refresh) Power-Down INVAID EIT Power-Down, > Idle. EIT Power-Down, > Idle. IEGA IEGA IEGA NOP (Maintain ow-power Mode) All. Banks Idle 7 Refer to the function truth table Enter Power- Down Enter Power- Down IEGA IEGA IEGA Enter Self-Refresh IEGA NOP Abbreviations: RA = Row Address of CA = Column Address of = ddress RB = Row Address of CB = Column Address of = Auto RC = Row Address of Bank C CC = Column Address of Bank C RD = Row Address of Bank D CD = Column Address of Bank D Notes for SDRAM function truth table: 1. Current State is state of the bank determined by. All entries assume that was active (IG) during the preceding clock cycle. 2. Illegal to bank in specified state; Function may be legal in the bank indicated by, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in Idle state. May precharge bank(s) indicated by (and). 5. Illegal if any bank is not Idle. 6. ow to igh transition will re-enable CK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EIT. 7. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 8. Must be legal command as defined in the SDRAM function truth table. Rev.1.5 June

53 ProMOS TECNOOGIES Package Diagram 54 Ball FBGA Rev. 1.5 June

54 ProMOS TECNOOGIES Package Diagram 60 Ball FBGA 60 PINS SOC Rev.1.5 June

55 ProMOS TECNOOGIES Package Diagram 54 PINS TSOP II [1.20] MA 0.04 ±0.002 [1 ±0.05] ±0.005 [10.16 ±0.13] [0.80].008 [0.2] M 54x.004 [0.1] [0.15] MA ± [11.76 ± 0.20] ± [0.60 ±.020] Index Marking [ ] 1 Does not include plastic or metal protrusion of 0.15 max. per side Unit in inches [mm] Rev. 1.5 June

56 ProMOS TECNOOGIES WORDWIDE OFFICES SAES OFFICES: TAIWAN(sinchu) NO. 19 I SIN ROAD SCIEE BASED IND. PARK SIN CU, TAIWAN, R.O.C. PONE: FA: USA(West) 3910 NORT FIRST STREET SAN JOSE, CA PONE: FA: JAN ONZE 1852 BUIDING 6F SINTOMI, CUO-KU TOKYO PONE: FA: TAIWAN(Taipei) 7F, NO. 102 MIN-CUAN E. ROAD SEC. 3, Taipei, Taiwan, R.O.C PONE: FA: USA(East) 25 Creekside Road opewell Jct, NY PONE: FA: Copyright,ProMOS TECNOOGY. Printed in U.S.A. The information in this document is subject to change without notice. ProMOS TEC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of ProMOS TEC. ProMOS TEC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. ProMOS TEC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. Rev.1.5 June