CYV15G0404DXB Evaluation Board Users Guide

Transcription

1 Cypress Semiconductor Corporation 3901 North First Street San Jose, CA Revised October 4, 2004

2 TABLE OF CONTENTS 1.0 OVERVIEW KIT CONTENTS FEATURES OF THE CYV15G0404DXB FUNCTIONAL DESCRIPTION OF CYV15G0404DXB CYV15G0404DXB TRANSCEIVER LOGIC BLOCK DIAGRAM BOARD PHOTOGRAPH AND PIN DESCRIPTIONS ADJUSTING SETTINGS ON THE BOARD Speed Select Jumpers DIP Switches Asserting Values to Control Latches Reference Clock Input Options TEST MODES BIST Test Set-up Single Channel BIST Set-up Equipment Required Test Equipment Set-up Test Set-up External Loopback Mode Four Channel BIST Set-up with Global Enable Equipment Required Test Set-up Parallel Data Test Mode Equipment Required Parallel Data Test Set-up Encoder Enable Mode Encoder Bypass Mode Reclocker Test Mode Equipment Required Test Equipment Set-up Test Set-up...28 APPENDIX A: Schematic Diagram of APPENDIX B: PCB Layout for APPENDIX C: Bill Of Material (BOM) Page 2 of 56

3 LIST OF FIGURES Figure 4-1. CYV15G0404DXB Block Diagram... 6 Figure 4-2. Transmit Path Block Diagram... 7 Figure 4-3. Receive Path Block Diagram... 8 Figure 4-4. Device Configuration Control Block Diagram... 9 Figure 5-1. Photograph of Board with Numbering of Connectors Figure 5-2. Channel A Connectors Figure 5-3. Optical Interface Signals Figure 5-4. JTAG Interface Signals Figure 6-1. Speed Select Control with Jumpers Figure 6-2. Controlling Dip Switch Settings Figure 6-3. Write Enable and Reset Buttons Figure 6-4. Top View of REFCLK Connectors...18 Figure 7-1. BIST Mode Operation Figure 7-2. Pictorial Representation of the Internal BIST Set-up Figure 7-3. The Eye Diagram through the Signal Analyzer Figure 7-4. SMA Connectors for External Loopback Mode Figure 7-5. Loop Enable, Use Local Clock, and Input Select DIP Switches Figure 7-6. Optical Connector for External Loopback Mode Figure 7-7. Loop Enable, Use Local Clock, and Input Select DIP Switches Figure 7-8. Generated Clock, Data and Control Signals for Encoded Mode from DG Figure 7-9. Generated Clock and Data Signals for Encoder Bypass Mode from DG Figure Pictorial Representation of the Reclocker Test Equipment Set-up Page 3 of 56

4 LIST OF TABLES Table 5-1. Description of Connectors of the Table 5-2. Description of External Control Pins for Connectors J31 to J Table 5-3. Device Control Latch Description Table 5-4. Device Control Latch Configuration Table 6-1. Device Control Latch Configuration Example Table 7-1. Device Control Latch Configuration for BIST on Channel A Table 7-2. Device Control Latch Configuration Table for Global Configuration Table 7-3. Device Control Latch Configuration for Parallel Data Test Mode Table 7-4. Input Register Bit Assignments Table 7-5. Output Register Bit Assignments Table 7-6. Device Control Latch Configuration for Parallel Data Test Mode, Unencoded Table 7-7. Device Control Latch Configuration for Bist on Channel A Page 4 of 56

5 1.0 Overview The CYV15G0404DXB Quad Independent-Channel HOTLink II Transceiver is a point-to-point or point-to-multipoint communications building block that allows the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from MBaud per serial link. The independence of each channel provides the ability to simultaneously transport different types of data at different signaling rates across multiple channels. This user s guide describes the operation and interface of the CYV15G0404DXB evaluation board. The evaluation board allows users to become familiar with the functionality of the CYV15G0404DXB. 2.0 Kit Contents CYV15G0404DXB-EVAL (the evaluation board) Dear Customer letter A CD containing CYV15G0404DXB data sheet User s Guide CYV15G0404DXB application notes 0404EN.PDA and 0404BYP.PDA files for the DG2020 parallel data generator BSDL model 3.0 Features of the CYV15G0404DXB Quad channel transceiver for 195- to 1500-MBaud serial signaling rate Aggregate throughput of up to 12 Gbits/second Second-generation HOTLink technology Compliant with multiple standards ESCON, DVB-ASI, SMPTE 292M, SMPTE 259M, Fibre Channel and Gigabit Ethernet (GbE) (IEEE802.3z) 8B/10B coded data or 10 bit uncoded data Truly independent channels Each channel can perform reclocker function Each channel can operate at a different signaling rate Each channel can transport a different type of data Selectable input/output clocking options Internal phase-locked loops (PLLs) with no external PLL components Selectable differential PECL-compatible serial inputs per channel Internal DC-restoration Redundant differential PECL-compatible serial outputs per channel Source matched for 50Ω transmission lines No external bias resistors required Signaling-rate controlled edge-rates MultiFrame Receive Framer provides alignment options Bit and byte alignment Comma or Full K28.5 detect Single or Multi-byte Framer for byte alignment Low-latency option Synchronous LVTTL parallel interface JTAG boundary scan Built-In Self-Test (BIST) for at-speed link testing Page 5 of 56

6 Compatible with Fiber-optic modules Copper cables Circuit board traces Per-channel Link Quality Indicator Analog signal detect Digital signal detect Low-power 3.3V typical Single 3.3V supply 256-ball thermally enhanced BGA 0.25µ BiCMOS technology 4.0 Functional Description of CYV15G0404DXB Figure 4-1 shows the block diagram of CYV15G0404DXB, which has four pairs of transmit and receive channels (A,B,C,D). Each of the four modules represents a transceiver channel. The left side of the transceiver represents the transmitter, which is composed of a phase-align buffer, 8B/10B encoder and serializer. The right side of the transceiver is the receiver, which is composed of a deserializer, framer, 8B/10B decoder and elasticity buffer. CYV15G0404DXB Transceiver Logic Block Diagram TXDA[7:0] TXCTA[1:0] RXDA[7:0] RXSTA[2:0] TXDB[7:0] TXCTB[1:0] RXDB[7:0] RXSTB[2:0] TXDC[7:0] TXCTC[1:0] RXDC[7:0] RXSTC[2:0] TXDD[7:0] TXCTD[1:0] RXDD[7:0] RXSTD[2:0] x10 x11 x10 x11 x10 x11 x10 x11 Phase Align Buffer Elasticity Buffer Phase Align Buffer Elasticity Buffer Phase Align Buffer Elasticity Buffer Phase Align Buffer Elasticity Buffer Encoder 8B/10B Decoder 8B/10B Encoder 8B/10B Decoder 8B/10B Encoder 8B/10B Decoder 8B/10B Encoder 8B/10B Decoder 8B/10B Framer Framer Framer Framer Serializer Deserializer Serializer Deserializer Serializer Deserializer Serializer Deserializer TX RX TX RX TX RX TX RX OUTA1± OUTA2± INA1± INA2± OUTB1± OUTB2± INB1± INB2± OUTC1± OUTC2± INC1± INC2± OUTD1± OUTD2± IND1± IND2± REFCLKA± REFCLKB± REFCLKC± REFCLKD± Figure 4-1. CYV15G0404DXB Block Diagram Page 6 of 56

7 Figure 4-2 shows the transmitter section of CYV15G0404DXB in more detail. The building blocks of the channel include the phase-align buffer, the 8B/10B encoder and the serializer (shifter). When the reclocker function is enabled, the recovered serial data is reclocked and retransmitted through the serial outputs. Transmit Path Block Diagram REFCLKA+ REFCLKA- RCLKENA SPDSELA TXCLKOA TXERRA TXCLKA TXDA[7:0] TXCTA[1:0] TXCKSELA 8 2 RCLKA 0 1 Input Register 0 1 Phase-Align Buffer Transmit PLL Clock Multiplier A Character-Rate Clock A PABRSTA Encoder 8B/10B Encoder ENCBYPA BIST LFSR Bit-Rate Clock TXBISTA RCLK[A..D] are Internal Reclocker Character Clock Signals RED[A..D] are Internal Reclocker Serial Data Signals TXLB[A..D] are Internal Serial Loopback Signals OE[2..1]A TXRATEA Shifter REDA Register OE[2..1]A RCLKENA 1 0 = Internal Signal OUTA1+ OUTA1- OUTA2+ OUTA2- REFCLKB+ REFCLKB- RCLKENB SPDSELB TXCLKOB TXERRB TXCLKB TXDB[7:0] TXCTB[1:0] TXCKSELB 8 2 RCLKB 0 1 Input Register 0 1 Phase-Align Buffer Transmit PLL Clock Multiplier B Character-Rate Clock B PABRSTB Encoder 8B/10B Encoder ENCBYPB BIST LFSR Bit-Rate Clock TXBISTB OE[2..1]B TXRATEB Shifter REDB Register OE[2..1]B RCLKENB 1 0 TXLBA OUTB1+ OUTB1- OUTB2+ OUTB2- REFCLKC+ REFCLKC- RCLKENC SPDSELC TXCLKOC TXERRC TXCLKC TXDC[7:0] TXCTC[1:0] TXCKSELC 8 2 RCLKB 0 1 Input Register 0 1 Phase-Align Buffer Transmit PLL Clock Multiplier C Character-Rate Clock C PABRSTC Encoder 8B/10B Encoder ENCBYPC BIST LFSR Bit-Rate Clock TXBISTC OE[2..1]C TXRATEC Shifter REDC Register OE[2..1]C RCLKENC 1 0 TXLBB OUTC1+ OUTC1- OUTC2+ OUTC2- REFCLKD+ REFCLKD- RCLKEND SPDSELD TXCLKOD TXERRD TXCLKD TXDD[7:0] TXCTD[1:0] TXCKSELD 8 2 RCLKD 0 1 Input Register 0 1 Phase-Align Buffer Transmit PLL Clock Multiplier D Character-Rate Clock D PABRSTD Encoder 8B/10B Encoder ENCBYPD BIST LFSR Bit-Rate Clock TXBISTD OE[2..1]D TXRATED Shifter REDD Register OE[2..1]D RCLKEND 1 0 TXLBC OUTD1+ OUTD1- OUTD2+ OUTD2- TXLBD Figure 4-2. Transmit Path Block Diagram Page 7 of 56

8 Figure 4-3 shows the receive section of the CYV15G0404DXB. The serial data input passes through the clock and data recovery PLL, the deserializer, the framer, the 10B/8B decoder, and the elasticity buffer. When the reclocker function is enabled, the serial data (REDx) and recovered character clock (RCLKx) are passed to the transmitter, where the data is retransmitted. Receive Path Block Diagram RCLK[A..D] are Internal Reclocker Character Clock Signals RED[A..D] are Internal Reclocker Serial Data Signals TXLB[A..D] are Internal Serial Loopback Signals = Internal Signal RESET SPDSELA RXPLLPDA RCLKENA LPENA INSELA INA1+ INA1 INA2+ INA2 ULCA SPDSELB RXPLLPDB RCLKENB LPENB INSELB INB1+ INB1 INB2+ INB2 ULCB SPDSELC RXPLLPDC RCLKENC LPENC INSELC INC1+ INC1 INC2+ INC2 ULCC SPDSELD RCLKEND RXPLLPDD LPEND INSELD IND1+ IND1 IND2+ IND2 ULCD LDTDEN TXLBA TXLBB TXLBC TXLBD SDASEL[A..D][1:0] Receive Signal Monitor Clock & Data Recovery PLL Receive Signal Monitor Clock & Data Recovery PLL Receive Signal Monitor Clock & Data Recovery PLL Receive Signal Monitor Clock & Data Recovery PLL Shifter Shifter Shifter Shifter REDA RFMODE[A..D][1:0] RFEN[A..D] FRAMCHAR[A..D] DECMODE[A..D] RXBIST[A..D] RXCKSEL[A..D] DECBYP[A..D] RXRATE[A..D] RECLKA REDB RECLKB REDC RECLKC REDD RECLKD Framer Framer Framer Framer 10B/8B BIST 10B/8B BIST 10B/8B BIST 10B/8B BIST Clock Select Clock Select Clock Select Clock Select Elasticity Buffer Elasticity Buffer Elasticity Buffer Elasticity Buffer JTAG Boundary Scan Controller Output Register Output Register Output Register Output Register TRST TMS TCLK TDI TDO LFIA RXDA[7:0] RXSTA[2:0] RXCLKA+ RXCLKA LFIB RXDB[7:0] RXSTB[2:0] RXCLKB+ RXCLKB LFIC RXDC[7:0] RXSTC[2:0] RXCLKC+ RXCLKC LFID RXDD[7:0] RXSTD[2:0] RXCLKD+ RXCLKD Figure 4-3. Receive Path Block Diagram Page 8 of 56

9 Figure 4-4 shows the device configuration and control block diagram. The inputs are the external signals WREN, ADDR[3:0], and DATA[7:0] and will be described in subsequent sections. The outputs are the internal signals that are described in Table 5-4. Device Configuration and Control Block Diagram = Internal Signal WREN ADDR[3:0] DATA[7:0] Device Configuration and Control Interface RFMODE[A..D][1:0] RFEN[A..D] FRAMCHAR[A..D] DECMODE[A..D] RXBIST[A..D] RXCKSEL[A..D] DECBYP[A..D] RXRATE[A..D] SDASEL[A..D][1:0] RXPLLPD[A..D] TXRATE[A..D] TXCKSEL[A..D] PABRST[A..D] TXBIST[A..D] OE[A..D][2..1] ENCBYP[A..D] GLEN[11..0] FGLEN[2..0] Figure 4-4. Device Configuration Control Block Diagram Page 9 of 56

10 5.0 Board Photograph and Pin Descriptions Figure 5-1 shows the different connectors and pins of the CYV15G0404DXB evaluation board. Table 5-1 provides a description of each connector. Figure 5-1. Photograph of Board with Numbering of Connectors OPTICAL (XT1x) OPT (J25) 3.3V (J48) (DT6) 3.3V LED GND(J49) VCC LED (D6) (see Fig. 5) Channel B I/O (see Fig. 5) VCC(J50) LFIx(D1x, J19x) Channel A I/O B OUTB A INB (Y1B) OSC TXERR(J9B) (J18)LVTTL (J11,12)SMA REFCLKA OSC(Y1C) OUTA D INA (J18)LVTTL (J11,12)SMA REFCLKB OSC(Y1C) TXERR(J9D,A) (J9C) TXERR OUTD C IND (J18C)LVTTL (J11,12)SMA REFCLKC (Y1D) OSC Factory Test Settings LDTDEN(J38) (J18D)LVTTL (J11,12)SMA REFCLKD OUTC INC SERIN/OUT(J13-16)x WREN/RESET DATA(S4) RCLKEN(S7) LPEN(S2) Channel C I/O (see Fig. 5) (S6) (S5) JTAG(J44) ADDR(S1) ULC(S3) Channel D I/O (see Fig. 5) SPDSELx(see Fig. 9) INSEL(S3) Page 10 of 56

11 Figure 5-2 shows the parallel I/O and reference clock connectors for channel A. Channels B, C, and D have a similar layout of connectors. Note that TXERR is not located at the same position for the other channels. Refer to Figure 5-1 for their locations. J17A(RXCLKA+ SMA) Y1A(OSC) J11A(REFCLKA+ SMA) J18A(REFCLKA) J12A(REFCLKA- SMA) J10A(TXCKLOA SMA) J9A(TXERRA) J8A(RXCLKA+) J7A(RXCLKA-) J6A(RXSTA) J5A(RXDA) J4A(TXCLKOA) J3A(TXCLKA) J2A(TXCTA) J1A(TXDA) Figure 5-2. Channel A Connectors Table 5-1 gives a brief description of the connectors on the evaluation board. An x following a connector or signal name represents all four channels; e.g., Connector J1x for TXDx represents the connectors J1A, J1B, J1C, and J1D for the buses TXDA[7:0], TXDB[7:0], TXDC[7:0], and TXDD[7:0], respectively. For a more detailed description of the connectors and signals, refer to the data sheet. Table 5-1. Description of Connectors of the Connectors Signals Description J1x TXDx[7:0] LVTTL Input Transmit parallel data input for channel x J2x TXCTx[1:0] LVTTL Input Transmit control signals for channel x J3x TXCLKx LVTTL Input Transmit clock input for channel x J4x TXCLKOx LVTTL Output Buffered version of internal character rate clock J5x RXDx[7:0] LVTTL Output Receive parallel data output for channel x J6x RXSTx[2:0] LVTTL Output Receive parallel data status output for channel x J7x RXCLKx- LVTTL Output Complement of recovered clock at the receiver for channel x J8x RXCLKx+ LVTTL Output Recovered clock at the receiver for channel x J9x TXERRx LVTTL Output Transmit path error signal for channel x J10x TXCLKOx SMA Connector for TXCLKOx Buffered version of internal character rate clock J11x REFCLKx+ SMA Connector for REFCLKx + Positive input of reference clock for channel x Page 11 of 56

12 Table 5-1. Description of Connectors of the (continued) Connectors Signals Description J12x REFCLKx- SMA Connector for REFCLKx - Negative input of reference clock for channel x J13x, J14x SERINx1+, SERINx1- SMA Connectors for serial data input of channel x PECL compatible primary differential serial data inputs Routed through 50-Ohm impedance AC coupling capacitors present 100-Ohm differential load present J15x, J16x SEROUTx1-, SEROUTx1+ SMA Connectors for serial data output of channel x PECL-compatible primary differential serial data CML outputs Routed through 50-Ohm impedance AC coupling capacitors present Expects to see a 50-Ohm single ended or 100-Ohm differential termination in the receive ends J17x RXCLKx+ SMA Connector for RXCLKx Recovered clock at the receiver for channel x J18x REFCLKx+ Headers to probe the reference clock for channel x J19x LFIx Header to probe the Link Fault Indicator status for channel x J25 OPT LVTTL Output Headers to probe the signals for the optical modules Control Signals: OPT_RATE_SEL, OPT_TX_DISABLE Output Signals: OPT_TX_FAULT_x, OPT_LOS_x (x = A,B,C,D) J26 ADDR[3:0] Headers to control the configuration addressing bus or to probe the ADDR[3:0] dip switches J27 LPENx Header to control Loop Enable signal or probe the LPEN dip switch for channel x J28 INSELx Header to control the Receive Input Selector or probe the INSEL dip switch for channel x J29 ULCx Header to control the Use Local Clock signal or probe the ULC dip switch for channel x J30 DATA[7:0] Headers to control the configuration data bus or probe the DATA[7:0] dip switches J1 RCLKENx Header to control the Reclocker Enable signal or probe the RCLKEN dip switch for channel x XT1x Optical Modules Option for Small Form-Factor Pluggable (SFP) optical modules. The optical modules make use of the secondary input (INx2+) and secondary output (OUTx2+) in each transceiver channel. D1x LFIx, asynchronous Link Fault Indication output LEDs Signal active LOW. LED is lit when signal is active. Logical OR of six internal conditions: Received serial data frequency outside expected range Analog amplitude below expected levels Transition density lower than expected Receive channel disabled ULCx is LOW Absence of REFCLKx± Y1x REFCLK± 14-pin DIP socket for an external Crystal Oscillator to provide an independent reference clock for channel x. Page 12 of 56

13 Table 5-1. Description of Connectors of the (continued) Connectors Signals Description Power D6 Power Indicator Indicates if the power supply is ON. The LED glows when the power supply is ON. J48 3.3V Banana Jack Connector for power supply to the board +3.3 V DC DT6 Power Indicator Indicates if the power supply is ON. The LED glows when the power supply is ON. J50 V CC Banana Jack Connector for power supply to the chip +3.3 V DC J49 GND Banana Jack Ground Switches S1 ADDR[3:0] Configuration Addressing Bus Dip Switches S2 LPENx Loop Enable Dip Switch for channel x S3 ULCx INSELx Use Local Clock Dip Switch for channel x Receive Input Selector Dip Switch for channel x S4 DATA[7:0] Configuration Data Bus Dip Switches S5 WREN Control Write Enable Push-Button Switch (Active LOW) S6 RESET Asynchronous Device Reset (Active LOW) S7 RCLKENx Reclocker Enable for channel x JTAG JTAG Interface Standard JTAG Interface. CYV15G0404DXB does not have a dedicated JTAG reset. It has a built-in power-on-reset circuit for resetting the JTAG logic. Figure 5-3 shows the optical interface connector J25, along with the signal name for each pin. For a description of each signal, refer to the Small-form Factor Pluggable (SFP) Transceiver Multi-source agreement (MSA). Figure 5-4 shows the JTAG interface connector and the signal names for each pin. For a description of each signal, consult the CYV15G0404DXB data sheet. Figure 5-4 also shows the control pin header JTAG RESET (J41). It is described in Table 5-2. GND VCC OPT_LOS_D OPT_LOS_C OPT_LOS_B OPT_LOS_A OPT_TX_FAULT_D OPT_TX_FAULT_C OPT_TX_FAULT_B OPT_TX_FAULT_A No Connection OPT_TX_DISABLE OPT_RATE_SEL Figure 5-3. Optical Interface Signals GND TRST TDI TCK TMS JTAG RESET(J41) TDO VCC GND Figure 5-4. JTAG Interface Signals No Connection No Connection Table 5-2 provides a brief description of all the control pins from J31 to J41. The SPDSELX signals are 3-level inputs. This means that they operate at three voltage levels, termed as: HIGH (Direct connection to V CC ) MID (Open) LOW (Direct connection to V SS, i.e., GND). Page 13 of 56

14 Table 5-2. Description of External Control Pins for Connectors J31 to J41 Pin Name Characteristics SPDSELA (J34) SPDSELB (J33) SPDSELC (J32) SPDSELD (J31) LDTDEN (J38) Serial Rate Select 3-Level Select LOW = MBd MID = MBd HIGH = MBd Level Detect Transition Density Enable When HIGH, the Signal Level Detector, Range Controller, and Transition Density Detector are all enabled When LOW, only the Range Controller is enabled LTEN1 (J37) Factory Test 1 This input should be HIGH SCANEN2(J36) Factory Test 2 This input should be left open or LOW TMEN3(J35) Factory Test 3 This input should be left open or LOW WREN(J39) Control Write Enable Header When the jumper is connected across the middle and right pins (see Figure 6-3 on page 17), the push-button signal controls the WREN input to the chip When the jumper is connected across the middle and left pins, WREN is permanently ACTIVE (LOW) RESET(J40) Asynchronous Global Reset Header When HIGH, the push-button signal controls the RESET input to the chip When LOW, RESET is permanently ACTIVE (LOW) JTAG RESET(J41) Asynchronous JTAG Reset Header When closed, the global RESET signal will reset the JTAG interface When open, the global RESET signal has no effect on the JTAG interface Table 5-3 provides a brief description of the control latches for the configuration interface. For a detailed description, please refer to the datasheet. When a signal has multiple bits (e.g., RFMODEx[1:0] = 10), the right-most bit is the LSB (bit 0). Table 5-3. Device Control Latch Description Pin Name Characteristics RFMODEx[1:0] Reframe Mode Select When RFMODEx[1:0] = 00, low-latency framer is selected When RFMODEx[1:0] = 01, alternate mode Multi-byte framer is selected When RFMODEx[1:0] = 10, Cypress-mode Multi-byte framer is selected RFMODEx[1:0] = 11 is reserved for test FRAMCHARx Framing Character Select When 1, framer looks for either disparity of the K28.5 character When 0, framer looks for either disparity of the 8-bit Comma characters DECMODEx Receiver Decoder Mode Select When 1, the Cypress Decoding Mode is used When 0, the Alternate Decoding Mode is used DECBYPx Receiver Decoder Bypass When 1, the decoder is enabled When 0, the decoder is bypassed and raw 10-bit characters are passed through Page 14 of 56

15 Table 5-3. Device Control Latch Description (continued) Pin Name RXCKSELx RXRATEx SDASEL1x[1:0] SDASEL2x ENCBYPx TXCKSELx TXRATEx RFENx RXPLLPDx RXBISTx TXBISTx OE2x Characteristics Receive Clock Select When 1, the associated Output Registers are clocked by REFCLKx When 0, the associated Output Registers are clocked by the recovered byte clock Receive Clock Rate Select. When 1, RXCLK output for channel x is half the character rate When 0, RXCLK output for channel x is the full character rate When RXCKSELx = 1 and REFCLKx± is a half-rate clock, RXRATEx isn t interpreted and the RXCLKx± clock outputs follow the reference clock operating at half the character rate. Primary Serial Data Input Signal Detector Amplitude Select. When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled When SDASEL1x[1:0]= 01, the peak-peak differential voltage threshold level is 140 mv When SDASEL1x[1:0]= 10, the peak-peak differential voltage threshold level is 280 mv When SDASEL1x[1:0]= 11, the peak-peak differential voltage threshold level is 420 mv Secondary Serial Data Input Signal Detector Amplitude Select. When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled When SDASEL2x[1:0]= 01, the peak-peak differential voltage threshold level is 140 mv When SDASEL2x[1:0]= 10, the peak-peak differential voltage threshold level is 280 mv When SDASEL2x[1:0]= 11, the peak-peak differential voltage threshold level is 420 mv Transmit Encoder Bypass When 1, the encoder is enabled When 0, the encoder is bypassed and raw 10-bit characters are transmitted Transmit Clock Select When 1, the associated Input Registers are clocked by REFCLKx When 0, the associated Input Registers are clocked by the TXCLKx input Transmit PLL Clock Rate Select When 1, the transmit PLL multiplies REFCLKx by 20 to generate the bit-rate clock When 0, the transmit PLL multiplies REFCLKx by 10 to generate the bit-rate clock Reframe Enable When 1, the framer is enabled When 0, the framer is disabled Receive Channel Enable When 1, the PLL and analog circuitry are enabled When 0, the PLL and analog circuitry are disabled Receive BIST Disable When 1, the receiver BIST function is disabled When 0, the receiver BIST function is enabled Transmit BIST Disable When 1, the transmitter BIST function is disabled When 0, the transmitter BIST function is enabled Secondary Differential Serial Data Output Driver Enable When 1, the output driver is enabled allowing data to be transmitted When 0, the output driver is disabled Page 15 of 56

16 Table 5-3. Device Control Latch Description (continued) Pin Name OE1x PABRSTx GLEN[11..0] FGLEN[2..0] Primary Differential Serial Data Output Driver Enable When 1, the output driver is enabled allowing data to be transmitted When 0, the output driver is disabled Transmit Clock Phase Alignment Buffer Reset When a 0 is written, the phase of TXCLKx relative to REFCLKx is initialized This is a self clearing latch, eliminating the requirement of writing a 1 to complete the initialization of the Phase Alignment Buffer Global Enable When 1 for a given address, that address can participate in a global configuration When 0 for a given address, that address will not participate in a global configuration Force Global Enable When 1 for the associated global channel, FGLEN forces the global update of the target latch banks Table 5-4 shows the mapping of latches in the device. Each row of the table is defined by an address, ADDR[3:0]. The Chnl column lists the channel being configured for the particular address. The Type column lists whether the signals for the particular address are static or dynamic. A detailed description of the latch types is in the datasheet. The data signals DATA[7:0] will determine the value of the respective control latches upon assertion. The Reset Value of an address is the value in the latch bank of that address after a global reset. For example, at address 0 (0000b), the reset value is Thus, RFMODEA1 = 1, RFMODEA0 = 0, FRAMCHARA=1, DECMODEA = 1, DECBYPA = 1, RXCKSELA = 1, RXRATEA = 1, and GLEN0 = 1. Table 5-4. Device Control Latch Configuration ADDR Chnl Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0 (0000b) 1 (0001b) 2 (0010b) 3 (0011b) 4 (0100b) 5 (0101b) 6 (0110b) 7 (0111b) 8 (1000b) 9 (1001b) 10 (1010b) 11 (1011b) 12 (1100b) 13 (1101b) 14 (1110b) 15 (1111b) A S RFMODE A[1] A S SDASEL2 A[1] A D RFEN A B S RFMODE B[1] B S SDASEL2 B[1] B D RFEN B C S RFMODE C[1] C S SDASEL2 C[1] C D RFEN C D S RFMODE D[1] D S SDASEL2 D[1] D D RFEN D GLBL S RFMODE GL[1] GLBL S SDASEL2 GL[1] GLBL D RFEN GL All Mask RFMODE A[0] SDASEL2 A[0] RXPLLPD A RFMODE B[0] SDASEL2 B[0] RXPLLPD B RFMODE C[0] SDASEL2 C[0] RXPLLPD C RFMODE D[0] SDASEL2 D[0] RXPLLPD D RFMODE GL[0] SDASEL2 GL[0] RXPLLPD GL FRAMCHAR A SDASEL1 A[1] RXBIST A FRAMCHAR B SDASEL1 B[1] RXBIST B FRAMCHAR C SDASEL1 C[1] RXBIST C FRAMCHAR D SDASEL1 D[1] RXBIST D FRAMCHAR GL SDASEL1 GL[1] RXBIST GL DECMODE A SDASEL1 A[0] TXBIST A DECMODE B SDASEL1 B[0] TXBIST B DECMODE C SDASEL1 C[0] TXBIST C DECMODE D SDASEL1 D[0] TXBIST D DECMODE GL SDASEL1 GL[0] TXBIST GL Characteristics DECBYP A ENCBYP A OE2 A DECBYP B ENCBYP B OE2 B DECBYP C ENCBYP C OE2 C DECBYP D ENCBYP D OE2 D DECBYP GL ENCBYP GL OE2 GL RXCKSEL A TXCKSEL A OE1 A RXCKSEL B TXCKSEL B OE1 B RXCKSEL C TXCKSEL C OE1 C RXCKSEL D TXCKSEL D OE1 D RXCKSEL GL TXCKSEL GL OE1 GL RXRATE A TXRATE A PABRST A RXRATE B TXRATE B PABRST B RXRATE C TXRATE C PABRST C RXRATE D TXRATE D PABRST D RXRATE GL TXRATE GL PABRST GL Reset Value GLEN GLEN GLEN GLEN GLEN GLEN GLEN GLEN GLEN GLEN GLEN GLEN FGLEN0 FGLEN1 FGLEN2 D D7 D6 D5 D4 D3 D2 D1 D N/A N/A N/A Page 16 of 56

17 6.0 Adjusting Settings on the Board To successfully operate the device, the SPDSELx settings and configuration interface must be correctly configured. This section provides directions on how to configure the device. 6.1 Speed Select Jumpers To set the appropriate operating range for each channel s transmit and receive PLL, jumpers need to be placed on the correct SPDSELx headers for each channel. Shown in Figure 6-1 is a picture of the headers and the set-up of the jumpers. SPDSELD is set to low by connecting a jumper across the right and center pins. The white dot that is beside each pin of the right column represents the LOW level. SPDSELC is set to HIGH by connecting a jumper across the left and center pins. SPDSELB and SPDSELA are set to MID by having no jumpers connected. Dot = LOW Set to LOW Set to MID Set to HIGH Figure 6-1. Speed Select Control with Jumpers 6.2 DIP Switches The 2-level dip switches (DATA[7:0](S4), ADDR[3:0] (S1), RCLKEN[D..A] (S7), INSEL[D..A] (S3), ULC[D..A] (S3), and LPEN[D:A] (S2)) are set HIGH or LOW as illustrated in Figure 6-2. Once again, the side of the switch with a dot represents the LOW level side. Push this side to set HIGH Push this side to set LOW Dot = LOW Figure 6-2. Controlling Dip Switch Settings Use this number scheme Jumpers connected to enable WREN, RESET buttons Press to Reset the Device Press to latch in data values Figure 6-3. Write Enable and Reset Buttons Note. Disregard the numbering scheme that is inscribed directly on the DIP switches. Follow the numbering inscribed on the board, directly below each switch. See Figure Asserting Values to Control Latches 1. Using the ADDR (S1) DIP switches shown in Figure 6-2, select the target address. For example, if the target address ADDR[3:0] = 1010, press ADDR0 to the LOW side (see Figure 6-2), ADDR1 to the HIGH side, ADDR2 to the LOW side and ADDR3 to the HIGH side. 2. Using the DATA (S4) DIP switches shown in Figure 6-2, select the values of the latches for the appropriate address bank. Table 6-1 provides an example of a control latch configuration for address 10 (ADDR[3:0] = 1010), where DATA[7:0] = The colored background represents a logic-1 value and the white background represents a logic-0 value. 3. Once the data signals are set up, they can be latched into the respective control latches by pressing the WREN (S5) push button (see Figure 6-3). Page 17 of 56

18 Table 6-1. Device Control Latch Configuration Example ADDR Chnl Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reset Value 10 (1010b) D S SDASEL2 D[1] = 1 SDASEL2 D[0] = Reference Clock Input Options SDASEL1 D[1] = 1 SDASEL1 D[0] = 1 ENCBYP D = 1 TXCKSEL D = 0 TXRATE D = 1 GLEN10 = The reference clock signal, REFCLKx, can have three different types of input: Single-ended SMA, Differential SMA, and the Crystal Oscillator. Figure 6-4 shows the SMA connectors, Crystal Oscillator, and headers to probe REFCLKx. Crystal Oscillator The crystal oscillator is the default source for the REFCLKx signal. It provides a single-ended input. Each channel has an oscillator with a different frequency. The default frequencies for each channel are: channel A runs at MHz, channel B at MHz, channel C at 27.0 MHz, and channel D at 20.0 MHz. When attaching the oscillator, line up the sharp corner of the oscillator with the sharp corner of the white outline on the silkscreen (see Figure 6-4). Single-ended SMA To use the single-ended SMA option, connect an appropriate cable to either the REFCLKx+ or REFCLKx- SMA connector (see Figure 6-4). The crystal oscillator for that channel must also be disconnected from the 14-pin DIP socket. Differential SMA To use the differential SMA option, connect appropriate cables to both the REFCLKx+ and REFCLKx- SMA connectors (see Figure 6-4). The crystal oscillator for that channel must also be disconnected from the 14-pin DIP socket. Crystal Oscillator SMA Connector for REFCLKx+ input Ground Probe of REFCLKx+ Probe of REFCLKx- SMA Connector for REFCLKx- input Corner of oscillator Corner of silk screen outline Figure 6-4. Top View of REFCLK Connectors Page 18 of 56

19 7.0 Test Modes The different test modes discussed in this document are BIST, parallel data, and reclocker test modes, including independent clocking on multiple channels. BIST Mode CYV15G0404DXB has the Built-In Self-Test (BIST) capability. Each transmit and receive channel contains an independent BIST Pattern Generator and Checker. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit and receive section, and across the interconnecting links. Figure 7-1 shows the two BIST modes of operation: External loopback BIST mode and Internal loopback BIST mode. Ext. BIST OUTx± INx± TX RX TX BIST LFSR RX BIST LFSR Parallel Inputs Ignored Int. BIST Figure 7-1. BIST Mode Operation To switch between BIST modes, use the LPENx DIP switch. LPENx = HIGH for Internal and LPENx = LOW for External BIST mode for channel x. For external BIST mode, connect two SMA-to-SMA cables from SEROUTx1+ to SERINx1+ and from SEROUTx1- to SERINx1-. For internal BIST mode, no cables are required. An example of external BIST mode is described in Section on page 21. Two examples of BIST will be described in the sections. Single Channel BIST Four Channel BIST Parallel Data Test Mode The variations discussed in this document for this mode are Parallel-in parallel-out mode (Encoder Enabled) at two different frequencies Parallel-in parallel-out mode (Encoder Bypassed) Parallel-in serial-out mode (testing the transmit side). The detailed description of each test will comprise Equipment required (equipment, cable etc.) Test set-up Result verification Operational variations 7.1 BIST Test Set-up Single Channel BIST Set-up Equipment Required Equipment needed: CYV15G0404DXB evaluation board Instrument grade power supply 3-amp current 3.3V Oscilloscope (500 MHz or better). Optional Equipment: Digital signal analyzer (to observe eye diagrams) Pulse generator ( MHz) Page 19 of 56

20 Cables needed: SMA to SMA coaxial cables Power supply cables (banana plug cables) Test Equipment Set-up Figure 7-2 shows the test set-up for BIST on channel A. The signal analyzer in the diagram is optional. See Section 6.4 on page 18 for REFCLKx input options. The BIST tests will use the Crystal Oscillator option. To use the optional pulse generator instead of the supplied oscillators, connect an SMA-to-SMA cable using the single-ended SMA option (see Section 6.4 on page 18). If using the pulse generator, make sure the SPDSELx control is set correctly (see Section 6.1 on page 17). Signal Analyzer Ext Trigger Input 3.3V 3.0A Power Supply 3.3V GND 3.3V Pulse Generator TXCLKOA SEROUTA1 Output REFCLKA OSC Oscilloscope Input CYV15G0404DX Evaluation Board RXSTA[2:1] 3.3V GND Vcc Figure 7-2. Pictorial Representation of the Internal BIST Set-up Test Set-up The intention of this set-up is to test the CYV15G0404DXB in BIST mode. For this test, the device will transmit BIST data across Channel A and receive the same BIST data across the same channel by looping back the serial data within the device (referred to as Internal Loopback mode). Follow the procedure below for the test set-up. 1. Ensure that there are no SMA cables connected to the REFCLKA± inputs. Make sure the 125 MHz oscillator is connected to the14-pin DIP socket for Channel A. This test is using the Crystal Oscillator clock option (see Section 6.4 on page 18). 2. Adjust the power supply to 3.3V and 3A limit. Apply power to the board and chip by connecting 3.3V banana plugs to J48 and J50. Connect a banana plug from ground on the power supply to J Verify that the power supply LEDs (D6 and DT6) are on. 4. Set SPDSELA to HIGH (see Figure 6-1 on page 17). 5. Set LPENA(S2) to HIGH, ULCA(S3) to HIGH, and RCLKENA(S7) to LOW. The value of INSELx does not matter during internal loopback mode. 6. Make sure the jumpers for WREN (J39) and RESET(J40) are configured to enable the push buttons (see Figure 6-3 on page 17). 7. Press and release RESET to reset the board. 8. Verify that all LFIx LEDs are ON, indicating line faults on all channels. 9. Configure the control signals for channel A according to the configuration table below (refer to Section 6.3 on page 17). Page 20 of 56

21 Table 7-1. Device Control Latch Configuration for BIST on Channel A ADDR Chnl Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reset Value 0 (0000b) 1 (0001b) 2 (0010b) A S RFMODE A[1] = 1 A S SDASEL2 A[1] = 1 A D RFEN RFMODE A[0] = 0 SDASEL2 A[0] = 0 RXPLLPD FRAMCHAR SDASEL1 A[1] = 1 RXBIST A = 0 DECMODE SDASEL1 A[0] = 0 TXBIST A = 0 DECBYP ENCBYP OE2 RXCKSEL TXCKSEL OE1 RXRATE TXRATE A = 0 PABRST A = 0 GLEN0 = 1 GLEN1 = 1 GLEN2 = Steps 10 through 12 are for result verification of the BIST on channel A: 10.Verify that the LFIA LED turns off. 11.Connect a probe from the oscilloscope to RXSTA1 and verify that RXSTA1 signal has pulses of approximately 8.0-ns (1/125.0 MHz) width and 4.2-µs (8.0 ns/character * 527 characters/bist sequence) period. 12.Verify that RXSTA2 remains low to indicate that there are no BIST errors. Optional: Check the BIST serial out data as an eye diagram by following the procedure below. 13.Change LPENA (S2) to LOW. Notice that the LFIA LED will turn ON. 14.Connect a pair of serial outputs (SEROUTA1+/SEROUTA1-) to the digital signal analyzer using SMA cables. 15.Trigger the analyzer by connecting an SMA-to-SMA cable from TXCLKOA (J10) to the trigger input of the analyzer. 16.Verify on the analyzer that the eye diagram looks as shown in Figure 7-3. Make sure that the eye-width is 1-bit period. Figure 7-3. The Eye Diagram through the Signal Analyzer Note: This test can be repeated for other channels by changing the configuration of the associated bits for each channel External Loopback Mode Electrical Transmission For external loopback, connect SMA-to-SMA cables from SEROUTA1+ (J16A) to SERINA1+ (J13A) and from SEROUTA1- (J15A) to SERINA1- (J14A). See Figure 7-4. Also, the control signals for Loop Enable, Use Local Clock and Input Select need to be configured (see Figure 7-5). Set LPENA = LOW for external loopback mode, set ULCA = HIGH for clock and data recovery, and set RCLKENA = LOW to disable the reclocker function. Lastly, set INSELA = HIGH to select the SERINA1 SMA connectors. To run an external loopback BIST test, repeat the procedure in Section on page 20, but replace the values for LPENA, ULCA, RCLKENA, and INSELA in Step 5 with the values listed in this section. Page 21 of 56

22 Figure 7-4. SMA Connectors for External Loopback Mode Set RCLKENA = LOW (Reclocker Disabled) Set ULCA = HIGH (Clock & Data Recovery) Set INSELA = HIGH Set LPENA = LOW (SMA Connectors) (Ext. Loopback) Figure 7-5. Loop Enable, Use Local Clock, and Input Select DIP Switches Optical Transmission For external loopback with an optical signal, connect an optical module into the optical connector (XT1A). See Figure 7-6. Also, the control signals for Loop Enable, Use Local Clock and Input Select need to be configured (see Figure 7-7). Set LPENA = LOW for external loopback mode, set ULCA = HIGH for clock and data recovery, and set RCLKENA = LOW to disable the reclocker function. Lastly, set INSELA = LOW to select the optical connector. To run an external loopback BIST test, repeat the procedure in Section on page 20, but replace the values for LPENA, ULCA, RCLKENA, and INSELA in Step 5 with the values listed in this section. The locations of the optical control and error signals are shown in Figure 5-3 on page 13. Set RCLKENA = LOW (Reclocker Disabled) Set INSELA = LOW (Optical Connectors) Set ULCA = HIGH (Clock & Data Recovery) Set LPENA = LOW (Ext. Loopback) Figure 7-6. Optical Connector for External Loopback Mode Figure 7-7. Loop Enable, Use Local Clock, and Input Select DIP Switches Four Channel BIST Set-up with Global Enable Equipment Required Equipment needed is the same as mentioned in Section on page 19. This test will use the onboard clocks for each channel. To reconnect the clocks, see Figure 6-4 on page Test Set-up The purpose of this test is to display the device s ability to operate each channel at a different frequency or in a different mode. Also, this test will familiarize the user with the global configuration of the control latches. The Global Enable function can simultaneously configure multiple channels with the same settings. To show how to prevent a channel from participating in the global configuration, Channel A will have the Global Enable function (GLENx) disabled. Follow the procedure below. Page 22 of 56

23 1. Ensure that there are no SMA cables connected to the REFCLKx inputs. Make sure the oscillators are all connected to their respective 14-pin DIP sockets. This test is using the Crystal Oscillator clock option (see Section 6.4 on page 18). Make sure channel A is running at 125 MHz, channel B at MHz, channel C at 27 MHz, and channel D at 20 MHz. 2. Adjust Power Supply to 3.3V and 3A limit. Apply power to the board and device. 3. Verify that the power supply LEDs (D6 and DT6) are on. 4. Place jumpers on J31 J34 so that SPDSELA = HIGH, SPDSELB = HIGH, SPDSELC = LOW and SPDSELD = LOW (see Figure 6-1 on page 17). 5. Set LPENx (A,B,C,D) to HIGH, ULCx to HIGH, and RCLKENx to LOW. 6. Make sure the jumpers for WREN (J39) and RESET(J40) are configured to enable the push buttons (see Figure 6-3 on page 17). 7. Press and release the RESET button. 8. Verify that the LFIx LED s are all on. To prevent the Channel A latches from being affected by the global configuration, the Global Enable Control bits for Channel A (GLEN0, GLEN1, and GLEN2) need to be set to 0. All of these control bits are located at bit 0 of each address. To leave the other Channel A latches (bits 1 to 7) in their original states, they need to be masked out by following the next step. 9. Set ADDR[3:0] =1111 to select the mask latch bank. Set DATA[7:0] = to mask out bits 1 to 7. Press the WREN button. 10.To change GLEN0, set ADDR[3:0] = 0000 and DATA[7:0] = Press WREN. This will only change GLEN0 to Follow the same procedure as in step 10 to set both GLEN1 (ADDR[3:0] = 0001) and GLEN2 (ADDR[3:0] =0010) to Remove all the masks by setting ADDR[3:0] =1111 and DATA[7:0] = Press WREN. 13.To run the BIST on Channels B, C, and D, configure the control signals according to the configuration table below. Note: FGLEN0, FGLEN1, and FGLEN2 are all 0 so that Channel A is not altered. Colored background = 1, white = 0. Table 7-2. Device Control Latch Configuration Table for Global Configuration ADDR Chnl Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reset Value 12 (1100b) 13 (1101b) 14 (1110b) GLBL S RFMODE GL[1] = 1 GLBL S SDASEL2 GL[1] = 1 GLBL D RFEN GL = 1 RFMODE GL[0] = 0 SDASEL2 GL[0] = 0 RXPLLPD GL = 1 The following steps are for result verification of the four channel BIST: 14.Verify that the LED s for LFIB, LFIC, and LFID, are now off. The LFIA LED should still be on. 15.Check the RXSTx1 signal for all four channels. RXSTA1 should always be LOW because its BIST wasn t enabled. RXSTB1 should have pulses of approximately 9.4-ns width and 4.9-µs period. RXSTC1 should have pulses of approximately 37.0-ns width and 19.4-µs period and RXSTD1 should have pulses of approximately 50.0-ns width and 26.3-µs period. 16.Verify that RXSTB2, RXSTC2, and RXSTD2 remain low to indicate that there are no BIST errors. 17.To force all channels (including channel A) to run a BIST, run the same configuration as in step 13, but with FGLEN0, FGLEN1, and FGLEN2 set to Verify that the LFIA LED turns off. 19.Check that RXSTA1 has pulses of approximately 8-ns width and 4.2-µs period. 20.Verify that RXSTA2 remains low to indicate that there are no BIST errors. 7.2 Parallel Data Test Mode FRAMCHAR GL = 1 SDASEL1 GL[1] = 1 RXBIST GL = 0 DECMODE GL = 1 SDASEL1 GL[0] = 0 TXBIST GL = 0 DECBYP GL = 1 ENCBYP GL = 1 OE2 GL = 1 RXCKSEL GL = 1 TXCKSEL GL = 1 OE1 GL = 1 RXRATE GL = 0 TXRATE GL = 0 PABRST GL = Equipment Required Equipment needed: CYV15G0404DXB evaluation board Instrument-grade power supply 3 3.3V Parallel Data Generator: DG2020 from TekTronix (settings will be provided by Cypress) or equivalent Logic Analyzer: TDA700 series from TekTronix or equivalent. FGLEN0 = 0 FGLEN1 = 0 FGLEN2 = 0 N/A N/A N/A Page 23 of 56

24 Cables needed: Two SMA-to-SMA coaxial cables Power supply cables DG2020 cables with appropriate connectors Logic analyzer cables with appropriate connectors Parallel Data Test Set-up For this test, channels A, B, and C will accept parallel data from the DG2020, transmit and receive the data serially in internal loopback mode, and output the same parallel data to the Logic Analyzer. Channel D will accept parallel data from the DG2020 and will output the data serially to the Signal Analyzer. Channel A 100 MHz in encoder enable mode. Channel B 50 MHz in encoder enable mode. Channel C 100 MHz in encoder bypass mode. Channel D 100 MHz in encoder bypass mode. This test is separated into two sections (encoder enable mode and encoder bypass mode) because the DG2020 does not have enough wires to supply data for four channels. Follow the procedure below for the test set-up Encoder Enable Mode 1. Load the Cypress supplied file 0404EN.PDA in DG2020 data generator. If you are using a different data generator, use a waveform similar to the one shown in Figure 7-8. REFCLK (100 MHz.) TXDATA [7:0] FF FE FD FB F7 EF DF BF 7F FF 00 AA 55 AA 55 TXCT0 REFCLK50 Figure 7-8. Generated Clock, Data and Control Signals for Encoded Mode from DG2020 Note. The outputs of the DG2020 for this PDA file are mapped to POD-A bits If outputs need to be remapped for a particular test set-up, consult the DG2020 user s manual. 2. Connect two TXDATA lines of the DG2020 to J1A and J1B (TXDATA[7:0] to TXDA[7:0] and TXDB[7:0], respectively). 3. Connect two TXCT0 lines to TXCTx0 (x = A and B). Ground TXCTx1 on J2x by placing a shunt across the two pins of row 1 (TXCTx1). 4. Connect the REFCLK line of the DG2020 to REFCLKA+ (J12A) and connect REFCLK50 to REFCLKB+ (J12B). Make sure the oscillators (Y1A and Y1B) are disconnected. This test is using the single-ended SMA clock option for both channels (see Section 6.4 on page 18). 5. Connect the Logic Analyzer TDA700 to read the receive data lines on J5x (x= A and B) for RXDx[7:0] and on J6x for RXSTx[2:0]. 6. Connect two clock inputs of the logic analyzer to RXCLKx+ (x = A and B) on J17x. The clocking of the logic analyzer needs to be set to external. On the TDA700 series logic analyzer, go to the SET-UP window. After selecting external clocking, press Page 24 of 56

25 the MORE button to customize your clock's settings. Your clock definition needs to be changed to the RXCLKA clock to trigger on the faster clock. 7. Adjust the power supply to 3.3V and 3 Amps limit. 8. Apply power to the board and the device. 9. Verify that the power supply LEDs (D6 and DT6) are on. 10.Set SPDSELA = HIGH and SPDSELB = MID. Set ULCx = HIGH, LPENx = HIGH for internal loopback, and RCLKENx = LOW. 11.Start transmitting data from the data generator, making sure it is in REPEAT mode. 12.Make sure the jumpers for WREN (J39) and RESET(J40) are configured to enable the push buttons (see Figure 6-3 on page 17). 13.Press and release RESET to reset the board. 14.Configure the control latches as listed in Table 7-3 for addresses 0 (0000b) through 5 (0101b) for channels A and B. Table 7-3. Device Control Latch Configuration for Parallel Data Test Mode ADDR Chnl Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0 (0000b) 1 (0001b) 2 (0010b) 3 (0011b) 4 (0100b) 5 (0101b) A S RFMODE A[1] = 1 A S SDASEL2 A[1] = 1 A D RFEN B S RFMODE B[1] = 1 B S SDASEL2 B[1] = 1 B D RFEN B = 1 RFMODE A[0] = 0 SDASEL2 A[0] = 0 RXPLLPD RFMODE B[0] = 0 SDASEL2 B[0] = 0 RXPLLPD B = 1 FRAMCHAR SDASEL1 A[1] = 1 RXBIST FRAMCHAR B = 1 SDASEL1 B[1] = 1 RXBIST B = 1 DECMODE SDASEL1 A[0] = 0 TXBIST DECMODE B = 1 SDASEL1 B[0] = 0 TXBIST B = 1 DECBYP ENCBYP OE2 DECBYP B = 1 ENCBYP B = 1 OE2 B = 1 RXCKSEL TXCKSEL OE1 RXCKSEL B = 1 TXCKSEL B = 1 OE1 B = 1 RXRATE A = 0 TXRATE A = 0 PABRST A = 0 RXRATE B = 0 TXRATE B = 0 PABRST B = 0 GLEN0 = 1 GLEN1 = 1 GLEN2 = 1 GLEN3 = 1 GLEN4 = 1 GLEN5 = 1 Reset Value The following steps are done for result verification on channels A and B: 1. Run the logic analyzer. After it has acquired the data, it will pause and display the data received. 2. Compare the data on channel A with the transmitted data.the data should be the same as the transmitted data except for the period when TXCT0 is 1. During that period, the 00h input will produce a 05h output, which is the K28.5 framing sequence. RXSTA[2:0] should be 0 (000b) during data transmission. When the K28.5 framing sequence is being transmitted, RXSTA[2:0] should be 3 (011b) 3. Repeat the procedure for channel B. However, because REFCLKB is half the frequency rate, only every other data value will be clocked in. Therefore, the data output from the receiver will be either 05, 01, 04,10, 40,... or 05,00,02,08,20, 80,... (see Figure 7-8 on page 24) Encoder Bypass Mode For channels C and D, complete the following steps: 1. Load the Cypress supplied file 0404BYP.PDA in DG2020 data generator. If you are using your own data generator, use a waveform similar to the one shown in Figure 7-9. REFCLK (100 MHz.) TXDATA [9:0] 17C FF 3FE 3FD 3FB 3F7 3EF 3DF 3BF 37F 2FF 1FF 3FF 000 Figure 7-9. Generated Clock and Data Signals for Encoder Bypass Mode from DG2020 Page 25 of 56

26 Note. The output of the DG2020 for this PDA file are mapped to POD-A bits If outputs need to be remapped for a particular test set-up, consult the DG2020 user s manual. 2. Using the bit assignment scheme in Table 7-4, connect two TXDATA parallel cables from the DG2020 to J1C and J2C (TX- DATA[9:0] to TXDC[7:0] and TXCTC[1:0]). Connect two more TXDATA cables from the DG2020 to J1D and J2D using the same assignment scheme. Table 7-4. Input Register Bit Assignments Signal Name Unencoded TXDx0 (LSB) TXDATA0 TXDx1 TXDATA1 TXDx2 TXDATA2 TXDx3 TXDATA3 TXDx4 TXDATA4 TXDx5 TXDATA5 TXDx6 TXDATA6 TXDx7 TXDATA7 TXCTx0 TXDATA8 TXCTx1 (MSB) TXDATA9 3. Connect two REFCLK lines of the DG2020 to REFCLKC+ (J12C) and REFCLKD+ (J12D). Make sure the oscillators (Y1C and Y1D) are disconnected. This test is using the single-ended SMA clock option for both channels (see Section 6.4 on page 18) 4. Connect the Logic Analyzer TDA700 to read the receive data lines on J5C for RXDC[7:0] and on J6C for RXSTC[2:0]. Follow the bit assignment in Table 7-5 Table 7-5. Output Register Bit Assignments Signal Name RXSTC2 (LSB) RXSTC1 RXSTC0 RXDC0 RXDC1 RXDC2 RXDC3 RXDC4 RXDC5 RXDC6 RXDC7 (MSB) BYPASS ACTIVE (DECBYP = 0) COMDET DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 5. Connect a clock input of the logic analyzer to RXCLKC on J17C. The clocking of the logic analyzer needs to set to external. On the TDA700 series logic analyzer, go to the SET-UP window. After selecting external clocking, press the MORE button to customize your clock's settings. Your clock definition needs to be set to the RXCLKC input. 6. Connect a pair of serial outputs (SEROUTD1/SEROUTD1) to the digital signal analyzer using SMA cables. 7. Trigger the analyzer by connecting an SMA-to-SMA cable from TXCLKOD (J10D) to the trigger input of the analyzer. 8. Adjust the power supply to 3.3 volts and 3 amps limit and apply power to the board and the device. 9. Verify that the power supply LED s (D6 and DT6) are on. 10.Set SPDSELC = HIGH and SPDSELD = HIGH. Set ULCx = HIGH, LPENx = HIGH for internal loopback, and RCLKENx = LOW. 11.Start transmitting data from the data generator, making sure it is in REPEAT mode. 12.Make sure the jumpers for WREN (J39) and RESET(J40) are set HIGH to enable the push buttons (see Figure 6-3 on page 17). 13.Press and release RESET to reset the board. 14.Configure the control latches as listed in Table 7-6 for addresses 6 (0110b) through 11 (1011b) for channels C and D. Page 26 of 56