Research Results in Mixed Signal IC Design

Transcription

1 Research Results in Mixed Signal IC Design Jiren Yuan, Professor Department of Electroscience Lund University, Lund, Sweden J. Yuan, Dept. of Electroscience, Lund University 1

2 Work packages in project 3 WP3-1 Wide Dynamic Range A/D Converters WP3-2 Low-Glitch and RF D/A Converters WP3-3 High Speed Sampling and Digitizing Technique WP3-4 Design Techniques for Single Chip Mixed Signal Circuits and Systems WP3-5 Re-configurable Low-Power ADC for Flexible Radio Terminal New 2

3 A list of major results A floating-point ADC A charge sampler with embedded filter function An 8-bit 100-MHz low glitch interpolation DAC A direct digital RF-modulator using a 10-bit 100-MHz low glitch interpolation DAC A non-feedback multi-phase clock generator Besides, 6 more chips are in fabrication. 3

4 A list of designs sent for fabrication A 10+5 bit floating point ADC A direct digital RF quardrature modulator A 500MHz 8-bit CMOS sampler A 100 MS/s low power 2-step ADC using differential difference comparators An arbitrarily skewable multiphase clock generator with phase error average A 16-bit parallel adder using a new silent digital technique 4

5 Why a floating-point ADC IF AMP A/D Digital filter LNA ~20bit (thermal) π/2 LO IF AMP A/D FFT Digital filter Dominated by A/D quantization noise Decoder 5

6 A/D dynamic range For rapid fluctuation, AGC fails, effective resolution decreases Too expansive to cover the dynamic range with a full resolution 6

7 A floating-point ADC (FADC) Input Passive weighting 1 1/2 1/4 1/8 1/ S/H S/H S/H S/H S/H Compare & select 8-10 bit pipeline ADC 10-bit Mantissa 4-bit Exponent Such an FADC chip has been constructed and tested. 7

8 An FADC test chip 0.35 µm digital CMOS 12-bit dynamic range 8-bit resolution 30 MS/s 3.3V, 25mW A 10+5 bit 100MHz floating point ADC chip has been sent for fabrication. 8

9 Why study charge sampling? Track Hold R C Limitations: C min = 4kT 2 2(n+1) R max = 1/(ωC min 2 2(n+1) ) Difficulties in tracking input at both high speed and high resolution. 9

10 Problem in sub-sampling t < 0.62ps for 8-bit f=1ghz f s =49MHz f out =20MHz + Sampling rate is reduced - Demands on t remains the same! 10

11 Charge sampling S 1 I(t) Integrator C s S r i=m I(t) = Σ I i sin(ω i t+φ i ) i=0 t 2 I i (t)dt = QA i sin(ω i t s ) t 1 I(t) S r t 1 t s t 2 The signal is sampled at t s with a defined coefficient. S 1 t t Reset Sample Hold The value of C s can be large so it does not limit the speed. 11

12 Embedded filter function Kaiser window FIR ns db MHz Input Passive weighting.. V-to-I Converter Integration Sampled voltage 12

13 A sampling FIR filter chip 0.35 µm digital CMOS 62.5 MS/s sampling rate 3 MHz input bandwidth 60dB suppression at 15MHz 3.3V, 35mW 13

14 Why interpolation DAC (IDAC)? V Zero-order hold First-order hold H(f) SinX X SinX X ( ) 2 t f s /2 f s f Realized by Interpolation Image amplitude close to f s is greatly attenuated 14

15 A new interpolation method 3.3V (45mW) Clock delay line Output (270mV) Switch unit Clock B1 B2 B3 B4 B5 B6 B7 B8 15

16 An 8-bit 100MHz IDAC 0.35 µm digital CMOS 100MHz, 8-bit 16x linear interpolation SFDR = 63.4 db 3.3V, 45mW 0.67x0.67mm 2 16

17 Full scale output waveform 270 mv 17

18 Linearity DNL < LSB LSB INL < ± 0.15 LSB 18

19 Two-tone test result (8-bit) F S = 100MHz, F SIG1 = 2.37MHz F SIG2 = 3.79MHz SFD = db 19

20 A 10-bit 100MHz IDAC 0.35 µm digital CMOS 100MHz, 10-bit 16x linear interpolation SFDR = 58 db 3.3V, 80mW 0.49x0.49mm 2 This IDAC is used in a direct digital RF modulator on the same chip. 20

21 Direct digital amplitude modulation RF 01.Apr 02 23:37 Ref -21 dbm * Att 20 db * RBW 300 khz * VBW 1 khz SWT 1.85 s Delta 2 [T1] db MHz f 0 PA 1 AP CLRWR Marker 1 [T1] dbm MHz Delta 1 [T1] db MHz A Current (No filter) dB PRN 10-bit Interpolation DAC Digital input Center 800 MHz 22 MHz/ 800MHZ Span 220 MHz Date: 1.APR :37:43 21

22 Measured result at 1.2 GHz 01.Apr 02 23:16 Ref dbm -30 * Att 20 db 1 * RBW 100 khz * VBW 1 khz SWT 1 s Delta 1 [T1] db MHz Marker 1 [T1] dbm GHz A 1 AP CLRWR MHz dB PRN Center 1.2 GHz Date: 1.APR :16:44 5 MHz/ 1.2GHz Span 50 MHz 22

23 RF modulation stage R1 R2 V out M3 M4 M5 M6 RF+ RF- V bias M1 M2 V bias I+ Linear Interpolation I- Current Steering DAC 23

24 Direct digital quardrature modulation f 0 (I) 10-bit digital input (I) 10-bit digital input (Q) 10-bit Interpolation DAC 10-bit Interpolation DAC (No filter) Current Current (No filter) PA PA Combiner A and φ modulated RF f 0 (Q) This chip is in fabrication. 24

25 An arbitrarily skewable multi-clock generator

26 A multi-phase clock generator chip 0.35 µm digital CMOS Input clock GHz 8 evenly distributed clocks in one input clock period 3.3V supply voltage % phase error A new chip with phase average (higher accuracy) is under fabrication. 26

27 Silent CMOS circuit technique (WP3-4) φ 1 φ 2 φ 1 φ 2 Overlap pseudo 2-phase clock Differential logic - no missing current Current controlled pre-charge Free discharge - high speed Traditional CMOS Pre-charge Current Silent CMOS t A 16-bit parallel adder using this technique is in fabrication. 27

28 Re-configurable ADC for flexible radio (WP3-5) Re-configurable architecture Minimum power for a given task Adaptive control Resolution: Sampling rate: Power: Voltage: 6-12 bits 100MHz - 1MHz 200mW - 10mW V Input Clock Passive S/H Passive S/H Passive S/H clock and power management Low power ADC unit Low power ADC unit Low power ADC unit Common reference Digital background calibration Reconfigurable output register Output 28