On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping

Transcription

1 On Aea/Deph Tade-off in LUT-Baed FPGA Technolog Mapping Jaon Cong and Yheng Ding Depamen of Compe Science Uniei of Califonia, Lo Angele, CA 9002 Abac In hi pape e d he aea and deph ade-off in LUT baed FPGA echnolog mapping. Saing fom a deph-opimal mapping olion, e pefom a nmbe of deph elaaion opeaion o obain a ne neok ih bonded inceae in deph and adanageo o beqen e-mapping fo aea minimiaion. We hen e-map he eling neok o obain an aea-minimied mapping olion. B gadall inceaing he deph bond, fo each deign e ae able o podce a e of mapping olion ih mooh aea and deph ade-off. Fo he aea minimiaion ep, e hae deeloped an opimal algoihm fo comping an aea-minimm mapping olion iho node dplicaion. Epeimenal el ho ha o olion e opefom he olion podced b man eiing mapping algoihm in em of boh aea and deph minimiaion. 1. Inodcion The Field pogammable gae aa (FPGA) ha become a e popla echnolog in VLSI ASIC deign and em pooping. The lookp able (LUT) baed FPGA ae podced b eeal FPGA manface [16, 8], in hich he baic pogammable logic block i a K-inp lookp able ha can implemen an Boolean fncion of p o K aiable. The echnolog mapping poblem fo LUT-baed FPGA deign i o cone a geneal Boolean neok ino a fncionall eqialen K-LUT neok. Peio echnolog mapping algoihm fo LUT-baed FPGA deign can be oghl diided ino hee caegoie accoding o hei opimiaion objecie: he aea minimiaion algoihm [6, 10, 12, 9, 1, 13], he deph minimiaion algoihm [7, 11, 13, 2, 3], and he algoihm ha maimie oabili [1, 1]. Mo of hee mapping algoihm ae baed on heiic echniqe, ecep FloMap [3] hich gaanee o podce deph-opimal mapping olion. I emain open if he aea-opimal mapping poblem fo LUTbaed FPGA can be oled efficienl. The common limiaion of he eiing algoihm i ha fo a gien deign, each algoihm podce onl a ingle mapping olion opimied nde a fied objecie, hile ohe good mapping olion nde diffeen opimiaion objecie ae ignoed. Fige 1 compae he -LUT mapping el b ome eiing algoihm on an MCNC benchmak cici named o. The deph and he nmbe of LUT of he olion b diffeen algoihm a ignificanl. In geneal, he aea-minimied olion hae mch lage deph, hile he deph-minimied olion e mch moe LUT. Hoee, in pacice he be deign ma no come fom eihe one of hee o eeme. I i impoan o le he em deigne hae he fleibili o chooe fom a e of mapping olion ih mooh ade-off beeen aea and deph. In hi pape e d he ade-off beeen aea and deph in LUT-baed FPGA echnolog mapping. Specificall, e ae ineeed in obaining a e of mapping olion fo each deign, hich can mee aio aea and deph eqiemen. In pacice, he deigne all ha o podce he mo compac deign aifing ceain deph bond deemined b he pefomance pecificaion. To aif ch a need, o algoihm podce a e of aea-minimied mapping olion nde aio deph bond. The baic appoach of o algoihm i a follo. Saing fom a deph-opimal mapping olion (comped b he FloMap algoihm [3]), e pefom a nmbe of deph elaaion opeaion o obain a ne neok ih bonded inceae in deph o ha i i adanageo o beqen emapping fo aea minimiaion. We hen e-map he eling neok o obain an aea-minimied mapping olion ih bonded deph. B gadall inceaing he deph bond, fo each deign e ae able o podce a e of mapping olion ih mooh aea and deph ade-off. A he coe of he aea minimiaion ep, e hae deeloped a polnomial-ime algoihm fo comping an aea-opimal mapping olion iho node dplicaion fo a geneal Boolean neok, hich make a ignifican ep oad complee ndeanding of he geneal aea opimiaion poblem in FPGA echnolog mapping. De o page limiaion, deailed algoihm decipion and he poof of he heoem ae no inclded in hi pape. The can be fond in []. 2. Poblem Fomlaion A geneal Boolean neok i epeened a a DAG hee a node epeen a logic gae and a dieced edge <i, j > ei if he op of gae i i an inp of gae j. A pima inp (PI) node ha no incoming edge and a pima op (PO) node ha no ogoing edge. We e inp () o denoe he e of node hich ae he fanin of node, and op () o denoe he e of node hich ae he fano of node. Gien a bgaph H of he Boolean neok, inp (H) denoe he e of diinc node oide H hich ppl inp o he gae in H. The leel (o deph) of a node i he nmbe of edge on he longe pah fom an PI node o. The deph of a neok i he lage node leel in he Deph 12 MIS-pga [10] 11 Chole-cf [6] FloMap [3] DAG-Map [2] MIS-pga(dela) [11] Chole-d [7] # of -LUT Fige 1 Mapping olion of aio algoihm fo o (K=).

2 neok. A Boolean neok i K-bonded if inp () K fo each node. In he e of hi pape, e onl conide K-bonded neok. 1 Fo a node in he neok, a cone of, denoed C, i a bgaph of logic gae (eclding PI) coniing of and i pedeceo ch ha an pah connecing a node in C and lie eniel in C. We call he oo of C. A fano-fee cone (FFC) a, denoed FFC, i a cone of ch ha fo an node in FFC, op () FFC. A K-feaible cone of i a cone C ch ha inp (C ) K. If a K-LUT LUT implemen (coe) a K-feaible FFC of, e a ha LUT implemen node and ha i he oo of LUT. If he K-feaible cone C i no fano fee, e hae o dplicae he non-oo node in C ha hae fano oide of C in ode o coe C b a K-LUT. Gien a K- bonded neok, he echnolog mapping poblem fo K- LUT baed FPGA deign i o coe he neok ih K- feaible FFC (poibl ih node dplicaion). A echnolog mapping olion S i a DAG hee each node i a K- feaible FFC (eqialenl, a K-LUT) and he edge <C, C > ei if i in inp (C ). Fige 2 ho a Boolean neok and o mapping olion, one ih node dplicaion and he ohe iho node dplicaion. We a an LUT mapping olion aifie he deph bond D if he deph of he LUT neok i no moe han D. Gien a aified deph bond D, he lack on node i defined a follo: If i no a PI o PO, he lack of i D (L +P ), hee L i he leel of in he neok, and P i he lengh of he longe pah fom o an PO node. If i a PI o PO, he lack of i eo. A node i ciical if i ha eo lack. A pah fom a PI o a PO coniing of onl ciical node i a ciical pah. 3. Baic Opeaion and Oline of he Algoihm In hi ecion e dic he effec of deph elaaion and node dplicaion hich ae impoan in aea/deph ade-off, and gie an oeie of o algoihm. FloMap [3] podce deph-opimal LUT-baed FPGA mapping olion fo geneal Boolean neok. I oh noicing ha in a FloMap mapping olion, ee node (LUT) ha he minimm poible deph. Iniing minimm deph fo ee node, inclding he non-ciical one, ma lead o inefficien e of LUT. Fige 3(b) ho he mapping olion b FloMap fo he neok in Fige 3(a). Anohe olion i hon in Fige 3(d), hich ha he ame deph a (b) b e one fee LUT. Noe ha LUT in (b) ha he minimm deph 3. Hoee, ince i i no ciical, LUT doe no hae he minimm deph in (d). In fac, olion (d) can be obained fom (b) b decompoing LUT o (a) oiginal neok (b) mapping ih node dplicaed (6 LUT, 2 leel) (c) mapping iho node dplicaion ( LUT, 3 leel) Fige 2 Technolog mapping fo LUT-baed FPGA (K=3). 1 We e he DMIG algoihm [2] o anfom a neok hich i no K-bonded ino a K-bonded one ih minimm deph (a) oiginal neok 3 3 LUT 3* LUT (b) FloMap olion (c) afe deph elaaion (d) afe emapping Fige 3 Deph elaaion fo aea edcion (K=3, nmbe mean leel) eclde gae, a hon in (c), and hen pack LUT ino LUT. Since he decompoiion inceae he deph of he LUT, e call i a deph elaaion opeaion. When LUT i no ciical, hi opeaion doe no inceae he deph of he neok. Moe dicion abo deph elaaion ill be gien in ecion. Node dplicaion i pefomed hen e e an LUT o coe a K-feaible cone C hich ha a non-oo node ih a fano node oide of C (ee node in Fige 2(a)(b)). In geneal, node dplicaion i e impoan o deph opimiaion. Wiho node dplicaion, e ma hae o implemen man mli-fano node eplicil ih LUT, hich ma lead o lage deph in he mapping olion. In he FloMap mapping olion, node dplicaion i e ofen ed o gaanee he opimal deph. Hoee, node dplicaion ma no be e beneficial o aea minimiaion. If e make m dplicaion of a node, e need o coe hi node b m LUT, and i ma e ceain inp capaci of each of he m LUT. Theefoe, eceie node dplicaion ill e likel el in lage nmbe of LUT. Baed on hi obeaion, e hae deeloped he DF-map algoihm, hich pefom aea-opimal mapping iho node dplicaion. Deail ill be diced in ecion. O algoihm, named FloMap-, a ih he dephopimal mapping olion podced b FloMap. Fo each gien deph bond of he mapping olion, o algoihm coni of o phae. Ding he fi phae, e appl a nmbe of deph elaaion opeaion o podce an inemediae neok fo beqen aea minimiaion. Ding he econd phae, e ca o e-mapping fo aea minimiaion on he inemediae neok. Fi, e e he DF-Map pocede o compe an aea-opimal mapping olion iho node dplicaion. Then, e ca o o popoceing pocede hich allo necea node dplicaion fo fhe aea minimiaion. The o pocede ae MP-Pack, a maching-baed mli-fano pedeceo packing pocede fom he DAG-Map package [2], and Flo- Pack, a flo-baed aea minimiaion pocede fom he FloMap package [3]. To geneae a e of mapping olion, e gadall inceae he deph bond fo he mapping olion and epea he o-phae poce fo each deph bond. The algoihm op hen no impoemen on aea i aailable b fhe inceae of he deph bond. Cleal, he nmbe of ieaion i bonded b he deph of he oiginal neok.. Deph Relaaion Gien a non-ciical LUT LUT ooed a a node and ome node LUT, he deph elaaion opeaion decompoe LUT ino LUT and LUT, o ha LUT become a fanin of LUT. In he cae hee i a dplicaed node in LUT and LUT alead ei in he mapping olion, he

3 (a) (b) (c) Fige Thee pe of deph elaaion opeaion (ame K= and LUT ha non-eo lack). deph elaaion impl eplace LUT ih LUT and le LUT be a fanin of LUT, a in Fige 3(c). Oheie, LUT need o be ceaed eplicil. Nomall, e ill chooe and in ch a a ha afe he deph elaaion opeaion, LUT and/o LUT can be packed ih eiing LUT ding beqen e-mapping (a hon in Fige 3(d)). Since he deph elaaion opeaion ma lead o diffeen el hen applied on diffeen LUT, e an o appl hem o he mo pomiing LUT fi. Fige illae hee pe of deph elaaion, hich ae conideed in o algoihm. In Fige (a), LUT conain a dplicaion of node, and LUT i alead in he neok. If e appl deph elaaion opeaion on LUT o eclde, no ne LUT need o be ceaed. Moeoe, he inp ie of LUT ill be edced in mo cae, o ha i ma be packed ih ohe LUT. In hi eample, LUT can be packed eihe ih LUT o ih LUT. Fhemoe, he eliminaion of he dplicaion alo edce he fano ie of he fanin LUT of, hich ma eihe enable fhe packing of LUT ih he fanin LUT (in hi eample, LUT ), o he eliminaion of a edndan dplicaion of he fanin node (in hi eample, node ). In Fige (b), he o dplicaion of node ae in LUT and LUT. Since LUT need o be eplicil ceaed, hi cae i no a faoable a cae (a). Hoee, B appling deph elaaion on LUT, he inp ie of LUT i edced, heefoe fhe packing ma be poible. In hi eample, LUT can be packed ih LUT, o ih LUT and LUT. Moeoe, if e can lae appl deph elaaion on LUT o eclde i cop of node, no ne LUT need o be geneaed. In Fige (c), LUT conain node hich ha a ingle fano. Hoee, decompoing LUT o eclde ma lead o fhe packing o mege LUT ih LUT, and o mege LUT ih LUT. In hi cae he deph elaaion i alo applicable. In geneal, he poenial of aea edcion afe a deph elaaion opeaion aie. O algoihm chooe he opeaion hich ill el in he mo edcion. Afe he deph elaaion opeaion, he lack of elaed node ae ecomped, and he poce i epeaed nil no lack i aailable. Noe ha he e-mapping i no pefomed immediael afe a ingle deph elaaion opeaion. I i inoked afe all lack ae ehaed nde he cen deph bond o ha i can pefom global opimiaion fo aea minimiaion. I i ea o ee ha he oal co of he deph elaaion pocede fo each deph i no moe han O (n 2 ).. Aea Opimal Mapping iho Node Dplicaion In hi ecion e peen an algoihm fo aea-opimal mapping iho node dplicaion (dplicaion-fee mapping, o DF-mapping) fo geneal Boolean neok, hich i he coe of he e-mapping phae fo aea minimiaion. Noe ha DF-mapping i no eqialen o ee-baed mapping. Fige ho a imple eample hee DF-mapping e 2 LUT, hile ee-baed mapping e 6 LUT. O algoihm i baed on an impoan concep called he maimm fano fee cone. The maimm fano fee cone (MFFC) of, denoed MFFC, i an FFC of ch ha fo an non-pi node, if op () MFFC, hen MFFC. Fige 6 ho he MFFC of each node (he malle hadoed aea) in a neok. Cleal, MFFC i niqe fo ee node, and an FFC of i conained in MFFC. Moeoe, MFFC ha he folloing impoan popeie. Lemma 1 If MFFC, hen MFFC MFFC. Lemma 2 To MFFC ae eihe dijoin o one m conain he ohe. Lemma 3 If LUT i in a DF-mapping olion S, hen fo an, node MFFC implie LUT MFFC. Thee popeie of MFFC allo o ca o opimal DF-mapping efficienl. Fi, e poin o ha a geneal Boolean neok can be decompoed ino a e of dijoin MFFC ch ha he opimal DF-mapping fo he enie neok can be caied o in each MFFC independenl. Theoem 1 Le be a PO node of a geneal Boolean neok N. Then, an opimal DF-mapping olion S of N alo indce an opimal DF-mapping olion S of MFFC. Accoding o Theoem 1, e can paiion he neok N ino MFFC and N MFFC fo an PO node. An opimal DF-mapping olion coni of an opimal DF-mapping olion of MFFC and an opimal DF-mapping olion of N MFFC. B appling hi heoem eciel on N MFFC, e can paiion he enie neok N ino a e of dijoin MFFC o ha e can compe he opimal DFmapping fo each MFFC independenl o obain an opimal (a) oignal neok (b) dplicaion-fee mapping (c) ee-baed mapping Fige Dplicaion-fee mapping. ee-baed mapping (K=3).

4 p Fige 6 Maimm fano fee cone. DF-mapping olion of N. In Fige 6, he MFFC of node p, q,,, and fom a dijoin paiion of he neok. A c of MFFC i a paiion (X, X) of MFFC ch ha X i an FFC of. The ie of a c (X, X) i defined o be inp (X). A c i K-feaible if i ie i no moe han K. Cleal, a c (X, X) of MFFC i K-feaible if and onl if X can be coeed b a K-LUT ooed a. Fo each K-feaible c P = (X, X) of MFFC, e can coe X ih a K-LUT LUT P, and paiion X = MFFC X ino a e of dijoin MFFC MFFC 1 p, MFFC 2 p,..., MFFC p m. Then, e eciel compe he aea-opimal DF-mapping of each MFFC p i (1 i m). The co of he c P i defined o be co (P) = 1 + Σ m aea (MFFC i p), hee aea (MFFC i p) i i =1 he aea of he aea-opimal DF-mapping of MFFC i p. Cleal, co (P) gie he aea of he be DF-mapping olion of MFFC if X i coeed b LUT P. Theefoe, e geneae each K-feaible c of MFFC and chooe he c ih he lea co. Co compaion of each c inole eciel oling a e of DF-mapping fo MFFC of malle ie. Cleal, he ame dicion can be applied o dephopimal DF-mapping b impl aleing he co fncion. I i no difficl o ee ha hee ae onl polnomial nmbe of K-feaible c, ince he oal nmbe of poible combinaion of K o fee node i O (n K ), hee n i he nmbe of node in he MFFC. In pacice, hoee, eamining all hee combinaion o compe he K-feaible c ih he lea co i oo aefl, ince mo of hem do no fom a K-feaible c. We hall peen a moe efficien a o geneae he K-feaible c in MFFC. We fi conide he cae hee he MFFC i a ee. Ame ha MFFC i a ee T, ha f fanin node 1, 2,..., f (f K). Le T i denoe he bee in T ooed a i (1 i f). Cleal, an c of ie K in T indce a K i -c of T i, ih Σ i K i = K, and ice ea. Baed on hi fac, e can geneae all K-feaible c of a ee eciel. Noe ha in hi cae, he nmbe of c geneaed accoding o hi ecion i bonded b a conan ha depend onl on K and i independen of he ie of MFFC. Moe pecificall, e can poe Lemma If MFFC i a ee, he nmbe of c of ie K in MFFC 1 2K ( 2 K K 1 ). i no moe han he Kh Caalan nmbe, i.e. Fo K = he aboe bond i 1. If MFFC i no a ee, We fi conc a panning ee T ooed a, and hen ca o he ecion on he panning ee. Again, e ame ha node ha f fanin node q (a) (b) Fige 7 Complicaion in c geneaion. 1, 2,..., f (f K), and le T i denoe he bee in T ooed a i (1 i f). Hoee, a imple combinaion of he c in T 1, T 2,..., T f doe no ala gie a c of MFFC. In Fige 7, The MFFC in (a) ha a panning ee hon in (b) hee he dahed edge i no in he panning ee. If e epeen a c (X, X) b inp (X), hen, {,} i a c in he lef bee, and {,} i a c in he igh bee, b hei combinaion doe no fom a c in he MFFC, ince he edge <, > poide a pah connecing he node oide of he MFFC o he oo p. On he ohe hand, he c {,,,,} of he MFFC canno be geneaed fom he combinaion of he c in he o bee, ince {,,} i no a c of he lef bee. The poblem occ becae of he eience of he edge no in he panning ee (called non-ee edge). If a non-ee edge < i, j > coe o bee T i and T j of he panning ee T, e call i an ecape node of T i and j an enance node of T j. Fale c can be eail eliminaed b eamining he enance node. In ode o geneae he c ha ae no combinaion of he c of he bee, e genealie he concep of a c. A genealied c in a bee of he panning ee of an MFFC i a combinaion of a c ih ome ecape node. In Fige 7, {,,} i a genealied c of he lef bee. I can be hon (ee [] fo deail) ha he genealied c of ee T can be geneaed fom he combinaion of he genealied c of i bee T 1, T 2,..., T f, and he combinaion of he he oo ih he ecape node. Boh he e of genealied c and he e of ecape node can be comped eciel. Theefoe, e can compe all he genealied c of ie no moe han K efficienl, hich inclde all he K-feaible c in MFFC. C geneaion fo geneal neok i moe col han fo ee de o he eience of he ecape node. Hoee, o epeimenal el hoed ha in pacice, he ecion ofen qickl eache he poin hee he bee doe no conain an ecape node. In hi cae, he moe efficien ee c geneaion algoihm i applied. Fo K =, he nmbe of all poible K-node combinaion i O (n ), hile he oal nmbe of c eamined b o algoihm i beeen n 2 o n 3, hee n i he nmbe of node in one MFFC. We can fhe impoe he efficienc of he DF-mapping algoihm b collaping ee K-feaible MFFC ino i oo pio o he mapping, iho affecing he opimali of he beqen DF-mapping. Theoem 2 Thee ei an opimal DF-mapping olion in hich ee K-feaible MFFC i conained in a K-LUT. q p

5 In o epeimen, ch collaping edce he neok ie b 2% o 0% (hen K = ). O aea-opimal DF-mapping algoihm, he DF-Map, i mmaied a follo. We fi collape each K-feaible MFFC ino node. Then, e e he dnamic pogamming appoach o compe an opimal DF-mapping olion of MFFC fo each node accoding o he opological ode aing fom he PI node. Thi ode gaanee ha hen e compe he DF-mapping of MFFC, he opimal DFmapping olion of all he MFFC inide MFFC hae been comped, o ha e can ealae he co of each c in MFFC e eail. Finall, accoding o Theoem 1, e geneae he opimal DF-mapping olion fo he enie neok aing fom he PO node. Baed on he aboe dicion e hae Theoem 3 The DF-mapping poblem fo geneal Boolean neok in LUT-baed FPGA deign can be oled opimall in polnomial ime. In o FloMap- algoihm, nnecea node dplicaion b FloMap ae eliminaed in he deph elaaion ep. The beqen DF-mapping minimie aea iho inodcing ne node dplicaion. Afe appling he DF-Map algoihm, e ca o he o po-poceing pocede, he MP-Pack [2] and he Flo-Pack [3], hich eploe necea node dplicaion fo fhe aea edcion. Deph Deph o al de # of -LUT # of -LUT Fige 8 Aea/deph ade-off in FloMap- (K=). FloMap- Mapping Rel fo -LUT FPGA Opimal No. of -LUT Fo Diffeen Deph Cici Deph d op d op +0 d op +1 d op +2 d op +3 d op + p C C al al ape ape con de dke d o Table 1 Mapping olion of FloMap-. 6. Epeimenal Rel We hae implemened he FloMap- algoihm on SUN Spac okaion and eed i on he benchmak cici ed in [7, 2, 3]. Table 1 ho ome of he mapping olion e comped b FloMap-. In geneal, lage neok hae moe oom fo aea and deph ade-off, a hon in Fige 8. The aea edcion i all moe ignifican a he fi a fe ep of deph bond inceae. We alo compaed he aea- and deph-minimiaion olion geneaed b FloMap- ih hoe geneaed b ome eiing mapping algoihm. The daa fo hee algoihm ae qoed fom [7, 3, 11]. Table 2 compae he aeaminimm olion geneaed b FloMap- ih hoe geneaed b aea minimiaion mapping algoihm, inclding Chole-cf and MIS-pga. Oeall, he aea-minimm olion of FloMap- e % fee LUT and 1% fee leel han Chole-cf, and 2% fee LUT and 9% fee leel han MIS-pga (on aailable daa). Table 3 compae he deph-minimm olion geneaed b FloMap- ih hoe geneaed b deph minimiaion mapping algoihm, inclding FloMap, MIS-pga(dela), and Chole-d. Oeall, FloMap- ho bee pefomance han he compaed algoihm. 2 Moeoe, FloMap- i olel baed on combinaoial opimiaion echniqe, h i i fa. Fhemoe, FloMap- podce a e of mapping olion, each of hem aifie an eplicil aigned deph bond. Theefoe, i gie he deigne moe choice. The epeimen alo ho ha he edcion on he nmbe of LUT b he po-poceing ep ha pefom necea node dplicaion i % o 10%. Since he -LUT Mapping Rel Compaion: FloMap-. Aea Minimiaion Algoihm FloMap- Chole-cf Mi-pga Cici LUT Deph LUT Deph LUT Deph p m mml C C al al ape ape con de dke mie d o g ml oal Table 2 Compaion ih Chole-cf and MIS-pga. 2 The impoed eion of MIS-pga pogam, MIS-pga(ne) [12], opefom FloMap- in em of aea. The deph of hei olion ae no epoed in [12].

6 -LUT Mapping Rel Compaion: FloMap-. Deph Minimiaion Algoihm FloMap- FloMap Mi-pga(dela) Chole-d Cici LUT Dp LUT Dp LUT Dp LUT Dp p m mml C C al al ape ape con de dke mie d o g ml oal Table 3 Compaion ih FloMap, MIS-pga(dela), and Chole-d. pecenage of mli-fano node i mch lage, i fhe jifie he ampion ha an aea-opimal mapping olion hold no hae lage nmbe of node dplicaion. 7. Conclion and Fe Wok We hae peened a echnolog mapping algoihm fo LUT-baed FPGA deign ha i able o geneae a e of mapping olion ih mooh aea/deph ade-off. We hae deeloped an efficien mehod o compe an opimal dplicaion-fee mapping olion fo a geneal neok, and ed i fo aea minimiaion. The concep of he maimm fano fee cone pla an impoan ole in o dplicaionfee mapping algoihm, and i ma find applicaion o ohe logic nhei poblem a ell. The olion e geneaed b o algoihm opefom he olion b man eiing algoihm in em of aea and deph. Alhogh he algoihm i peened nde ni dela model, i can be genealied o he cae hee an abia dela i aigned o a ne [] Ḋing deph elaaion, e onl e cal infomaion o decompoe he LUT. I i alo poible o e Boolean opimiaion echniqe o e-nheie he LUT neok locall o eploe moe poibiliie, a he epene of longe compaion ime. The aea-opimal mapping poblem ih node dplicaion fo LUT-baed FPGA deign emain an open poblem. We ae cenl ding he poblem of aea-opimal mapping ih bonded node dplicaion. Acknoledgmen We hank D. K.C. Chen and D. Ban Pea fo hei helpfl dicion. Thi eeach i paiall ppoed b a gan fom Xilin Inc. nde he Sae of Califonia MICRO pogam No and a gan fom Fji Ameica, Inc.. Refeence [1] Bha, N. and D. Hill, Roable Technolog Mapping fo FPGA, Fi In l ACM/SIGDA Wokhop on Field Pogammable Gae Aa, pp , Feb [2] Chen, K. C., J. Cong, Y. Ding, A. B. Kahng, and P. Tajma, DAG-Map: Gaph-baed FPGA Technolog Mapping fo Dela Opimiaion, IEEE Deign and Te of Compe, Sep [3] Cong, J. and Y. Ding, An Opimal Technolog Mapping Algoihm fo Dela Opimiaion in Lookp- Table Baed FPGA Deign, IEEE In l Conf. on Compe Aided Deign, No [] Cong, J. and Y. Ding, On Aea/Deph Tade-off in LUT-Baed FPGA Technolog Mapping, UCLA Compe Science Depamen Tech. Repo CSD , Ocobe [] Cong, J., Y. Ding, T. Gao, and K. Chen, An Opimal Pefomance-Dien Technolog Mapping Algoihm fo LUT baed FPGA nde Abia Ne-Dela Model, Poc In l Conf. on Compe Gaphic and CAD, Ag [6] Fanci, R. J., J. Roe, and Z. Vaneic, Chole-cf: Fa Technolog Mapping fo Lookp Table-Baed FPGA, Poceeding 28h ACM/IEEE Deign Aomaion Confeence, pp , [7] Fanci, R. J., J. Roe, and Z. Vaneic, Technolog Mapping fo Dela Opimiaion of Lookp Table- Baed FPGA, MCNC Logic Snhei Wokhop, [8] Hill, D., A CAD Sem fo he Deign of Field Pogammable Gae Aa, Poc. ACM/IEEE Deign Aomaion Confeence, pp , [9] Kapl, K., Xmap: A Technolog Mappe fo Table-lookp Field-Pogammable Gae Aa, Poc. 28h ACM/IEEE Deign Aomaion Confeence, pp , [10] Mgai, R., e al, Logic Snhei Algoihm fo Pogammable Gae Aa, Poc. 27h ACM/IEEE Deign Aomaion Conf., pp , [11] Mgai, R., N. Sheno, R. K. Baon, and A. Sangioanni-Vincenelli, Pefomance Dieced Snhei fo Table Look Up Pogammable Gae Aa, Poc. In l Conf. Compe-Aided Deign, pp. 72-7, No., [12] Mgai, R., N. Sheno, R. K. Baon, and A. Sangioanni-Vincenelli, Impoed Logic Snhei Algoihm fo Table Look Up Achiece, Poc. In l Conf. Compe-Aided Deign, pp. 6-67, No., [13] Saka, P. and D. Thoma, Technolog Mapping fo Table-Look-Up Baed Field Pogammable Gae Aa, ACM/SIGDA Wokhop on Field Pogammable Gae Aa, pp , Feb [1] Schlag, M., J. Kong, and P. K. Chan, Roabili- Dien Technolog Mapping fo Lookp Table-Baed FPGA, Poc IEEE Inenaional Confeence on Compe Deign, Oc [1] Woo, N.-S., A Heiic Mehod fo FPGA Technolog Mapping Baed on he Edge Viibili, Poc. 28h ACM/IEEE Deign Aomaion Confeence, pp , [16] Xilin, The Pogammable Gae Aa Daa Book, Xilin, San Joe (1992).

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