A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements

Transcription

1 A Delay-efficien Radiaion-hard Digial Design Approach Using SP Elemens Charu Nagpal Rajesh Garg Sunil P Khari Deparmen of EE, Texas A&M Universiy, College Saion TX Absrac In his paper, we presen a radiaion-hardened digial design approach. This approach is based on he use of Code Word Sae Preserving (SP) elemens a each flip-flop of he design, and leaving he res of he design unalered. The SP elemen provides 100% SET proecion for glich widhs up o min{d min /2,(D max )/2}, where D min and D max are he minimum and maximum circui delay respecively and is an exra delay associaed wih our SET proecion circui. The SP circui has wo inpus - he lach oupu signal and he same signal delayed by a quaniy. In case an SET error is deeced, hen he curren compuaion is repeaed, using he correc oupu, which is generaed laer in he same clock period by he SP elemen. Unlike previous approaches, we use he SP elemen in a secondary pah and he SP logic is designed o minimally impac he criical delay pah of he design. The delay penaly of our approach (averaged over several designs) is less han 1%. Thus our echnique is applicable for high-speed designs, where he addiional delay associaed wih SET proecion mus be kep a a minimum. 1 Inroducion In recen imes, here has been an increased ineres in he radiaion immuniy of elecronic circuis [1, 2, 3, 4, 5, 6]. This has been an area of significan ineres and research for space or miliary elecronics [5, 4, 7] for many years, due o he significanly larger rae of radiaion srikes in such applicaions. For space applicaions, neurons, proons and heavy cosmic ions which are rapped in geomagneic bels produce inense showers of such radiaion. When such ions srike diffusion regions in VLSI designs, hey can deposi a charge, resuling in a volage spike on he affeced circui node. If he magniude of his spike is sufficienly large, an erroneous value may be compued by he circui. This is paricularly problemaic for memories, since he sored sae can flip as a resul of such a radiaion srike. Combinaional logic may also be affeced by such srikes, if he resuling glich occurs a he ime he circui oupus are being sampled. Such bi reversals are referred o as Single Even Transiens (SETs). Wih he relenless shrinking of he minimum feaure size of VLSI Inegraed Circuis (ICs), here is a corresponding reducion in he dimensions of diffusion nodes. This resuls in a reduced diffusion capaciance, and hence, if charge is dumped on he diffusion node as a consequence of a radiaion srike, a large volage spike may be generaed. Wih operaing volages geing smaller, his problem is furher aggravaed. As a resul, modern VLSI ICs are significanly more prone o SET problems. Even hough i is rue ha he amoun of radiaion received on he surface of he earh is lower han ha in space, he shrinking of process feaure sizes makes modern VLSI ICs more suscepible o SET problems han in he pas [6]. The charge deposiion rae is also referred o as he Linear Energy Transfer (LET). Cosmic ions have varying LETs, and hey resul in he deposiion of a charge in a semiconducor diffusion region of deph by he following formula [7]. = L Here L is he LET of he ion (expressed in MeV/cm 2 /mg), is he deph of he collecion volume (expressed in microns), and is charge in pc. The amoun of charge ha is required o cause a bi o be sampled incorrecly is referred o as he criical charge, C [8]. Wih diminishing process feaure sizes and supply volages, SET problems are a concern even for erresrial elecronics oday, paricularly for mission criical applicaions. Amospheric neurons as well as alpha paricles which are creaed by unsable isoopes in he IC packaging maerials can also cause SET problems. For reference, he LET of a 5 MeV alpha paricle is 1 MeV/cm 2 /mg [2]. Also, he probabiliy disribuion of energeic paricles drops off rapidly wih increasing LETs [9]. The larges populaion of paricles have an LET of 20 MeV/cm 2 /mg or less, and paricles wih an LET greaer han 30 MeV/cm 2 /mg are exceedingly rare [9, 10]. The curren pulse ha resuls from a paricle srike is radiionally expressed as a double exponenial funcion [11, 12]. The expression for his pulse is I() = (τ α τ β ) (e /τ α e /τ β ) (1) Here is he amoun of charge deposied as a resul of he ion srike, while τ α is he charge collecion ime consan for he juncion and τ β is he ion rack esablishmen consan. Based on he values used in [13], for he simulaions repored in his paper, we used τ β = 50ps and τ α = 200ps. Also, since he resuls in [13] are repored for = 100fC and 150fC (based on [14]), we compare our resuls wih hose of [13] for he same condiions. Addiionally, we provide resuls for oher values of as well. This paper uses he SP circui of [15] o achieve SET olerance. We refer o he normal circui compuaion pah as he funcional pah, while he alernaive pah used o deec and correc SET errors is called he secondary circui pah. The deecion of a fauly compuaion (due o an SET even) is done on he secondary pah by a wachdog circui, which used SP elemens. In case of an SET even, he correc value (which is compued by he SP elemen) is used o repea he compuaion, afer appropriaely inroducing a bubble in he compuaion pipeline. The main conribuions of his paper are: We achieve SET olerance for gliches of duraion up o min{d min /2,(D max )/2}, where D min, D max are he minimum and maximum delays of he design and is an addiional delay in he secondary circui pah. Since he SP elemens are conneced on a secondary as opposed o he funcional compuaion pah in he circui, here is a minimal (less han 1% on average) speed penaly. This is achieved since he secondary circui pah conaining he wachdog circui is conneced o he flip-flop inpus and oupus of he funcional circui in a manner ha addiional parasiic capaciances are minimized. Our resuls are beer han hose of [15], which has a delay overhead of 28.65%. Conrased wih an approach ha employs gae resizing [13], our average circui areas are comparable, while our delay penalies (0.54%) are much smaller han hose of [13] (which has a delay penaly of abou 2.8%). Our approach achieves 100% SET proecion, which is no he case for [13], which guaranees 90% circui proecion. The remainder of his paper is organized as follows: Secion 2 discusses some previous work in his area. In Secion 3 we describe our radiaion hardened design approach for digial elecronics. In Secion 4 we presen experimenal resuls, while conclusions and fuure work are discussed in Secion 5. 2 Previous Work There has been a grea deal of work on radiaion hardened circui design approaches. An excellen survey paper on his area is [16]. Several papers repor on experimenal sudies in he area of logic circuis [7, 8, 17, 18, 5], while ohers have focused on memory design [19, 8, 6, 20, 3, 4]. Since memories are paricularly suscepible o SET evens, hese effors were crucial o space and miliary applicaions. Ye oher approaches perform modeling and simulaion of radiaion evens [12, 9, 2]. In [1], he auhors address he sizing of ransisors in a digial design in order o improve he radiaion hardness of he design. In [6], he auhors provide a builin curren sensor (BICS) o deec SET evens in an SRAM. A radiaion hardened DRAM design was proposed in [20], while a FLASH memory based FPGA was inroduced in [5]. Oher radiaion hard design approaches ackle he problem of correcing errors a he sysem level, by using echniques such as riple modulo redundancy. A recen approach repored he use of Code Word Sae Preserving (SP) elemens [21, 15] o achieve SET proecion. This paper achieves he proecion achieved by TMR [16], while using only wo versions of any flip-flop/lach inpu signal (a regular version, and an appropriaely delayed copy). In his paper, he SP elemen was inroduced in he criical (funcional) circui pah. This approach incurs a 28.65% delay penaly and a 17.6% area penaly (averaged over several designs) for /DATE EDAA

2 oleraing a glich of widh up o 0.45ns. In conras o [15], our SP elemens are conneced in a secondary circui (i.e. no on he funcional circui pah, hereby resuling in a minimal speed penaly (of less han 1%). Also, we have designed our circuis o olerae SET gliches of widhs up o 0.5ns and 0.6ns corresponding o = 100fC and 150fC (based on [14]). However, he circui can easily be uned o olerae glich widhs of differen magniudes (up o min{d min /2,(D max )/2}). This is discussed in furher deail in Secion 4. Oher approaches [22, 13] ake he pah of gae resizing for SET proecion. Alhough his is orhogonal o our approach, we compare our resuls wih [13] as well. We find ha our average circui areas are comparable wih hose of [13], and our delay penalies are 0.54%, versus abou 2.8% for [13]. Also, our approach gives 100% SET proecion compared o 90% coverage provided by [13]. Anoher class of approaches [23] is based on performing muliple srobing of he oupu daa, wih differen delays beween he srobes. Wih an odd (n 3) number of srobes, his approach achieves TMR, alhough along he ime dimension. The muli-srobe TMR approach can olerae glich widhs up o D min /2. This is because he larges olerable glich widh is half he inerval beween he firs and las srobe. Since his inerval is consrained o be less han or equal o D min (he shores circui delay pah), a muli-srobe TMR approach achieves a maximum SET glich olerance of D min /2. However, for oleraing a glich of widh, his approach inroduces an exra delay of 2 plus he delay of he voing logic used o selec he correc oupu value from he muliple srobed values. Noe ha his delay is in he funcional circui pah. In conras o his echnique, our approach has a minimal delay overhead, since he compuaions which achieve SET hardening are done in a secondary pah. A horough comparison wih [23] is no possible since no experimenal resuls were provided in [23]. Oher orhogonal approaches include [24], where SET proecion is achieved by selecively shadowing he oupus of SET-suscepible gaes, and connecing he original and he shadow gae by a pair of diodes. Alhough his approach also achieves 100% SET proecion, i differs from ours in ha i does no explore he ime dimension in achieving SET proecion. 3 Our Approach Radiaion srikes cause charge o be dumped on a diffusion node, which resuls in volage gliches on hese nodes. We are concerned wih hose gliches ha cause nodes o change heir logical value (i.e. hose ha cross he swich-poin of he gae in quesion), and can be capured in a lach or flip-flop, hereby leading o incorrec circui operaion. Our approach uses SP elemens [15] o achieve 100% SET olerance. In case of a SET even, he correc value is always compued by he SP elemen (which is conneced in a secondary pah, off he funcional circui criical pahs). This correc value is used o repea he compuaion in case of a SET even, by inroducing a bubble in he compuaion. We achieve SET olerance for gliches of duraion up o min{d min /2,(D max )/2}, wihou he added design cos associaed wih alering he original design. The SP elemen is conneced o he flip-flop inpus and oupus, in a manner ha he addiional parasiic capaciances on he funcional circui pah are minimized. This secion is divided ino four subsecions. In Secion 3.1, we discuss, by way of inroducion, he design of he SP elemen, and explain how i is uilized in [21, 15]. Secion 3.2 explains our approach a he sysem level, while Secion 3.3 provides deails abou he circui level realizaion of our echnique. A discussion on iming analysis is presened in Secion SP Elemen We firs discuss he srucure of he Code Word Sae Preserving (SP) elemen, and how i is uilized in [21]. Figure 1 illusraes how SP elemens are uilized in a circui, using he approach of [21]. For he momen, le us assume ha he SP elemen oleraes SET gliches of widh up o, on any inernal circui node. p q gae G SP of gae G clk q a) Unproeced b) Proeced clk Figure 1: SP based SET Tolerance of [21] Consider he gae in he original design as shown in Figure 1 (a). In he SP-based SET-resilien design approach of [21], each gae whose p p q a a ou a) SP elemen for inverer a a a a b b b b ou b) SP elemen for NAND2 Figure 2: SP Elemens for NAND2 and INVERTER Gaes oupu is conneced o a flip-flop inpu is replaced by a corresponding SP elemen, as shown in Figure 1 (b). For a k inpu gae, he SP elemen has 2k inpus. One se of k inpus are conneced o he inpus of he gae ha he SP elemen replaces. The oher se of k inpus are conneced o he delayed version (by a delay value ) of he firs se of k inpus. This is illusraed in Figure 1. The resuling circui of Figure 1 (b) oleraes SET gliches of widh up o. We nex explain how a SP elemen oleraes gliches of widh up o. Figure 2 illusraes he SP circuis for an inverer and a NAND2 gae. In Figure 2, he inpus a and b are he un-delayed inpus, while he inpus a and b are delayed versions of a and b respecively (delayed by ime unis). Consider he SP elemen of eiher he INVERTER or he NAND2 gae. When he inpu a = a, and b = b, each SP elemen behaves normally, and he oupus are resisively driven o a and a b for he INVERTER and he NAND2 gae respecively. However, whenever here is an SET even which resuls in a glich on any inpu, he gae sops driving he oupu resisively, since boh he pullup and pulldown pahs are disabled. A his poin he oupu is held o is las correc value. The problem wih his approach is ha he SP elemen which replaces a k-inpu NAND or NOR gae requires 2k series devices, making he approach impracical for gaes wih more han 2 inpus. This is because in bulk CMOS echnologies, i is no pracical o connec more han 4-5 series devices in series, due o body effec [25]. [15] improved upon he approach of [21] o resolve his issue. As shown in Figure 3, [15] uses only one ype of SP elemen. In paricular, his is he SP elemen of an inverer. Combinaional Circui Combinaional Circui clk a) Unproeced b) Proeced SP of an Figure 3: Improved approach of [15] inverer In his approach, one of he inpus o he SP elemen comes direcly from he combinaional circui, while he oher inpu is he same oupu, delayed by. The combinaional circui is implemened o generae he complimen of he required oupu, and he SP elemen provides anoher inversion. Since his elemen has a mos 2 series devices, he delay and area overhead is kep a a minimum. This approach also avers he need o have a unique SP elemen for each library gae in he circui, reducing he design ime and cos. However, in boh [15, 21], he delay of he circui is increased significanly as SP elemens are added before every flip-flop in he design. In paricular, if an SET even resuls in a glich of widh a he un-delayed inpu o he SP elemen, i will aain is correc value afer ime. The delayed inpu aains is correc value afer anoher delay. Thus, he oupu of he SP elemen is guaraneed o be correc afer a delay of 2. This causes delay penaly of 2 in he funcional circui delay. Addiionally, he delay of he SP elemen (D SP ) is more han he delay of he gae i replaced (D g ), resuling in a furher increase in he delay penaly. The delay overhead is herefore given by: Delay = 2+D SP D g In our approach, delay is only minimally increased since he compuaion of he correc value using he SP elemens is done on a secondary pah, unlike [15]. The work of [15] does no ake ino accoun a possible SET srike a he oupu of he SP elemen. In our approach, we have upsized he clk

3 SP elemen o ensure ha i does no resul in a SET glich, for a srike wih colleced charge up o some value. The maximum value of used was 150fC. Noe ha his upsizing of he SP devices also helps ensure ha he capaciances a is nodes are high enough ha he SP elemen is able o hold is las correc sae when here is an SET even resuling in a glich on one of is inpus. 3.2 Sysem Level Design Figure 4 illusraes our approach schemaically. Consider a fragmen of he original design, shown in Figure 4 (a). This consiss of a combinaional oupu which is conneced o a flip-flop labeled DFF sysem. This flip-flop is in he funcional circui pah of he design. Our SP based modificaion o his circui is shown in Figure 4 (b). The original combinaional logic is lef inac, excep ha he flip-flop is redesigned and renamed DFF modi f ied (his design is discussed laer). In addiion, he values of he D and signals of he flip-flop are read by he SET proecion logic shown in Figure 4 (b). This logic is on a secondary pah, and hence he funcional delay is impaced only minimally. The D inpu of DFF modi f ied is conneced o a minimum-sized inverer, whose oupu is fed direcly o a SP elemen. The oher inpu of he SP elemen is he delayed version of he inverer oupu (delayed by ). The oupu of he SP elemen (called ) is compared wih he oupu of he sysem flip-flop using a rising-edge riggered equivalence checking circui, wih an oupu E. As explained in Secion 3.1, he oupu of he SP elemen is guaraneed o be correc afer a delay equal o he sum of 2 and he delay of he SP elemen. Thus, he equivalence check is riggered afer he rising edge of, delayed by he sum of 2 and he delay of he SP elemen. This delayed clock signal is referred o as DEL. Under normal operaion, we noe ha E is high, since is equal o. When here is an SET even, hese values can be differen causing E o fall. In his case, he curren compuaion is redone using he oupu of he SP elemen (which is guaraneed o be correc) as he inpu o DFF modi f ied in he nex clock cycle. Noe ha if an SET even is deeced a any flip-flop in a design, he compuaion needs o be redone for all he flip-flops in he design. Consider ha a design has n flip-flops. Suppose E1 hrough En are he oupus of he Equivalence Checkers corresponding o each of hese flipflops. If any of hese E signals becomes low, he compuaion needs o be redone for all he flip-flops. A logical AND of all he E signals is herefore compued o obain a global E signal (called ). If he signal falls, he value of is lached ino a flip-flop (DFF2), whose oupu is. This value is guaraneed o be error-free 1, and is now used in he nex cycle as he inpu o DFF modi f ied, so ha he curren compuaion is redone in he nex cycle. We nex explain he purpose of he flip-flop used o lach he value of o produce he signal F. Say here is an SET even in he clock cycle i which causes he oupu i of he DFF modi f ied o be differen from he inpu D i. This will cause E, and hereby o fall. In he nex (i + 1) h clock cycle, (which is equal o D i ) will be lached o he sysem flip-flop DFF modi f ied. However, is compued using D i+1, which can be differen from D i. In he absence of he flip-flop which generaed F, E and will remain low in he cycle i+1, again riggering a recompuaion in he nex cycle. This recompuaion could go on indefiniely. The likelihood of wo srikes on our SET oleran design in wo consecuive clock cycles is exremely low 2. Hence, if here was an SET even in clock cycle i which resuled in E o be low, we can safely assume ha here will be no SET even in clock cycle i+1. As a resul, he E and signals can be ignored in he (i+ 1) h cycle. This can be done by making E and high in he nex clock cycle. To achieve his, he value of is lached o F a he posiive edge of. Following an SET error in cycle i, a low value on leads o being used as he inpu o DFF modi f ied for cycle i+1. In he Equivalence Checker (Figure 5), in cycle i+1, F being low will make E high and no recompuaion will be riggered in cycle i + 2. A he archiecural level, he decision o reapply he primary inpus and rigger a recompuaion is done if he value of is low a he rising edge of. This ensures proper handling of gliches as explained below. As long as he SP elemen is sized appropriaely o susain an SET even which resuls in a glich of size (he derivaion of will be described in Secion 3.4), he circui is able o correc 100% of he SET evens. To validae his claim, we consider several cases lised below. We have simulaed each of he scenarios below o confirm ha our approach indeed provides 100% SET olerance. Noe ha i is reasonable o assume ha here will no be more han one SET even occurring simulaneously. 1 if here is an error on, his error is silenly ignored by he circui 2 As per [26, 27], he maximum solar proon fluence for paricles of energy > 1MeV based on he JPL model is 2.91X10 11 /cm 2 /year wih 99% confidence. The maximum area and ime period for he escases run was seen o be 473.4X10 8 cm 2 and 5.5ns respecively. Using hese values, we can show ha he maximum number of paricle srikes in he escases run in wo consecuive cycles is 4.78X Thus, all he nodes in our proecion scheme are analyzed independen of he ohers. Suppose here is an SET even in he SP circui, or on is inpus. In his case, he SP elemen proecs agains his glich, as discussed. If here is an SET even in he ransiive fan-in of P or P, hen his would have caused he values of P and P o be differen in he wors case, causing he SP elemen o proec agains he glich. If he glich is caused on, hen he se of flip-flops ha are sequenially adjacen o DFF modi f ied are responsible for proecing agains i. Since all flip-flops are implemened wih SP elemens, his causes no erroneous compuaions. Furher, if a glich on causes E o be driven low, hen he curren compuaion is redone (albei needlessly). However, no incorrec compuaion is performed. If an SET even in he Equivalence Checker circui or he AND gae AND1 causes E and hereby o become low, here are wo scenarios o be considered. If he glich is presen a he posiive edge of, i will lead o a recompuaion. Since only one SET glich can occur a a ime, he value of will be correc, so he correc compuaion is redone (albei needlessly). A glich on a any oher ime is neiher lached o F nor i is used o deermine he inpu o DFF modi f ied for he nex clock cycle. I is herefore silenly ignored. Also, since he decision o rigger a bubble in he pipeline a he archiecural level is made if is low a he posiive edge of, no recompuaion will be riggered. If here is an SET even in DFF1, i may lead o F being low. This will ensure ha E becomes high in he nex clock cycle, which is benign considering ha he probabiliy of wo srikes in wo consecuive clock cycles is exremely low, as discussed earlier. If here is an SET even in DFF2, i migh resul in a glich a. However, in ha case, E would be high, and inpu D of he sysem flip-flop would be used for he compuaion. Thus, he glich a is inconsequenial. If here is an SET even a he oupu of he SP elemen, proecion is achieved by appropriae upsizing of he ransisors in he SP elemen. The key feaures of our echnique is ha i achieves 100% SET olerance, unlike [22, 13]. The SET correcion circuiry is conneced on a secondary pah (no on he funcional pah), and hence he delay penaly is exremely small (much smaller han [22, 13, 15]). The sysem model requires recompuaions in case of an SET even. A horough simulaion and analysis of a single SP elemen assures SET olerance for he enire design. The echnique can olerae SET gliches up o a widh min{d min /2,(D max )/2}, where is a fixed delay associaed wih he SET proecion circuiry. The expression for is derived in Secion Circui Level Design Figure 5 describes our echnique a he gae level. The circui blocks(dff modified, Equivalence Checker and F Circui) from Figure 4 are marked wih a doed ouline in his figure. The SP elemen and is delay circuiry is no shown in Figure 5. The Equivalence Checker block consiss of a XNOR, followed by a MUX wih F as he selec signal. The purpose of his MUX was explained in Secion 3.2. The oupu of he MUX is fed o a flipflop, which is clocked by he rising edge of DEL ( delayed by 2+D SP ). A logical AND of he E oupus of all he flip-flops in he design is used o generae he signal. Insead of using an AND gae, i is more area efficien o achieve he same funcionaliy by performing a NOR of he invered E signals. I was experimenally seen ha he delay of he NOR gae wih up o 30 inpus is reasonable (abou 80ps). For designs wih more han 30 flip-flops (E signals), a mulilevel AND srucure was used. Our experimens accoun for his. The Maser lach of DFF modi f ied is modified so ha when is high, he Maser lach inpu is conneced o D. When is low (in case of an equivalence check mismach in one of he flip-flops), hen he Maser lach inpu is conneced o (he guaraneed error-free value). Devices in he SET proecion circuiry are minimum-sized, o minimize he area overhead required o achieve SET proecion. PMOS gae widhs are made he same as NMOS gae widhs, for he same reason. We simulaed he enire circui in SPICE, o verify for correc operaion.

4 DFF modified LOGIC D LOGIC DFF sysem D P SP P Equivalence Checker DEL E E AND1 DFF1 SEU proecion logic a) Original Circui b) Modified Circui DFF2 c) F Circui Figure 4: Archiecural view of our SET Toleran Design DFF modified D Equivalence Checker E 0 F Circui DFF1 DEL DFF2 There was a 66mV reducion in he noise margin of an inverer in he proecion logic due o our modified sizing approach. However, since his skewed sizing is only used in he secondary pah, and all he nodes in he proecion circuiry are SET immune based on he discussion of Secion 3.2, his is no a problem. The funcional pah is no impaced by his skewed sizing. I is imporan o noe ha in our approach, he Maser lach of he sysem flip-flop needs o muliplex is inpu from he combinaional logic (if here was no SET error) or from he signal in case here was a SET error. Insead of placing a MUX a is inpu, we fold he MUX ino he Maser lach iself. This resuls in a minimal delay penaly. The modified Maser laches used in he RAZOR approach [28, 29, 30] add a MUX in he criical delay pah insead. 3.4 Timing Analysis The maximum widh of a SET glich ha can be proeced by our SET proecion scheme is deermined as he minimum of wo quaniies (D min /2 and 1/2(D max )). This secion provides he iming analysis o derive hese wo condiions. The firs quaniy which deermines he maximum olerable SET glich is D min /2. In Figure 4b), consider an SET glich of widh a he D inpu of he sysem flip-flop (DFF modified). Le us assume ha he glich begins jus before he rising edge of. In an unproeced circui, his could have led o incorrec sysem evaluaion. The inpu P o he SP elemen is a is correc value afer ime. The second inpu o he SP elemen aains is correc value afer an addiional delay of. Thus, he oupu of he SP elemen is guaraneed o be correc only afer a delay of 2. Thus, he minimum delay D min of he circui mus be greaer han 2. Therefore, he maximum widh of a SET induced glich ha can be proeced by our approach is less han or equal o D min /2. The value of used for he delay elemen is in fac slighly larger han he maximum glich widh ha we inend o proec he circui from. Figure 5: Gae Level View of our SET Toleran Design D min /2 (2) The signal aains is correc value afer a delay of 2 + D SP, where D SP is he delay of he SP elemen. An addiional delay is inroduced by he MUX wih F as he selec signal. Thus, DEL should be delayed (compared o he sysem clock ) by: delay for DEL = 2+D SP + delay o f MUX + T SETUP E(3) where T SETUP E is he seup ime of he Equivalence Checker design. Afer DEL becomes high, if he E signal goes low, is pulled low and he value is lached o. In he nex clock cycle, would be used as he inpu for he sysem flip-flop. Thus, should aain is sable value before he nex rising edge of he sysem clock. Therefore, he minimum ime period required for he design o proec a glich of widh is given by he righ hand side of Equaion 4 D max + T SETUP SY S + T OUT SY S delay for DEL +T OUT E + delay o f AND1+T OUT DFF2 + T SETUP SY S (4) where T OUT E, T OUT DFF2 and T OUT SY S are he clock o oupu delays of he Equivalence Checker, DFF2 and he sysem flip-flop respecively. T SETUP SY S is he seup ime for he sysem flip-flop. Noe ha we do no need o add he seup ime for DFF2 in he righ hand side of Equaion 4, because aains is sable value before he rising edge of DEL. The lef hand side of Equaion 4 is he minimum duraion of he sysem clock, in erms of he maximum combinaional delay D max, he seup and clock-o-oupu imes of he sysem flipflop DFF modified. This minimum sysem clock duraion mus be larger han he righ hand side of Equaion 4 for he oupu o be correcly lached in every clock cycle. Using Equaions 3 and 4, we can find he maximum size of he SET induced glich ha we can proec he circui from. This is given by: 1/2(D max (T OUT E + T OUT DFF2 + D SP T OUT SY S + delay o f MUX + T SETUP E + delay o f AND1)) = 1/2(D max ) For a circui wih a given maximum delay D max, Equaion 5 can be used o find he value of he maximum SET induced glich ha he circui can olerae using our approach. If he clock period T is specified direcly, hen is given by 1/2(T (T OUT E + T OUT DFF2 + delay o f MUX + T SETUP SY S + D SP + T SETUP E + delay o f AND1)) In order o compare our resul wih [13], we designed our circuis o olerae gliches induced by an SET srike wih charge = 100fC and 150fC and wih τ β = 50ps and τ α = 200ps. These values of, τ α and τ β were experimenally simulaed using SPICE [31], and found o cause gliches of widhs 500ps and 600ps respecively when hey srike a minimum-sized inverer. In order o proec he circui from SET induced gliches of duraion 500ps and 600ps, he circui should have D min 1000ps and 1200ps respecively (from Equaion 2). I should also have a D max value saisfying Equaion 5. Since he operaion of our circui criically depends on he clock, i is imporan o analyze he affec of clock skew. If here is a clock skew of amoun s, he effecive D min reduces by s. As per Equaion 2, his will increase he consrain on as follows: (D min s)/2. The second consrain on ( Equaion 6) depends on he clock period, which will no be impaced by clock skew. 4 Experimenal Resuls The SET olerance of our circui srucures was simulaed in SPICE [31]. We used a 65nm BPTM [32] model card, wih VDD = 1V and V TN = V TP = 0.22V. The benchmark circuis for our simulaions were chosen from he LGSynh93 and he ITC design suies. (5) (6)

5 Area Overhead Delay Overhead Circui Regular (µm 2 ) Hardened (µm 2 ) %Ovh. D max (ps) Regular (ps) Hardened (ps) %Ovh. alu alu apex C C seq C C Average Table 1: Area and Delay Overhead of Our Circui Proecion Approach for = 0.15pC, τ α = 200ps and τ β = 50ps Area Overhead Delay Overhead Circui Regular (µm 2 ) Hardened (µm 2 ) %Ovh. D max (ps) Regular (ps) Hardened (ps) %Ovh. alu alu apex C C C C C seq C dalu Average Table 2: Area and Delay Overhead of Our Circui Proecion Approach for = 0.10pC, τ α = 200ps and τ β = 50ps Gae Oupu Volage (V) =0.1pC τ α =200ps τ β =50ps =0.15pC τ α =200ps τ β =50ps ime(ns) Figure 6: Volage Glich Waveform The radiaion srike was modeled as a curren source described as I()= (τ α τ β ) (e /τ α e /τ β). In order o compare our resuls wih [13], he firs se of experimens were done using a value of τ β = 50ps, τ α = 200ps and = 100 fc and 150 fc. We firs compue he widh of he volage glich when a charge of his value srikes a minimum-sized inverer. The resuls from his simulaion are shown in Figure 6. Noe ha he volage of he node rapidly rises, before sauraing a 1.6V. This occurs due o he urning on of juncion diodes in he devices (which urn on a 0.6V above VDD). We noe ha he resuling maximum glich widhs are 500ps and 600ps (for = 100 fc and 150 fc respecively). Based on his informaion, we know ha for our SET proecion scheme o work, we should uilize delay elemens whose delay value (for delaying he D signal of DFF modified) and 2+D SP + T SETUP E (for deriving DEL). The delay circui was consruced by connecing a high resisiviy POLY2 wire in series wih he inpu of a minimum-sized inverer (wih is PMOS device widh equal o he widh of he NMOS device). We define one POLY2 resisor followed by an inverer as a segmen. For = 100 fc, we required 4 segmens o achieve a delay, and 8 segmens o implemen he delay elemen for DEL. For = 150 fc, we used 4 and 10 segmens o achieve a delay of and DEL respecively. We were able o obain a higher delay wih 4 segmens for =150 fc compared o = 100 fc by increasing he value of he POLY2 resisors used. Noe ha he delay elemen can be modified o provide differen values of delay by eiher changing he number of segmens or he value of he resisors. The value of he resisors is limied since we require ha he oupu of he resisors ransiion beween V DD and GND wihin he required delay. Also, he SP elemen of our design should be SET oleran for volage gliches induced by = 100 fc and 150 fc. The exercise of deermining he sizing of he SP devices was conduced via SPICE [31] simulaions. The SP elemen for 100fC SET olerance was sized 30/12 3. For 150fC SET olerance, he SP elemen was sized 40/16. The remaining ransisors in Figure 5 were all cusom sized, and heir correc operaion was validaed in SPICE. 3 A size of X/Y indicaes ha all he PMOS devices were X imes minimum sized, and he NMOS devices were Y imes minimum According o he iming analysis discussion of Secion 3.4, in order o proec a glich of maximum widh, he minimum value of D max can be compued using Equaion 4. The only variable quaniy in his equaion is he delay o f AND1. For a 30-inpu NOR gae, o proec a circui from gliches of widhs 500ps and 600ps, his minimum value of D max was found o be 1415ps and 1605ps respecively. For he escases wih more han 30 oupus, a muli level gae was used o confirm ha he D max consrain is being me. Table 1 shows he delay and area overheads associaed wih our approach, for several examples. This able shows he overheads for an SET olerance of up o 150fC. Column 1 describes he circui under consideraion. Columns 2 and 3 repor he acive area in µm 2 for regular design and a design hardened by our approach. Column 4 repors he percenage area overhead of using our approach. Column 5 provides he D max value for he circuis. As required, all he escases in Table 1 have a Dmax value greaer han 1605ps. Columns 6 and 7 repor he delays for a regular design and a design hardened wih our approach. Column 8 repors he percenage delay overhead of our approach. Table 2 shows corresponding resuls for = 100fC. As per [33], indusrial circuis are ypically balanced o have roughly equal longes and shores pah lenghs. This is done in order o avoid hold-ime violaions. Sae of he ar echnology mapping ools ensure ha he D min is abou 80% of D max [33]. Based on his, aking D min o be 80% of D max, we noe ha D min /2 consrain is saisfied for all he circuis in Table 1 and Table 2. The SET oleran porion of our design is no in he criical pah of he sysem compuaion. I is sized carefully, so as o add minimal parasiic capaciances o he sysem flip-flop delay pah. Based on our simulaions, he -o- delay increased o 76ps using our approach (compared o 69ps). However, he seup ime decreased by 2ps (from 40ps o 38ps) using our approach. Addiionally, he increased load on he D inpu of he Maser sysem lach resuled in an increase in he delay (by 6.5ps) of he combinaional oupu of he design. As a consequence, he oal delay penaly associaed wih adding our SET oleran circui is 11.5ps per flipflop. These values have been used o calculae he delays as per he lef hand side of equaion 4. For he proeced case, he exra 6.5ps due o he increased load on he D inpu of he Maser sysem lach (explained above) was also included. The difference in our SET proecion circui (Figure 4) for = 100 fc and 150 fc is he delay elemen and he size of he SP elemen. The pah hrough he sysem flip-flop remains unalered. Therefore, he delay penaly in boh he cases is same. Based on he resuls in Table 1 and Table 2, we noe ha our approach has an average area overhead of 45.34% (39.31%) for = 150 fc ( = 100 fc). However, he corresponding delay penaly is 0.56% (0.51%) which is exremely small. Hence, our SET proecion approach has a negligible delay penaly. Table 4 summarizes our resuls in comparison o he resuls of [13] and [15]. The approach of [13] repors average area overheads which are comparable, and larger average delay overheads (abou 2.8%). Also, he approach of [13] provides 90% proecion o SET induced gliches, while our approach provides 100% proecion. For high speed, mission criical applicaions, he reduced delay of our scheme could be exremely crucial, especially when i comes wih a no addiional area penaly compared o [13]. In [15], he calculaed average area overheads were abou 17.6%. However, he average delay penaly was quie subsanial

6 Area Overhead Delay Overhead Max. Glich Widh Circui Regular (µm 2 ) Hardened (µm 2 ) %Ovh. D max (ps) Regular (ps) Hardened (ps) %Ovh (ps) apex apex b11 op C C C C ex5p k apex ex4p Average Table 3: Area and Delay Overhead of Our Circui Proecion Approach for glich widh up o = min{d min /2,(D max )/2} (28.65%). Therefore, our approach provides an aracive design poin. Technique Area Overhead (%) Delay Overhead (%) Proecion Our Approach % [13] % [15] % Table 4: Summary of our resuls compared o he approach of [13] and [15] For he cases in which D max is less han 1415ps (corresponding o = 100 fc), we can sill proec agains SET induced gliches of widh up o min{d min /2,(D max )/2}. To achieve his, in he circui for our SET proecion scheme shown in Figure 4, he delay elemen needs o be changed o a value = min{d min /2,(D max )/2}. This can be achieved by reducing he value of he POLY2 resisors used for he delay elemen, or by reducing he number of segmens used o consruc he delay elemens. Also, he SP elemen can be made smaller as well, since i needs o olerae a glich of lesser widh (compared o = 100 fc). In Table 3, we have used he area of our SET proecion circui for = 100 fc o compue he area overhead. Noe ha his is an upper bound on he acual area overhead achievable. To find ou he maximum widh of he SET induced glich () ha our echnique can proec hese circuis agains (min{d min /2,(D max )/2}), D min was aken o be 80% of D max [33]. We used he same value of as was used for he experimens wih = 100 fc, which was equal o 415ps. All oher columns in his able have he same meaning as he columns of Tables 1 and 2. The delay overhead is calculaed in he manner discussed earlier in his secion. I can be seen ha he delay overhead is minimal (0.99%) wih an area overhead of 61.41%. Noe ha his area overhead is an overesimae of he rue area overhead. 5 Conclusion In his paper, we presen a novel radiaion-hardened digial design approach. This approach uses Code Word Sae Preserving (SP) elemens a each flip-flop of he design, leaving he res of he design unalered. Since he SP elemens are conneced off he criical delay pah in he design, our SET oleran approach has negligible delay overheads. Our SP based approach provides 100% proecion for SET induced gliches of widhs up o min{d min /2,(D max )/2}. In case an SET error is deeced, hen he curren compuaion is repeaed, using he correc oupu, which is generaed laer in he same clock period by he SP elemen. The SP logic is designed o minimally impac he criical delay pah of he design, wih a delay penaly (averaged over several designs) of less han 1%. Thus our echnique is applicable for high-speed designs, where he addiional delay associaed wih SET proecion mus be kep a a minimum. References [1]. Zhou and K. Mohanram, Transisor sizing for radiaion hardening, in Proc. Inernaional Reliabiliy Physics Symposium, pp , apr [2] A. Johnson, Scaling and echnology issues for sof error rae, in Proc. Annual Research Conference on Reliabiliy, oc [3] M. Caffrey, P. Graham, E. Johnson, and M. Wirhli, Single-even upses in SRAM FPGAs, in Proc. Inernaional Conference on Miliary and Aerospace Programmable Logic Devices, sep [4] C. Carmichael, E. Fuller, M. Caffrey, P. Blain, and H. Bogrow, SEU miigaion echniques for virex FP- GAs in space applicaions, in Proc. Inernaional Conference on Miliary and Aerospace Programmable Logic Devices, sep [5] T. Speers, J. Wang, B. Cronquis, J. McCollum, H. Tseng, R. Kaz, and I. Kleyner, 0.25pm flash memory based FPGA for space applicaion, in Proc. Inernaional Conference on Miliary and Aerospace Programmable Logic Devices, sep [6] B. Gill, M. Nicolaidis, F. Wolff, C. Papachrisou, and S. Garverick, An efficien BICS design for SEUs deecion and correcion in semiconducor memories, in Proceedings, Design, Auomaion and Tes in Europe, pp , march [7] W. Massengill, M. Alles, and S. Kerns, SEU error raes in advanced digial CMOS, in Proc. Second European Conference on Radiaion and is Effecs on Componens and Sysems, pp , sep [8] J. Pickle and J. Blandford, CMOS RAM cosmic-ray-induced error rae analysis, IEEE Trans. on Nuclear Science, vol. NS-29, pp , [9] K. Hass and J. Gambles, Single even ransiens in deep submicron CMOS, in Proc. IEEE 42nd Midwes Symposium on Circuis and Sysem, pp , [10] W. Beauvais, P. McNuly, W. A. Kader, and R. Reed, SEU parameers and proon-induced upses, in Proc. Second European Conference on Radiaion and is Effecs on Componens and Sysems, pp , sep [11] G. Messenger, Collecion of charge on juncion nodes from ion racks, IEEE Trans. Nuclear Science, vol. 29, no. 6, pp , [12] A. Dharchoudhury, S. Kang, H. Cha, and J. Pael, Fas iming simulaion of ransien fauls in digial circuis, in Proc. IEEE/ACM Inernaional Conference on Compuer-Aided Design, pp , Nov [13]. Zhou and K. Mohanram, Gae sizing o radiaion harden combinaional logic, in Proceedings, Compuer-Aided Design of Inegraed Circuis and Sysems, pp , Jan [14] D. Mavis and P. Eaon, Sof error rae miigaion echniques for modern microcircuis, pp , [15] L. Anghel, D. Alexandrescu, and M. Nicolaidis, Evaluaion of a sof error olerance echnique based on ime and/or space redundnacy, in Proceedings, 13h Symposium on Inegraed Circuis and Sysems Design, pp , [16] S. Mira, N. Seifer, M. Zhang, and K. Kim, Robus sysem design wih buil-in sof-error resilience, IEEE Compuer, pp , Feb [17] E. Fuller, M. Caffrey, A. Salazar, C. Carmichael, and J. Fabula, Radiaion esing updae, SEU miigaion, and availabiliy analysis of he Virex FPGA for space reconfigurable compuing, in Proc. Inernaional Conference on Miliary and Aerospace Programmable Logic Devices, sep [18] J. Wang, B. Cronquis, and J. McGowan, Rad-hard/hi-rel FPGA, in Proc. of he Third ESA Elecronic Componens Conference, apr [19] T. May and M. Woods, Alpha-paricle-induced sof errors in dynamic memories, IEEE Trans. on Elecron Devices, vol. ED-26, pp. 2 9, jan [20] G. Agrawal, L. Massengill, and K. Gulai, A proposed SEU oleran dynamic random access memory (DRAM) cell, in IEEE Transacions on Nuclear Science, vol. 41, pp , Dec [21] M. Nicolaidis, Time redundancy based sof-error olerance o rescue nanomeer echnologies, in VLSI Tes Symposium, pp , April [22]. Zhou and K. Mohanram, Transisor sizing for radiaion hardening, in Proceedings, Reliabiliy Physics Symposium Proceedings, pp , [23] M. Nicolaidis, Time redundancy-based sof-error olerance o rescue nanomeer echnologies, in Proceedings, IEEE VLSI Tes Symposium, pp , [24] R. Garg, N. Jayakumar, S. Khari, and G. Choi, A design approach for radiaion-hard digial elecronics, in DAC 06: Proceedings of he 43rd annual conference on Design auomaion, pp , ACM Press, [25] J. Rabaey, Digial Inegraed Circuis: A Design Perspecive. Prenice Hall Elecronics and VLSI Series, Prenice Hall, [26] E. E. C. for Space Sandardizaion, Energeic Paricle Radiaion, hp:// [27] J. Feynman, G. Spiale, J. Wang, and S. Gabriel, Inerplaneary Proon Fluence Model: JPL J. Geophys. Res. 98, A8, [28] S. Das, S. Pan, D. Robers, S. Lee, D. Blaauw, T. Ausin, T. Mudge, and K. Flauner, A self-uning DVS processor using delay-error deecion and correcion, Journal of VLSI Circuis, pp , Jun [29] S. Das, D. Robers, S. Lee, S. Pan, D. Blaauw, T. Ausin, T. Mudge, and K. Flauner, A self-uning dynamic volage scaled processor using delay-error deecion and correcion, pp , Apr [30] D. Erns, N. S. Kim, S. Das, S. Pan, R. Rao, T. Pham, C. Ziesler, D. Blaauw, T. Ausin, K. Flauner, and T. Mudge, Razor: a low-power pipeline based on circui-level iming speculaion, in Inernaional Symposium on Microarchiecure, pp. 7 18, Dec [31] L. Nagel, Spice: A compuerprogram o simulae compuer circuis, in Universiy of California, Berkeley UCB/ERL Memo M520, May [32] Y. Cao, T. Sao, D. Sylveser, M. Orshansky, and C. Hu, New paradigm of predicive MOSFET and inerconnec modeling for early circui design, in Proc. of IEEE Cusom Inegraed Circui Conference, pp , Jun hp://www-device.eecs.berkeley.edu/ pm. [33] W. K. C. Lam, R. K. Brayon, and A. L. Sangiovanni-Vincenelli, Valid clock frequencies and heir compuaion in wavepipelined circuis, Compuer-Aided Design of Inegraed Circuis and Sysems, vol. 15, no. 7, pp , 1996.