LATCHES Implementation With Complex Gates

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Clement Jones
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1 LECTURE 7 SEUENTIAL MOS LOGIC CIRCUITS Implemenaion Wih Primiive Gaes Lecure Goals * Undersand and be able o design: laches and flip-flops implemened wih primiive gaes laches and flip-flops implemened wih complex gaes laches and flip-flops implemened wih ransmission gaes laches and flip-flops implemened wih hree-sae srucures, and Schmid riggers. Read he Inroducion and Behavior of Bisable Elemens in Kang and Leblebici. Review he gae-level implemenaions SR Lach, Clocked SR Lach, Clocked J-K Lach, and Maser-Slave Flip-Flop in Kang and Leblebici. The laer maerial is ypically covered in logic design courses excep for he brief reamen of delay issues given. Assignmen Kang and Leblebici: pp /7/98 3/3/02 2 1/7/98 3/3/02 Implemenaion Wih Complex Gaes Implemenaion Wih Complex Gaes NOR-ype Clocked S-R Lach Using AOI (AN-OR-INVERT) gae: The S-R Lach conains wo copies of he following srucure: This srucure is implemened as a complex AOI gae and duplicaed o form an S-R Lach: R S No. of FETs in NOR-based clocked CMOS S-R Lach = 20 No. of FETs in AOI-based clocked CMOS S-R Lach = 12 NAN-ype S-R Lach Using OAI (OR-AN-INVERT) gae: (Noe ha NAN is dual of NOR and OAI is dual of AOI.) No. of FETs in NAN-based clocked CMOS S-R Lach = 16 No. of FETs in AOI-based clocked CMOS S-R Lach = 18 (AOI-based S-R requires only 14) Maser-Slave JK Flip-Flop No. of FETs in NAN-based CMOS JK MSFF = 36 No. of FETs in AOI-based CMOS JK MSFF = 28 Conclusion: Complex gae implemenaions of sorage elemens can reduce ransisor couns. Also, here is poenial for reduced delay. 3 1/7/98 3/3/02 4 1/7/98 3/3/02

2 Implemenaion Wih Transmission Gaes Implemenaion Wih Three-Sae Transmission gae Lach: Uses swich-like properies of ransmission gaes Operaion: For = 1, = and =. A bi is loaded. For = 0, = () and = ( ). Thus, a bi is sored. Noe ha Propagaion elay o is less han delay o. Wha abou changes in relaive o changes in? Seup Time and Hold Time relaive o : 1 0 evice couns for TG-based lach reduced from AOI/OAI No. of FETs in AOI-based clocked -lach = 14 No. of FETs in TG-based clocked -lach = 8 (plus 2 o inver clock) 5 1/7/98 3/3/02 (No ri-sae which is a rademark of Naional Semiconducor) Similar o he TG-based implemenaion, excep as if connecion beween n and p FETs in a driving inverer and inpu side of a driven ransmission gae is severed. Requires addiion of inverer a inpu firs. 6 1/7/98 3/3/02 Locaion of increases inernal node loading, so may need oupu inverer. FLIP-FLOP Maser-Slave & Negaive Edge-Triggered FLIP-FLOP Maser-Slave & Negaive Edge-Triggered 7 1/7/98 3/3/02 Why? Avoids redundancy produced by parallel FETs in ransmission gae. Failure of one of wo devices open causes easy-o-deec funcional failure raher han more insidious delay increase. Maser-Slave Flip-Flop M TG-Based Lach TG-Based Lach for generaing can be in each flip-flop, common o all flipflops, or shared among some subse of flip-flops. S Noe ha oupus are used o reduce seup ime and propagaion delay for flip-flop oupu (no for flip-flop oupu). This increases hold ime. Since M follows he inpu wih = 1, i may change unil jus a seup ime before becomes 0 and mus remain here a hold ime afer he change. Thus, his is also a negaive edge-riggered flip-flop! By inerchanging he and inpus, can obain a posiive edge-riggered flip-flop In conras, SR and JK flip-flops based on SR laches have a 1 s caching behavior which makes hem maser-slave only. If wih = 1, a emporary incorrec value occurs on he inpus o hese flip-flops which changes he sae of M, ha sae change can persis (i. e., presence of he 1 is caugh) and cause an incorrec oupu change when becomes 0. Thus, he seup ime is he enire ime while = 1. To implemen a negaive edge-riggered (or posiive edge-riggered) flip-flop, a flip-flop for M wih inpu logic can be used. For example: = J + K 8 1/7/98 3/3/02

3 FLIP-FLOP Clock Skew Issues The Circui In a TG or hree-sae implemened flip-flop, if and changes are skewed (misaligned) enough, hen a change in M can immediaely propagae ino S violaing he maser-slave (edge-riggered) concep. If global or shared drivers used, can use he following o reduce skew: IN 0 1 Adjus devices sizes o mach inverer delay M1 M2 M4 M5 For he global case, skew can also arise due o inerconnec delay; will discuss laer in he course. 9 1/7/98 3/3/ /7/98 3/3/02 The VTC Applicaions Inpu line wih reflecions: V T Schmid Trigger 11 1/7/98 3/3/ /7/98 3/3/02

4 Applicaions Slowly changing inpu signal (wih noise): = 0: V T Schmid Trigger = = V n M1 ON M2 ON M4 M5 13 1/7/98 3/3/ /7/98 3/3/02 = V n and rising: V GS4 = V n and rising: = V GS4 < V n M1 ON M2 ON M4 M5 ON V GS4 M1 M2 V = 0 x V M4ON V z M5 ON Trigger even occurs, pulling o 0 V. =, he forward rigger volage. Jus before M4 urns on, 15 1/7/98 3/3/ /7/98 3/3/02

5 = V GS4 + V S5 = V n + V S5 => V S5 = V GS5 V n. Ignoring body effec, his implies M5 a edge of sauraion, giving: I 5 = (k 5 /2) ( V n ) 2 is also sauraed, I 6 = (k 6 /2) ( ) 2 Since I 4 = 0, I 5 = I 6. Equaing and solving, k ( V k V p ) k k 3 For design, use specified o solve for k 1 /k 3. k V k n k k 6 For design, use specified o solve for k 5 /k 6. By symmery, 17 1/7/98 3/3/ /7/98 3/3/02

-To become familiar with the input/output characteristics of several types of standard flip-flop devices and the conversion among them.

-To become familiar with the input/output characteristics of several types of standard flip-flop devices and the conversion among them. Experimen 6 Sequenial Circuis PART A: FLIP FLOPS Objecive -To become familiar wih he inpu/oupu characerisics of several ypes of sandard flip-flop devices and he conversion among hem. References Donald