-To become familiar with the input/output characteristics of several types of standard flip-flop devices and the conversion among them.

Transcription

1 Experimen 6 Sequenial Circuis PART A: FLIP FLOPS Objecive -To become familiar wih he inpu/oupu characerisics of several ypes of sandard flip-flop devices and he conversion among hem. References Donald P.Leach : Experimenal in Digial Principles, 3 rd Ediion Malvino/Leach : Digial Principles and Applicaions Baree : Digial Compuer Fundamenals, 6 h Ediion John F.Wakerley : Digial Designs, Principle and Pracice, 2 nd Ediion Ronald A Reis: Digial Elecronics Through Projec Analysis, 1 s Ediion Componen Inroducion 1-74LS00 TTL IC 1-74LS74 TTL IC 1-74LS76 TTL IC Logic circui whose oupus depend upon circui inpus as well as previous values of circui oupus described as heir presen saes are known as sequenial logic circuis. A sequenial sysem can be defined in erms of is inpus and presen sae. Tha is, he nex sae of he sequenial sysem can be deermined from hese wo quaniies. The (clocked) RS, D, JK and T flip-flops are characerized by he following sae ables. 1 P a g e

2 The? in he RS flip-flop sae able (refer o able 1) means ha when R = 1 and S = 1 hen he nex sae is no deermined explicily. Procedure 1) Consruc he cross-coupled NAND gae basic RS flip-flop depiced in fig 6.1 and verify is sequenial operaion by compleing he iming diagram shown in fig 6.2. Fig 6.1 : Basic RS flip flop 2 P a g e

3 R S Q Q Fig 6.2 : Timing Diagram 2) Consruc he clocked RS flip flop of fig 3. Complee iming diagram as in fig 6.2 bu add clock pulses as exra inpu. Use pulse swich as your clock source. Fig 6.3 : Clocked RS flip-flop 3) Simulaneously applicaion of ones o R and S of he clocked RS flip flop, observe he oupus. 4) Since he consruced clocked RS flip flop is symmeric, we can change he posiion of R & S, and Q and Q. I is sill a clocked RS flip flop. Repea sep 3, see wha has happened. Give your conclusion. 3 P a g e

4 5) Using he 74LS74 dual D flip flop, invesigae he operaion of he D flipflop (see fig 6.4). Compare your resul wih he sae able given above. Pay aenion o he change in sae of he device as he clock signal is rising or falling. Compare he following iming diagram. Fig 6.4 : D Flip Flop Assume when =0, Q=0 CLK D Q Fig 6.5 : Timing Diagram 6) Le inpu R open, ground he inpu S, wach he oupu and hen le S open, ground R, wach he oupu. Deermine he usage of R and S. 4 P a g e

5 7) Using he 74LS76 dual JK flip flop, deermine is logical operaion. The circui diagram is shown in fig 6.6. Pay aenion o he change in sae of he device as he clock signal is rising or falling. Compare he following iming diagram. Fig 6.6 : JK Flip flop assume when =0, y=0 CLK K J Y Fig 6.7 : Timing diagram 5 P a g e

6 8) The flip flop can simulae each oher. Consruc he circui shown in fig 6.8. Verify is sequenial operaion as a D flip flop. Complee he following iming diagram. Compare i wih he iming diagram of fig 6.5. Fig 6.8 : D flip flop ( consruced by JK FF) assume when =0, Q=0 CLK D Q Fig 6.9 : Timing Diagram 6 P a g e

7 9) Wire he circui shown in fig 6.10, verify ha i is a T flip flop by. drawing he iming diagram for he T flip flop. Fig 6.10 : T flip flop 7 P a g e

8 Experimen 6 Sequenial Circuis PART B: COUNTERS Objecives -To design a ripple couner using JK flip flop. -To connec a pre-seable couner and observe is operaion. -To creae differen couner module by decoding oupus and loading prese inpus. Inroducion A couner is a circui consising of a number of Flip Flop and gaes working ogeher o coun he number of clock pulses applied o is inpu. Such couners are used in digial clocks, frequency couners, digial volmeers, digial compuers, and numerous oher applicaions. There are numerous ypes of couners, and we canno look a heme in his experimen. The basic binary couner is probably he simples o consruc and form he basis for more advanced ypes of couners. In his experimen, we look a some of he couner circuis found mos ofen and give you an opporuniy o connec and observe hem. Ripple Couner(Asynchronous) A ripple couner is a serial couner. The clock inpu is applied o only he firs of he series of he Flip Flop. Clock pulses for he oher Flip Flop come from he preceding Flip Flop.Thus, he clock pulse ripple hrough he circui in a series fashion. Such circui is also called asynchronous since he only pulse required for he operaion is he clock pulse. The JK Flip Flop have he J and K inpus boh ied high, which allows hem o oggle wih each inpu pulse. Fig 7-1 shows a 4-bi ripple couner. 8 P a g e

9 Fig. 7.1 : Logic diagram for a 4-bi (mod16) ripple couner. Synchronous Couners The synchronous couner has he limiaion of he ime lag in riggering all he Flip Flop. To cure his problem, parallel couners can be used. The logic diagram for a 3-bi parallel couner is shown in fig 7-2. Noe ha all CLK inpus are ied direcly o inpu clock. They are wired in parallel. Noe ha also he use of he AND gae a he oupu of Flip Flop 2 which will eiher hold Flip Flop 3(AND=0), or oggle Flip Flop 3(AND=1). Fig P a g e

10 UP DOWN IC Couner : The The is a synchronous up-down 4-bi binary couner. I has a maser rese (CLR), and i can be rese o any desired coun wih he parallel load inpus. Basically, i funcions like any binary couner, excep ha is has wo clock inpus, one for UP couning, and he oher for DOWN couning. The logic symbol for he is shown in fig 7-3 (examine he daa shee).load is a conrol inpu o load daa ino pins A, B,C and D. Figure 7.3 Pin CLR is he maser rese, and i is normally held below (a high level on CLR will rese all FF). CO and BO are oupus o be used o drive he following s and we shall simply leave hem open. The clock inpus are UP and DOWN. Placing he clock on UP will cause he couner o coun UP, and placing he clock on DOWN will cause he couner o coun DOWN. Noe ha he clock should be conneced o eiher UP or DOWN, bu no boh, and he unused inpus should be held HIGH. The oupus of he couner are QA,QB,QC and QD. Componens needed: 1-74LS00 Quad NAND Gae TTL IC 2-74LS76 Dual JK Flip Flop 1-74LS93 4 bi binary couner 1-74LS193 4 bi UP-DOWN couner 1- Oscilloscope 10 P a g e

11 Procedure 1) Consruc he Ripple couner shown in fig 7.1. Clear all oupu FF by giving a negaive clock pulses o he clear inpus, and apply he clock of a one sho acuaed by he push buon. Repea ha for 17 clock pulses. Record he oupu QA,QB,QC and QD of he couner in able 1 below (MSB = QD ; LSB = QA ) Draw he iming diagram of he above circui. CLK Pulse Q C Q D Q B Q A CLK Pulse Q D Q C Q B Q A Table 1 2) Use he 74LS93 couner o implemen a) A modulo 16 couner; b) A decade couner 3) Make hese connecions o he couner of fig 7.3 Pin 15,1,10 and 9 (prese daa inpus ) Open Pins 12 and 13 (CO and BO)Open Pins 3,2,6 and 7 (oupus ) o LED s Pin 11 (LOAD) o +Vcc Pin 16 (+Vcc) o +Vcc Pin 14 (CLR) o ground Pin 8 (GND) o ground 11 P a g e

12 4) For he coun-up mode, connec pin 4 (DOWN) o +Vcc, and apply he clock o pin 5(UP). Record carefully he 4 oupu waveforms wih respec o he clock. 5) For he coun-down mode, connec pin 5(UP) o +Vcc, and apply he clock o pin 4(DOWN). Record he resuling oupu waveforms. 12 P a g e

13 Experimen 6 Sequenial Circuis PART C: SHIFT REGISTERS Abou regisers A flip-flop is a sequenial device able o sore one binary bi of informaion. More general sequenial device, consruced by inerconnecing a number of flip flops, can process one or more bis of informaion and are known as REGISTERS and COUNTERS. A REGISTER is a memory device used for soring and manipulaing daa regisers (found by he housand in digial compuers)may be classified according o how heir sored informaion is enered or removed. A SERIAL regiser is one in which he daa is enered or removed one bi a a ime and a PARALLEL regiser acceps or ransfers all bis of daa simulaneously. Serial inpu parallel oupu neworks as well as he inverse are also available. References Donald P.Leach : Experimenal in Digial Principles, 3rd Ediion Baree : Digial Compuer Fundamenals, 6h Ediion John F. Wakerley : Digial Design, Principle and Pracice, 2nd Ediion Ronald A Reis : Digial Elecronics Through Projec Analysis, 1s Ediion Garrord & Borns : Digial Logic, Analysis, Applicaion & Design Componen 1-74LS04 Hex inverer TTL IC 3-74LS95 4 bi parallel access shif regiser 2-74LS74 Dual D FF TTL IC 1-74LS193 4 bi UP-DOWN couner 13 P a g e

14 Procedure A) Four-bi Memory Regiser (Parallel In-Parallel Ou) Memory regiser ypically provide emporary sorage of daa, such as he coun from a couner. The device supplying he daa is hen free o perform oher asks while he daa is preserved for he fuure use, such as being decoded and read ou or being displayed. Insall wo 74LS74 Dual D ype Posiive Edge Trigger Flip-Flop IC s ino he logic lab breadboard. Connec hese D flip-flops o implemen he following Parallel In- Parallel Ou 4 Bi memory regiser shown in fig 8-1. Use swiches as inpus and LED s for oupus. Also, remember he power connecions for each chip. Before enering any daa, be sure o clear all flip-flops. Remember ha he clear should be normally be in he HIGH sae. Swich he clear inpu as follows: HIGH LOW HIGH o clear he Flip-Flop. Describe he operaion of his circui as a 4-bi memory devices by enering various combinaions of inpus (A,B,C,D) and observing he oupus (Q1,Q2, Q3,Q4) as you will simulae clock pulses on he CLK bus (i.e common clock inpu o all he flip-flops ). Wha range of numerical values can be sored in his 4-bi memory regiser? Show a sample iming diagram for wo differen ses of inpu daa. Figure P a g e

15 B) Four-bi Shif Regiser wih Serial Enry Anoher ype of regiser is a shif regiser. Alhough i can also sored daa as a memory regiser, i is more ofen used o process or move he daa.usually he movemen is a shif of daa from one sage of he regiser o an adjacen sages eiher from lef o righ( a righ shif regiser ), from righ o lef (a lef shir regiser) or in boh direcions ( a bidirecional shif regiser). Shif regisers differ from memory regisers in ha adjacen sages are conneced o allow shifs of daa from one sage o he nex. A serial enry of shif regiser capable of soring 4-bi words as shown in fig 8-2. The sages used here are D flip-flop, bu oher ypes may used as well. The oupus Q1, Q2, Q3 and Q4 are made O iniially by a Clear conrol. The firs daa bi, say D1 is applied o he serial inpu erminal; and on he firs posiive edge of he CLK, i is loaded ino he firs sage as Q1 = D1. Nex D2 is applied and clocked in as Q1 = D2, a which poin D1 is shifed o Q2 = D1. Coninuing he process wih D3 and D4,he nex wo serial enries, we have Q1 = D4, Q2 = D3, Q3 = D2 Q4 = D1. Try several inpu combinaions for his sequenial nework o learn how i operaes. Observe ha he inpu daa may be aken in eiher a serial or parallel manner. Tha is, he oupus Q1,Q2,Q3 and Q4 may be all read simulaneously or he oupu may be read one bi a a ime a he oupu Q4 of he fourh sage. Deermine he iming diagram for he following se of inpus; D1 = D4=1, D2 = D3 =0. show he inpu CLK, Q1, Q2, Q3 and Q4. Carefully observe he ime delay on he oscilloscope and explain how his happens. Figure P a g e

16 Pin Connecion Diagram 74LS00 TTL IC 74LS74 TTL IC 16 P a g e

17 74LS76 Dual JK Flip Flop 74LS193 4 bi UP-DOWN couner 17 P a g e

18 74LS93 4 bi binary couner 74LS95 4 bi parallel access shif regiser 18 P a g e