Overview ECE 553: TESTING AND TESTABLE DESIGN OF. Ad-Hoc DFT Methods Good design practices learned through experience are used as guidelines:

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1 ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS Design for Tesabiliy (DFT) - 1 Overview Definiion Ad-hoc mehods Scan design Design rules Scan regiser Scan flip-flops Scan es sequences Overhead Scan design sysem Summary 11/11/ Definiion Design for esabiliy (DFT) refers o hose design echniques ha make es generaion and es applicaion cos-effecive. DFT mehods for digial circuis: Ad-hoc mehods Srucured mehods: Scan Parial Scan Buil-in self-es (BIST) Boundary scan 11/11/ Good design pracices learned hrough experience are used as guidelines: Don -s and Do-s Avoid asynchronous (unclocked) feedback. Avoid delay dependan. Avoid parallel drivers. Avoid monosables and self-reseing. Avoid gaed clocks. Avoid redundan gaes. Avoid high fanin fanou combinaions. 11/11/ Good design pracices learn hrough experience are used as guidelines: Don -s and Do-s (cond.) Make flip-flops iniializable. Separae digial and analog circuis. Provide es conrol for difficul-o-conrol signals. Buses can be useful and make life easier. Limi gae fanin and fanou. Consider ATE requiremens (risaes, ec.) Design reviews Manual analysis Conduced by expers. Programmed analysis Using design audiing ools Programmed enforcemen Mus use cerain design pracices and cell ypes. Objecive: Adherence o design guidelines and esabiliy improvemen echniques. 11/11/ /11/

2 Disadvanages of ad-hoc DFT mehods: Expers and ools no always available. Tes generaion is ofen manual wih no guaranee of high faul coverage. Design ieraions may be necessary. Scan Design Objecives Simple read/wrie access o all or subse of sorage elemens in a design. Direc conrol of sorage elemens o an arbirary value (0 or 1). Direc observaion of he sae of sorage elemens and hence he inernal sae of he circui. Key is Enhanced conrollabiliy and observabiliy. 11/11/ /11/ Scan Design Circui is designed using pre-specified design rules. Tes srucure (hardware) is added o he verified design: Add one (or more) es conrol () primary inpu. Replace flip-flops by scan flip-flops and connec o form one or more shif regisers in he es mode. Make inpu/oupu of each scan shif regiser conrollable/observable from /. Use combinaional ATPG o obain ess for all esable fauls in he combinaional. Add shif regiser ess and conver ATPG ess ino scan sequences for use in manufacuring es. Scan Design Rules Use only clocked D-ype flip-flops for all sae variables. A leas one pin mus be available for es; more pins, if available, can be used. All clocks mus be conrolled from s. Clocks mus no feed daa inpus of flip-flops. 11/11/ /11/ Correcing a Rule Violaion Scan Flip-Flop (maser-slave) All clocks mus be conrolled from s. D2 D1 FF D SD Logic overhead MUX Maser lach Slave lach D flip-flop D2 D1 FF Maser open Slave open Normal mode, D seleced Scan mode, SD seleced 11/11/ /11/

3 Level-Sensiive Scan-Design Lach (LSSD) Adding Scan Srucure D Maser lach Slave lach M S SD K Logic overhead M K M K D flip-flop S 11/11/ Normal mode Scan mode or K No shown: or M/S feed all s (scan Flipflops). 11/11/ Tes Vecors Tes Vecors I1 I2 Don care or random bis Presen sae I1 I2 O1 O2 S1 S2 11/11/ N1 N2 Nex sae S1 S O1 O2 N1 N2 Sequence lengh = (n sff + 1) n comb + n sff clock periods n comb = number of combinaional vecors n sff = number of scan flip-flops 11/11/ Tesing Scan Regiser Scan regiser mus be esed prior o applicaion of scan es sequences. A shif sequence of lengh n sff +4 in scan mode (=0) produces 00, 01, 11 and 10 ransiions in all flip-flops and observes he resul a oupu. Toal scan es lengh: ((n sff + 1) n comb + n sff ) + (n sff + 4) clock periods. (n comb + 2) n sff + n comb + 4 clock periods. Example: 2,000 scan flip-flops, 500 comb. vecors, oal scan es lengh ~ 10 6 clocks. Muliple scan regisers reduce es lengh. 11/11/ Muliple Scan Regisers Scan flip-flops can be disribued among any number of shif regisers, each having a separae scanin and scanou pin. Tes sequence lengh is deermined by he longes scan shif regiser. Jus one es conrol () pin is essenial. / 11/11/ M U X / 3

4 Scan Overhead IO pins: One pin necessary. Area overhead: Gae overhead = [4 n sff /(n g +10n ff )] x 100%, where n g = comb. gaes; n ff = flip-flops; Example n g = 100k gaes, n ff = 2k flip-flops, f p, overhead = 6.7%. More accurae esimae mus consider scan wiring and layou area. Performance overhead: Muliplexer delay added in combinaional pah; approx. wo gae-delays. Flip-flop oupu loading due o one addiional fanou; approx. 5-6%. 11/11/ Scanin Hierarchical Scan Scan flip-flops are chained wihin subneworks before chaining subneworks. Advanages: Auomaic scan inserion in nelis Circui hierarchy preserved helps in debugging and design changes Disadvanage: Non-opimum chip layou Scanou Scanin Hierarchical nelis Fla layou 11/11/ Scanou IO pad Flipflop cell Opimum Scan Layou X cell Y Y Rouing channels Inerconnecs Acive areas: XY and X Y 11/11/ X SCAN OUT Scan Area Overhead Linear dimensions of acive area: X = (C + S) / r X = (C + S + αs) / r Y = Y + ry = Y + Y(1--β) / T Area overhead X Y --XY XY XY = x 100% XY 1--β = [(1+αs)( ) 1] x 100% T y = rack dimension, wire widh+separaion C = oal comb. cell widh S = oal non-scan FF cell widh s = fracional FF cell area = S/(C+S) α = cell widh fracional increase r = number of cell rows or rouing channels β = rouing fracion in acive area T = cell heigh in rack dimension y 1--β = (αs ) x 100% T 11/11/ Example: Scan Layou 2,000-gae CMOS chip Fracional area under flip-flop cells, s = Scan flip-flop () cell widh increase, α = 0.25 Rouing area fracion, β = Cell heigh in rouing racks, T = 10 Calculaed overhead = 17.24% Acual measured daa: Scan implemenaion Area overhead Normalized clock rae None ATPG Example: S5378 Number of combinaional gaes Number of non-scan flip-flops (10 gaes each) Number of scan flip-flops (14 gaes each) Gae overhead Number of fauls / for ATPG Faul coverage Faul efficiency Number of ATPG vecors Scan sequence lengh Original 2, % 4,603 35/ % 70.9% Full-scan 2, % 4, / % 100.0% ,662 Hierarchical 16.93% 0.87 Opimum layou 11.90% /11/ /11/

5 Rule violaions Auomaed Scan Design Behavior, RTL, and Design and verificaion Scan design rule audis Gae-level nelis Scan hardware are ATPG inserion vecors Scan sequence and es program generaion Tes program Scan chain order Design and es daa for manufacuring Scan nelis Chip layou: Scanchain opimizaion, iming verificaion Mask daa 11/11/ Timing and Power Small delays in scan pah and clock skew can cause race condiion. Large delays in scan pah require slower scan clock. Dynamic muliplexers: Skew beween and signals can cause momenary shoring of D and SD inpus. Random signal aciviy in combinaional circui during scan can cause excessive power dissipaion. 11/11/ Summary Scan is he mos popular DFT echnique: Rule-based design Auomaed DFT hardware inserion ATPG Advanages: Design auomaion High faul coverage; helpful in diagnosis Hierarchical scan-esable modules are easily combined ino large scan-esable sysems Moderae area (~10%) and speed (~5%) overhead Disadvanages: Large es daa volume and long es ime Basically a slow speed (DC) es 11/11/

Lecture 23 Design for Testability (DFT): Full-Scan

Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads