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1 676 Chaper 8 Sequenial Logic Design Pracices Synchronizing High-Speed Daa Transfers A very common problem in compuer sysems is synchronizing exernal daa ransfers wih he compuer sysem clock. A simple example is he inerface beween personal compuer s nework inerface card and a 100 Mbps Eherne link. The inerface card may be conneced o a PCI bus, which has a MHz clock. Even hough he Eherne speed is an approximae muliple of he bus speed, he signal received on he Eherne link is generaed by anoher compuer whose ransmi clock is no synchronized wih he receive clock in any way. Ye he inerface mus sill deliver daa reliably o he PCI bus. Figure shows he problem. NRZ serial daa RDATA is received from he Eherne a 100 Mbps. The digial phase-locked loop (DPLL) recovers a 100- MHz clock signal R which is cenered on he 100 Mbps daa sream and MHz R 100 MHz DPLL shif regiser SREG RDATA DIN EN 100 Mbps Eherne RBYTE[7:0] SBYTE[7:0] received daa UT[7:0] DIN[7:0]? UT[7:0] SD[7:0] bye synchronizer Figure DIN[7:0] Eherne synchronizaion problem. ONE NIBBLE The explanaion of 100 Mbps Eherne recepion above is oversimplified, bu sufficien for discussing he synchronizaion problem. In realiy, he received daa AT A TIME rae is 125 Mbps, where each 4 bis of user daa is encoded as a 5-bi symbol using a so-called 4B5B code. By using only 16 ou of 32 possible 5-bi codewords, he 4B5B code guaranees ha regardless of he user daa paern, he bi sream on he wire will have a sufficien number of ransiions o allow clock recovery. Also, he 4B5B code includes a special code ha is ransmied periodically o allow nibble (4-bi) and bye synchronizaion o be accomplished very easily. As a resul of nibble synchronizaion, a ypical 100-Mbps Eherne inerface does no see an unsynchronized 100 MHz sream of bis. Insead, i sees an unsynchronized 25 MHz sream of nibbles. So, he deails of a real 100-Mbps Eherne synchronizer are differen, bu he same principles apply.

2 Secion 8.9 Synchronizer Failure and Measabiliy ns 80 ns R Figure Eherne link and sysem clock iming. 30 ns allows daa o be clocked bi-by-bi ino an 8-bi shif regiser. A he same ime, a bye synchronizaion circui searches for special paerns in he received daa sream ha indicae bye boundaries. When i deecs one of hese, i assers he signal and does so on every eighh subsequen R ick, so ha is assered whenever he shif regiser conains an aligned 8-bi bye. The res of he sysem is clocked by a MHz clock. We need o ransfer each aligned bye RBYTE[7:0] ino a regiser SREG in s domain. How can we do i? Figure shows some of he iming. We immediaely see is ha he bye-aligned signal,, is assered for only 10 ns per bye. We have no hope of consisenly deecing his signal wih he asynchronous, whose period is a much longer 30 ns. The sraegy ha is almos universally followed in his kind of siuaion is o ransfer he aligned daa firs ino a holding regiser HREG in he receive clock (R) domain. This gives us a lo more ime o sor hings ou, 80 ns in his case. Thus, he? box in Figure can be replaced by Figure 8-104, which shows HREG and a box marked SCTRL. The job of SCTRL is o asser during exacly one 30-ns period, so ha he oupu of HREG is and sable for he seup and hold imes of regiser SREG in he domain. also serves as a new-daa available signal for he res of he inerface, indicaing ha a new daa bye will appear on SBYTE[7:0] during he SCTRL Figure Bye holding regiser and conrol. HREG R EN RBYTE[7:0] DIN[7:0] UT[7:0] SBYTE[7:0]

3 678 Chaper 8 Sequenial Logic Design Pracices 10 ns 80 ns R 30 ns SBYTE Figure Timing for SBYTE and possible iming SD for. nex period. Figure shows possible iming for based on his approach and he previous iming diagram. Figure is a circui ha can generae wih he desired iming. The idea is o use o se an S-R lach as a new bye becomes available. The oupu of his lach,, is sampled by FF1 in he domain. Since is no synchronized wih, FF1 s oupu SM may be measable, bu i is no used by FF2 unil he nex clock ick, 30 ns laer. Assuming ha he AND gae is reasonably fas, his gives pleny of measabiliy resoluion ime. FF2 s oupu is he signal. The AND gae ensures ha is only one period wide; if is already 1, i can be se o 1 on he nex ick. This gives ime for he S-R lach o be rese by in preparaion for he nex bye. A iming diagram for he overall circui wih ypical iming is shown in Figure Since is asynchronous o R, i can have an arbirary relaionship wih R and. In he figure, we ve shown a case where he nex rising edge occurs well afer is se. Alhough he figure shows a window in which SM and SM1 could be measable in he general case, measabiliy doesn acually happen when he iming is as drawn. Laer, we ll show wha can happen if he edge occurs when is changing. We should make several noes abou he circui in Figure Firs, he signal mus be glich-free, since i conrols he S inpu of a lach, and i mus be wide enough o mee he minimum pulse widh requiremen of he lach. SM SM1 Figure S Q D Q D Q SCTRL circui for R generaing. FF1 FF2

4 Secion 8.9 Synchronizer Failure and Measabiliy ns 80 ns R 30 ns SBYTE r pd su SM SM1 Figure Timing for he SCTRL SD circui in Figure Since he lach is se on he leading edge of, we acually cheaed a lile; may be assered a lile before a new bye is acually available in HREG. This is OK, because we know ha i akes wo periods from when is sampled unil SREG is loaded. In fac, we migh have cheaed even more if an earlier version of was available (see Exercise 8.76). Assuming ha su is he seup ime of a D flip-flop and pd is he propagaion delay of he AND gae in Figure 8-106, he available measabiliy resoluion ime r is one period, 30 ns, minus su + pd, as shown in Figure The iming diagram also shows why we can use SM direcly as he rese signal for he S-R lach. Since SM can be measable, i could wreak havoc. For example, i could be semi-high long enough o rese he lach bu hen fall back o LOW; in ha case, would no ge se and we would miss a bye. By using insead he oupu of he synchronizer () boh for he lach rese and for he load signal in he domain, we ensure ha he new bye is deeced and handled consisenly in boh clock domains. The iming ha we showed in Figure is nominal, bu we also have o analyze wha happens if has a differen phase relaionship wih R and han wha is shown. You should be able o convince yourself ha if he edge occurs earlier, so ha i sample jus as i s going HIGH, everyhing sill works as before, and he daa ransfer jus finishes a lile sooner. The more ineresing case is when occurs laer, so ha i jus misses as i s going HIGH, and caches i one period laer. This iming is shown in Figure

5 680 Chaper 8 Sequenial Logic Design Pracices sar end R 8 R R SBYTE goes LOW before deeced SM1 nex bye is missed SD in Figure Maximum-delay iming for SCTRL circui. In he iming diagram, we have shown going high around he same ime as he edge less han FF1 s su before he edge. Thus, FF1 may no see as HIGH or is oupu may become measable, and i does no solidly capure unil one period laer. Two periods afer ha, we ge he edge ha loads SBYTE ino SREG. This iming scenario is bad news, because by he ime he load occurs, SBYTE is already changing o he nex received bye. In addiion, happens o be assered during and a lile bi afer he pulse for his nex received bye. Thus, he lach has boh S and R assered simulaneously. If hey are removed simulaneously, he lach oupu may become measable. Or, as we ve shown in he iming diagram, if (R) is negaed las, hen he lach is lef in he rese sae, and his nex received bye is never deeced and loaded ino he domain. Thus, we need o analyze he maximum-delay iming case carefully o deermine if a synchronizer will work properly. Figure shows a saring reference poin sar for he SCTRL circui, namely he R edge on which a bye is loaded ino HREG, a end of pulse). The ending reference poin end is he edge on which SBYTE is loaded ino SREG. The maximum delay beween hese wo reference poins, which we ll call maxd, is he sum of he following componens: R Minus one R period, he delay from sar back o he edge on which was assered. This number is negaive because is assered one clock ick before he ick ha acually loads HREG.

6 Secion 8.9 Synchronizer Failure and Measabiliy 681 CQ One flip-flop -o-q maximum delay. Assuming ha is a direc flip-flop oupu in he R domain, his is delay from he R edge unil is assered. SQ Maximum delay from S o Q in he S-R lach in Figure This is he delay for o be assered. su Seup ime of FF1 in Figure mus be assered a or before he seup ime o guaranee deecion. One period. Since R and are asynchronous, here may be a delay of up o one period before he nex edge comes along o sample. Afer is deeced by FF1, is assered on he nex ick. Afer is assered, SBYTE is loaded ino SREG on he nex ick. Thus, maxd = 3 + CQ + SQ + su R. A few oher parameers mus be defined o complee he analysis: h The hold ime of SREG. CQ(min) The minimum -o-q delay of HREG, conservaively assumed o be 0. rec The recovery ime of he S-R lach, he minimum ime allowed beween negaing S and negaing R (see box on page 441). To be loaded successfully ino SREG, SBYTE mus be remain unil a leas ime end + h. The poin a which SBYTE changes and becomes in is 8 R periods afer sar, plus CQ(min). Thus, for proper circui operaion we mus have end + h sar + 8 R For he maximum-delay case, we subsiue end = sar + maxd ino his relaion and subrac sar from boh sides o obain maxd + h 8 R Subsiuing he value of maxd and rearranging, we obain 3 + CQ + SQ + su + h 9 R (8-1) as he requiremen for correc circui operaion. Too bad. Even if we assume very shor componen delays ( CQ, SQ, su, h ), we know ha 3 (90 ns) plus anyhing is going o be more han 9 R (also 90 ns). So his design will never work properly in he maximum-delay case. Even if he load-delay analysis gave a good resul, we would sill have o consider he requiremens for proper operaion of he SCTRL circui iself. In paricular, we mus ensure ha when he pulse for he nex bye occurs, i

7 682 Chaper 8 Sequenial Logic Design Pracices is no negaed unil ime rec afer for he previous bye was negaed. So, anoher condiion for proper operaion is end + CQ + rec sar + 8 R + CQ(min) Subsiuing and simplifying as before, we ge anoher requiremen ha isn me by our design: CQ + SQ + su + rec 9 R (8-2) There are several ways ha we can modify our design o saisfy he worscase iming requiremens. Early in our discussion, we noed ha we cheaed by assering one R period before he daa in HREG is, and ha we acually migh ge away wih assering even soon. Doing his can help us mee he maximum delay requiremen, because i reduces he 8 R erm on he righ-hand side of he relaions. For example, if we assered wo R periods earlier, we would reduce his erm o 6 R. However, here s no free lunch, we can asser arbirarily early. We mus also consider a minimum delay case, o ensure ha he new bye is acually available in HREG when SBYTE is loaded ino SREG. The minimum delay maxd beween sar and end is he sum of he following componens: n R Minus n R periods, he delay from sar back o he edge on which was assered. In he original design, n = 1. CQ(min) This is he minimum delay from he R edge unil is assered, conservaively assumed o be 0. SQ This is he delay for o be assered, again assumed o be 0. h Minus he hold ime of FF1 in Figure migh be assered a he end of he hold ime and sill be deeced. 0 Zero imes he period. We migh ge lucky and have he edge come along jus as he hold ime of FF1 is ending. A one--period delay o assering, as before. A one--period delay o loading SBYTE ino SREG, as before. In oher words, mind = 2 h n R. For his case, we mus ensure ha he new bye has propagaed o he oupu of HREG when he seup ime window of SREG begins, so we mus have end su sar + co, where co is he maximum clock-o-oupu delay of HREG. Subsiuing end = sar + mind and subracing sar from boh sides, we ge mind su co. Subsiuing he value of mind and rearranging, we ge he final requiremen, 2 h su co n R (8-3)

8 Secion 8.9 Synchronizer Failure and Measabiliy 683 If, for example, h, su, and co are 10 ns each, he maximum value of n is 3; we can generae more han wo clock icks before is original posiion in Figure This may or may no be enough o solve he maximum-delay problem, depending on oher delay values; his is explored for a paricular se of componens in Exercise Moving he pulse earlier may no give enough delay improvemen or may no be an available opion in some sysems. An alernaive soluion ha can always be made o work is o increasing he ime beween successive daa ransfers from one clock domain o he oher. We can always do his because we can always ransfer more bis per synchronizaion. In he Eherne-inerface example, we could collec 16 bis a a ime in he R domain and ransfer 16 bis a a ime o he domain. This changes he previously saed 8 R erms o 16 R, providing a lo more margin for he maximum-delay iming requiremens. Once 16 bis have been ransferred ino he domain, we can sill break hem ino wo 8-bi chunks if we need o process he daa a bye a a ime. I may also be possible o improve performance by modifying he design of he SCTRL circui. Figure shows a version where is generaed direcly by he flip-flop ha samples. In his way, appears one period sooner han in our original SCTRL circui. Also, he S-R lach is cleared sooner. This circui works only if a couple of key assumpions are rue: 1. A reduced measabiliy resoluion ime for FF1 is accepable, equal o he ime ha is HIGH. Measabiliy mus be resolved before goes LOW, because ha s when he S-R lach ges cleared if is HIGH. 2. The seup ime of SREG s EN inpu (Figure 8-102) is less han or equal o he ime ha is LOW. Under he previous assumpion, he signal applied o EN migh be measable unil goes LOW. 3. The ime ha is LOW is long enough o generae a rese pulse on RNEW ha mees he minimum pulse-widh requiremen of he S-R lach. Noe ha hese behaviors makes proper circui operaion dependen on he duy cycle of. If is relaively slow and is duy cycle is close o 50%, his circui generally works fine. Bu if is oo fas or has a very small, very large, or unpredicable duy cycle, he original circui approach mus be used. S Q D Q RNEW R Figure Half-clock-period FF1 SCTRL circui for generaing.

9 684 Chaper 8 Sequenial Logic Design Pracices All of hese synchronizaion schemes require he clock frequencies o be wihin a cerain range of each oher for proper circui operaion. This mus be considered for esing, where he clocks are usually run slower, and for upgrades, where one or boh clocks may run faser. For example, in he Eherne inerface example, we wouldn change he frequency of sandard 100-Mbps Eherne, bu we migh upgrade he PCI bus from 33 o 66 MHz. The problems caused by clock frequency changes can be suble. To ge a beer handle on wha can go wrong, i s useful o consider how a synchronizer works (or doesn work!) if one clock frequency changes by a facor of 10 or more. For example wha happens o he synchronizer iming in Figure if we change R from 100 MHz o 10 MHz? A firs glance, i would seem ha all is well, since a bye now arrives only once every 800 ns, giving much more ime for he bye o be ransferred ino he domain. Cerainly, Eqn. 8-1 on page 681 and Eqn. 8-2 on page 682 are saisfied wih much more margin. However, Eqn. 8-3 is no longer saisfied unless we reduce n o zero! This could be accomplished by generaing one R ick laer han is shown in Figure Bu even wih his change, here s sill a problem. Figure shows he new iming, including he laer pulse. The problem is ha he pulse is now 100 ns long. As before, (he oupu of he S-R lach in Figure Synchronizer iming wih slow (10 MHz) R. 100 ns R 30 ns SBYTE SM SM1

10 Secion 8.9 Synchronizer Failure and Measabiliy 685 SM SM1 1 D Q D Q D Q Figure CLR Synchronizer wih FF1 FF2 edge-riggered deecion. Figure on page 678) is se by and is cleared by. The problem is ha when goes away, is sill assered, as shown in he new iming diagram. Thus, he new bye will be deeced and ransferred wice! The soluion o he problem is o deec only he leading edge of, so ha he circui is no sensiive o he lengh of he pulse. A common way of doing his is o replace he S-R lach wih an edge-riggered D flip-flop, as shown in Figure The leading edge of ses he flip-flop, while is used as an asynchronous clear as before. The circui in Figure solves he slow-r problem, bu i also changes he derivaion of Eqns. 8-1 hrough 8-3 and may make iming more consrained in some areas (see Exercise 8.77). Anoher disadvanage ha his circui canno be realized in a ypical PLD, which has all flip-flops conrolled by he same clock; insead, a discree flip-flop mus be used o deec. Afer reading almos 10 pages o analyze jus one simple example, you should have a srong appreciaion of he difficuly of correc synchronizaioncircui design. Several guidelines can help you: Minimize he number of differen clock domains in a sysem. Clearly idenify all clock boundaries and provide clearly idenified synchronizers a hose boundaries. Provide sufficien measabiliy resoluion ime for each synchronizer so ha synchronizer failure is rare, much more unlikely han oher hardware failures. Analyze synchronizer behavior over a range of iming scenarios, including faser and slower clocks ha migh be applied as a resul of sysem esing or upgrades. Simulae sysem behavior over a wide range of iming scenarios as well. The las guideline above is a cach-all for modern digial designers, who usually rely on sophisicaed, high-speed logic simulaors o find heir bugs. Bu i s no a subsiue for following he firs four guidelines. Ignoring hem can lead o problems ha canno be deeced by a ypical, small number of simulaion scenarios. Of all digial circuis, synchronizers are he ones for which i s mos imporan o be correc by design!